* [PATCH v3 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s
@ 2025-06-25 8:57 Ziyue Zhang
2025-06-25 8:57 ` [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Ziyue Zhang @ 2025-06-25 8:57 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani,
lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon,
neil.armstrong, abel.vesa, kw
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy,
qiang.yu, quic_krichai, quic_vbadigan, Ziyue Zhang
This series adds add equalization settings for 8.0 GT/s, and add PCIe lane equalization
preset properties for 8.0 GT/s and 16.0 GT/s for sa8775p ride platform, which fix AER
errors.
While equalization settings for 16 GT/s have already been set, this update adds the
required equalization settings for PCIe operating at 8.0 GT/s, including the
configuration of shadow registers, ensuring optimal performance and stability.
The DT change for sa8775p add PCIe lane equalization preset properties for 8 GT/s
and 16 GT/s data rates used in lane equalization procedure.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Changes in v2:
- Update code in pcie-qcom-common.c make it easier to read. (Neil)
- Fix the compile error.
- Link to v1: https://lore.kernel.org/all/20250604091946.1890602-1-quic_ziyuzhan@quicinc.com
Changes in v3:
- Delte TODO tag and warn print in pcie-qcom-common.c. (Bjorn)
- Refined the commit message for better readability. (Bjorn)
- Link to v2: https://lore.kernel.org/all/20250611100319.464803-1-quic_ziyuzhan@quicinc.com/
Ziyue Zhang (3):
PCI: qcom: Add equalization settings for 8.0 GT/s
PCI: qcom: fix macro typo for CURSOR
arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset
properties
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++
drivers/pci/controller/dwc/pcie-designware.h | 5 +-
drivers/pci/controller/dwc/pcie-qcom-common.c | 55 +++++++++++--------
drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +-
drivers/pci/controller/dwc/pcie-qcom.c | 6 +-
6 files changed, 46 insertions(+), 34 deletions(-)
base-commit: e04c78d86a9699d136910cfc0bdcf01087e3267e
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s 2025-06-25 8:57 [PATCH v3 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s Ziyue Zhang @ 2025-06-25 8:57 ` Ziyue Zhang 2025-06-25 15:58 ` Manivannan Sadhasivam 2025-06-25 19:15 ` kernel test robot 2025-06-25 8:58 ` [PATCH v3 2/3] PCI: qcom: fix macro typo for CURSOR Ziyue Zhang 2025-06-25 8:58 ` [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties Ziyue Zhang 2 siblings, 2 replies; 7+ messages in thread From: Ziyue Zhang @ 2025-06-25 8:57 UTC (permalink / raw) To: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani, lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon, neil.armstrong, abel.vesa, kw Cc: linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai, quic_vbadigan, Ziyue Zhang Add lane equalization setting for 8.0 GT/s to enhance link stability and aviod AER Correctable Errors reported on some platforms (eg. SA8775P). 8.0 GT/s and 16.0 GT/s require the same equalization setting. This setting is programmed into a group of shadow registers, which can be switched to configure equalization for different speeds by writing 00b, 01b to `RATE_SHADOW_SEL`. Hence program equalization registers in a loop using link speed as index, so that equalization setting can be programmed for both 8.0 GT/s and 16.0 GT/s. Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> --- drivers/pci/controller/dwc/pcie-designware.h | 1 - drivers/pci/controller/dwc/pcie-qcom-common.c | 55 +++++++++++-------- drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +- drivers/pci/controller/dwc/pcie-qcom.c | 6 +- 5 files changed, 38 insertions(+), 32 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ce9e18554e42..388306991467 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -127,7 +127,6 @@ #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 #define GEN3_EQ_CONTROL_OFF 0x8A8 #define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c index 3aad19b56da8..ed466496f077 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -8,9 +8,11 @@ #include "pcie-designware.h" #include "pcie-qcom-common.h" -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) +void qcom_pcie_common_set_equalization(struct dw_pcie *pci) { u32 reg; + u16 speed, max_speed = PCIE_SPEED_16_0GT; + struct device *dev = pci->dev; /* * GEN3_RELATED_OFF register is repurposed to apply equalization @@ -19,32 +21,37 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) * determines the data rate for which these equalization settings are * applied. */ - reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); + if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT) + max_speed = pcie_link_speed[pci->max_link_speed]; - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); - reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | - GEN3_EQ_FMDC_N_EVALS | - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); - reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); + for (speed = PCIE_SPEED_8_0GT; speed <= max_speed; ++speed) { + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + speed - PCIE_SPEED_8_0GT); + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | + GEN3_EQ_FMDC_N_EVALS | + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); + + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); + } } -EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) { diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h index 7d88d29e4766..7f5ca2fd9a72 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.h +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h @@ -8,7 +8,7 @@ struct dw_pcie; -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); +void qcom_pcie_common_set_equalization(struct dw_pcie *pci); void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); #endif diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index bf7c6ac0f3e3..aaf060bf39d4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -511,10 +511,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) goto err_disable_resources; } - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { - qcom_pcie_common_set_16gt_equalization(pci); + qcom_pcie_common_set_equalization(pci); + + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) qcom_pcie_common_set_16gt_lane_margining(pci); - } /* * The physical address of the MMIO region which is exposed as the BAR diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c789e3f85655..0fcb17ffd2e9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -298,10 +298,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { - qcom_pcie_common_set_16gt_equalization(pci); + qcom_pcie_common_set_equalization(pci); + + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) qcom_pcie_common_set_16gt_lane_margining(pci); - } /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s 2025-06-25 8:57 ` [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang @ 2025-06-25 15:58 ` Manivannan Sadhasivam 2025-06-30 7:19 ` Ziyue Zhang 2025-06-25 19:15 ` kernel test robot 1 sibling, 1 reply; 7+ messages in thread From: Manivannan Sadhasivam @ 2025-06-25 15:58 UTC (permalink / raw) To: Ziyue Zhang Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon, neil.armstrong, abel.vesa, kw, linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai, quic_vbadigan On Wed, Jun 25, 2025 at 04:57:59PM +0800, Ziyue Zhang wrote: > Add lane equalization setting for 8.0 GT/s to enhance link stability and > aviod AER Correctable Errors reported on some platforms (eg. SA8775P). > > 8.0 GT/s and 16.0 GT/s require the same equalization setting. This > setting is programmed into a group of shadow registers, which can be > switched to configure equalization for different speeds by writing 00b, > 01b to `RATE_SHADOW_SEL`. > > Hence program equalization registers in a loop using link speed as index, > so that equalization setting can be programmed for both 8.0 GT/s and > 16.0 GT/s. > > Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-designware.h | 1 - > drivers/pci/controller/dwc/pcie-qcom-common.c | 55 +++++++++++-------- > drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +- > drivers/pci/controller/dwc/pcie-qcom.c | 6 +- > 5 files changed, 38 insertions(+), 32 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index ce9e18554e42..388306991467 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -127,7 +127,6 @@ > #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) > #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 > #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) > -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 > > #define GEN3_EQ_CONTROL_OFF 0x8A8 > #define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c > index 3aad19b56da8..ed466496f077 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-common.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c > @@ -8,9 +8,11 @@ > #include "pcie-designware.h" > #include "pcie-qcom-common.h" > > -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) > +void qcom_pcie_common_set_equalization(struct dw_pcie *pci) > { > u32 reg; > + u16 speed, max_speed = PCIE_SPEED_16_0GT; > + struct device *dev = pci->dev; > > /* > * GEN3_RELATED_OFF register is repurposed to apply equalization > @@ -19,32 +21,37 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) > * determines the data rate for which these equalization settings are > * applied. > */ > - reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > - reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, > - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > + if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT) > + max_speed = pcie_link_speed[pci->max_link_speed]; So the logic here is that you want to limit the max_speed to < 32 GT/s because you are not sure if 32 GT/s or more would require the same settings? If so, why can't you just simply bail out early if the link speed > 16 GT/s and just use pci->max_link_speed directly? Right now, 32 GT/s or more would be skipped implicitly because you have initialized max_speed to PCIE_SPEED_16_0GT. - Mani > > - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > - reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > - GEN3_EQ_FMDC_N_EVALS | > - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > - reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > + for (speed = PCIE_SPEED_8_0GT; speed <= max_speed; ++speed) { > + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, > + speed - PCIE_SPEED_8_0GT); > + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > > - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > - reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > + GEN3_EQ_FMDC_N_EVALS | > + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > + > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > + } > } > -EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); > +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); > > void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) > { > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h > index 7d88d29e4766..7f5ca2fd9a72 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-common.h > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h > @@ -8,7 +8,7 @@ > > struct dw_pcie; > > -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); > +void qcom_pcie_common_set_equalization(struct dw_pcie *pci); > void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); > > #endif > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index bf7c6ac0f3e3..aaf060bf39d4 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -511,10 +511,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) > goto err_disable_resources; > } > > - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { > - qcom_pcie_common_set_16gt_equalization(pci); > + qcom_pcie_common_set_equalization(pci); > + > + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) > qcom_pcie_common_set_16gt_lane_margining(pci); > - } > > /* > * The physical address of the MMIO region which is exposed as the BAR > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index c789e3f85655..0fcb17ffd2e9 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -298,10 +298,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) > { > struct qcom_pcie *pcie = to_qcom_pcie(pci); > > - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { > - qcom_pcie_common_set_16gt_equalization(pci); > + qcom_pcie_common_set_equalization(pci); > + > + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) > qcom_pcie_common_set_16gt_lane_margining(pci); > - } > > /* Enable Link Training state machine */ > if (pcie->cfg->ops->ltssm_enable) > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s 2025-06-25 15:58 ` Manivannan Sadhasivam @ 2025-06-30 7:19 ` Ziyue Zhang 0 siblings, 0 replies; 7+ messages in thread From: Ziyue Zhang @ 2025-06-30 7:19 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon, neil.armstrong, abel.vesa, kw, linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai, quic_vbadigan On 6/25/2025 11:58 PM, Manivannan Sadhasivam wrote: > On Wed, Jun 25, 2025 at 04:57:59PM +0800, Ziyue Zhang wrote: >> Add lane equalization setting for 8.0 GT/s to enhance link stability and >> aviod AER Correctable Errors reported on some platforms (eg. SA8775P). >> >> 8.0 GT/s and 16.0 GT/s require the same equalization setting. This >> setting is programmed into a group of shadow registers, which can be >> switched to configure equalization for different speeds by writing 00b, >> 01b to `RATE_SHADOW_SEL`. >> >> Hence program equalization registers in a loop using link speed as index, >> so that equalization setting can be programmed for both 8.0 GT/s and >> 16.0 GT/s. >> >> Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> >> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> >> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-designware.h | 1 - >> drivers/pci/controller/dwc/pcie-qcom-common.c | 55 +++++++++++-------- >> drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +- >> drivers/pci/controller/dwc/pcie-qcom.c | 6 +- >> 5 files changed, 38 insertions(+), 32 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index ce9e18554e42..388306991467 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -127,7 +127,6 @@ >> #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) >> #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 >> #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) >> -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 >> >> #define GEN3_EQ_CONTROL_OFF 0x8A8 >> #define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c >> index 3aad19b56da8..ed466496f077 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-common.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c >> @@ -8,9 +8,11 @@ >> #include "pcie-designware.h" >> #include "pcie-qcom-common.h" >> >> -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) >> +void qcom_pcie_common_set_equalization(struct dw_pcie *pci) >> { >> u32 reg; >> + u16 speed, max_speed = PCIE_SPEED_16_0GT; >> + struct device *dev = pci->dev; >> >> /* >> * GEN3_RELATED_OFF register is repurposed to apply equalization >> @@ -19,32 +21,37 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) >> * determines the data rate for which these equalization settings are >> * applied. >> */ >> - reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); >> - reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; >> - reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; >> - reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, >> - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); >> - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); >> + if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT) >> + max_speed = pcie_link_speed[pci->max_link_speed]; > So the logic here is that you want to limit the max_speed to < 32 GT/s because > you are not sure if 32 GT/s or more would require the same settings? > > If so, why can't you just simply bail out early if the link speed > 16 GT/s and > just use pci->max_link_speed directly? Right now, 32 GT/s or more would be > skipped implicitly because you have initialized max_speed to PCIE_SPEED_16_0GT. > > - Mani Hi Mani I'll update the code according to your feedback in my next submission. BRs Ziyue >> >> - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); >> - reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | >> - GEN3_EQ_FMDC_N_EVALS | >> - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | >> - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); >> - reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | >> - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | >> - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | >> - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); >> - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); >> + for (speed = PCIE_SPEED_8_0GT; speed <= max_speed; ++speed) { >> + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); >> + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; >> + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; >> + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, >> + speed - PCIE_SPEED_8_0GT); >> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); >> >> - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); >> - reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | >> - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | >> - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | >> - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); >> - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); >> + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); >> + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | >> + GEN3_EQ_FMDC_N_EVALS | >> + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | >> + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); >> + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | >> + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | >> + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | >> + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); >> + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); >> + >> + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); >> + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | >> + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | >> + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | >> + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); >> + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); >> + } >> } >> -EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); >> +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); >> >> void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) >> { >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h >> index 7d88d29e4766..7f5ca2fd9a72 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-common.h >> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h >> @@ -8,7 +8,7 @@ >> >> struct dw_pcie; >> >> -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); >> +void qcom_pcie_common_set_equalization(struct dw_pcie *pci); >> void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); >> >> #endif >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> index bf7c6ac0f3e3..aaf060bf39d4 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> @@ -511,10 +511,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) >> goto err_disable_resources; >> } >> >> - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { >> - qcom_pcie_common_set_16gt_equalization(pci); >> + qcom_pcie_common_set_equalization(pci); >> + >> + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) >> qcom_pcie_common_set_16gt_lane_margining(pci); >> - } >> >> /* >> * The physical address of the MMIO region which is exposed as the BAR >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index c789e3f85655..0fcb17ffd2e9 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -298,10 +298,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) >> { >> struct qcom_pcie *pcie = to_qcom_pcie(pci); >> >> - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { >> - qcom_pcie_common_set_16gt_equalization(pci); >> + qcom_pcie_common_set_equalization(pci); >> + >> + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) >> qcom_pcie_common_set_16gt_lane_margining(pci); >> - } >> >> /* Enable Link Training state machine */ >> if (pcie->cfg->ops->ltssm_enable) >> -- >> 2.34.1 >> ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s 2025-06-25 8:57 ` [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang 2025-06-25 15:58 ` Manivannan Sadhasivam @ 2025-06-25 19:15 ` kernel test robot 1 sibling, 0 replies; 7+ messages in thread From: kernel test robot @ 2025-06-25 19:15 UTC (permalink / raw) To: Ziyue Zhang, andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani, lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon, neil.armstrong, abel.vesa, kw Cc: llvm, oe-kbuild-all, linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai, quic_vbadigan, Ziyue Zhang Hi Ziyue, kernel test robot noticed the following build warnings: [auto build test WARNING on e04c78d86a9699d136910cfc0bdcf01087e3267e] url: https://github.com/intel-lab-lkp/linux/commits/Ziyue-Zhang/PCI-qcom-Add-equalization-settings-for-8-0-GT-s/20250625-170049 base: e04c78d86a9699d136910cfc0bdcf01087e3267e patch link: https://lore.kernel.org/r/20250625085801.526669-2-quic_ziyuzhan%40quicinc.com patch subject: [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s config: i386-buildonly-randconfig-002-20250626 (https://download.01.org/0day-ci/archive/20250626/202506260310.BUxJgnmS-lkp@intel.com/config) compiler: clang version 20.1.7 (https://github.com/llvm/llvm-project 6146a88f60492b520a36f8f8f3231e15f3cc6082) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250626/202506260310.BUxJgnmS-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202506260310.BUxJgnmS-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/pci/controller/dwc/pcie-qcom-common.c:15:17: warning: unused variable 'dev' [-Wunused-variable] 15 | struct device *dev = pci->dev; | ^~~ 1 warning generated. vim +/dev +15 drivers/pci/controller/dwc/pcie-qcom-common.c 10 11 void qcom_pcie_common_set_equalization(struct dw_pcie *pci) 12 { 13 u32 reg; 14 u16 speed, max_speed = PCIE_SPEED_16_0GT; > 15 struct device *dev = pci->dev; 16 17 /* 18 * GEN3_RELATED_OFF register is repurposed to apply equalization 19 * settings at various data transmission rates through registers namely 20 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF 21 * determines the data rate for which these equalization settings are 22 * applied. 23 */ 24 if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT) 25 max_speed = pcie_link_speed[pci->max_link_speed]; 26 27 for (speed = PCIE_SPEED_8_0GT; speed <= max_speed; ++speed) { 28 reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 29 reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 30 reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 31 reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 32 speed - PCIE_SPEED_8_0GT); 33 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); 34 35 reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); 36 reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | 37 GEN3_EQ_FMDC_N_EVALS | 38 GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | 39 GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); 40 reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | 41 FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | 42 FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | 43 FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); 44 dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); 45 46 reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 47 reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | 48 GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | 49 GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | 50 GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); 51 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); 52 } 53 } 54 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); 55 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] PCI: qcom: fix macro typo for CURSOR 2025-06-25 8:57 [PATCH v3 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s Ziyue Zhang 2025-06-25 8:57 ` [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang @ 2025-06-25 8:58 ` Ziyue Zhang 2025-06-25 8:58 ` [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties Ziyue Zhang 2 siblings, 0 replies; 7+ messages in thread From: Ziyue Zhang @ 2025-06-25 8:58 UTC (permalink / raw) To: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani, lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon, neil.armstrong, abel.vesa, kw Cc: linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai, quic_vbadigan, Ziyue Zhang Corrected a typo in the macro name GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA and GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA to ensure consistency and avoid potential issues. Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> --- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- drivers/pci/controller/dwc/pcie-qcom-common.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 388306991467..80831f99d72d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -137,8 +137,8 @@ #define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8AC #define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0) #define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5) -#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10) -#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14) +#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10) +#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14) #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c index ed466496f077..86ed86b72d5a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -35,12 +35,12 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci) reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | GEN3_EQ_FMDC_N_EVALS | - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); + GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA | + GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA); reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5); dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties 2025-06-25 8:57 [PATCH v3 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s Ziyue Zhang 2025-06-25 8:57 ` [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang 2025-06-25 8:58 ` [PATCH v3 2/3] PCI: qcom: fix macro typo for CURSOR Ziyue Zhang @ 2025-06-25 8:58 ` Ziyue Zhang 2 siblings, 0 replies; 7+ messages in thread From: Ziyue Zhang @ 2025-06-25 8:58 UTC (permalink / raw) To: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani, lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon, neil.armstrong, abel.vesa, kw Cc: linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai, quic_vbadigan, Ziyue Zhang, Konrad Dybcio Add PCIe lane equalization preset properties with all values set to 5 for 8.0 GT/s and 16.0 GT/s data rates to enhance link stability. Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 45f536633f64..16caf1da0708 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7159,6 +7159,9 @@ pcie0: pcie@1c00000 { phys = <&pcie0_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; pcieport0: pcie@0 { @@ -7317,6 +7320,9 @@ pcie1: pcie@1c10000 { phys = <&pcie1_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; pcie@0 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-06-30 7:19 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-06-25 8:57 [PATCH v3 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s Ziyue Zhang 2025-06-25 8:57 ` [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s Ziyue Zhang 2025-06-25 15:58 ` Manivannan Sadhasivam 2025-06-30 7:19 ` Ziyue Zhang 2025-06-25 19:15 ` kernel test robot 2025-06-25 8:58 ` [PATCH v3 2/3] PCI: qcom: fix macro typo for CURSOR Ziyue Zhang 2025-06-25 8:58 ` [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties Ziyue Zhang
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