* [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist
@ 2025-11-26 21:31 Anna Maniscalco
2025-11-26 21:34 ` Akhil P Oommen
2025-11-26 21:42 ` Dmitry Baryshkov
0 siblings, 2 replies; 3+ messages in thread
From: Anna Maniscalco @ 2025-11-26 21:31 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Akhil P Oommen,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, stable,
Anna Maniscalco
Previously this register would become 0 after IFPC took place which
broke all usages of counters.
Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
---
Changes in v2:
- Added Fixes tag
- Link to v1: https://lore.kernel.org/r/20251126-ifpc_counters-v1-1-f2d5e7048032@gmail.com
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 29107b362346..b731491dc522 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = {
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
+ REG_A6XX_RBBM_PERFCTR_CNTL,
REG_A6XX_TPL1_NC_MODE_CNTL,
REG_A6XX_SP_NC_MODE_CNTL,
REG_A6XX_CP_DBG_ECO_CNTL,
---
base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
change-id: 20251126-ifpc_counters-e8d53fa3252e
Best regards,
--
Anna Maniscalco <anna.maniscalco2000@gmail.com>
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist
2025-11-26 21:31 [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist Anna Maniscalco
@ 2025-11-26 21:34 ` Akhil P Oommen
2025-11-26 21:42 ` Dmitry Baryshkov
1 sibling, 0 replies; 3+ messages in thread
From: Akhil P Oommen @ 2025-11-26 21:34 UTC (permalink / raw)
To: Anna Maniscalco, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, stable
On 11/27/2025 3:01 AM, Anna Maniscalco wrote:
> Previously this register would become 0 after IFPC took place which
> broke all usages of counters.
>
> Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
> Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
-Akhil
> ---
> Changes in v2:
> - Added Fixes tag
> - Link to v1: https://lore.kernel.org/r/20251126-ifpc_counters-v1-1-f2d5e7048032@gmail.com
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 29107b362346..b731491dc522 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = {
> REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
> REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
> REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
> + REG_A6XX_RBBM_PERFCTR_CNTL,
> REG_A6XX_TPL1_NC_MODE_CNTL,
> REG_A6XX_SP_NC_MODE_CNTL,
> REG_A6XX_CP_DBG_ECO_CNTL,
>
> ---
> base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
> change-id: 20251126-ifpc_counters-e8d53fa3252e
>
> Best regards,
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist
2025-11-26 21:31 [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist Anna Maniscalco
2025-11-26 21:34 ` Akhil P Oommen
@ 2025-11-26 21:42 ` Dmitry Baryshkov
1 sibling, 0 replies; 3+ messages in thread
From: Dmitry Baryshkov @ 2025-11-26 21:42 UTC (permalink / raw)
To: Anna Maniscalco
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Akhil P Oommen,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, linux-arm-msm, dri-devel, freedreno,
linux-kernel, stable
On Wed, Nov 26, 2025 at 10:31:30PM +0100, Anna Maniscalco wrote:
> Previously this register would become 0 after IFPC took place which
> broke all usages of counters.
>
> Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
> Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
> ---
> Changes in v2:
> - Added Fixes tag
Cc: stable@vger.kernel.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> - Link to v1: https://lore.kernel.org/r/20251126-ifpc_counters-v1-1-f2d5e7048032@gmail.com
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
> 1 file changed, 1 insertion(+)
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-11-26 21:31 [PATCH v2] drm/msm: add PERFCTR_CNTL to ifpc_reglist Anna Maniscalco
2025-11-26 21:34 ` Akhil P Oommen
2025-11-26 21:42 ` Dmitry Baryshkov
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