* [PATCH v2 0/3] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT
@ 2026-01-03 13:45 Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 1/3] drm/msm/dpu: Check mode against PINGPONG or DSC max width Dmitry Baryshkov
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2026-01-03 13:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Jessica Zhang,
Xilin Wu
Currently, the DPU driver bases LM reservation off of the maximum
supported width for the layer mixer and an arbitrary MAX_HDISPLAY_SPLIT.
However, these limits are not hardware limits meaning that a single LM
can support higher resolutions.
Switch to basing LM reservation off of PINGPONG and DSC encoder hardware
limits.
---
Changes in v2:
- Dropped PP and DSC encoder width drop the catalog, they are now
determined in the code by using the DPU programming
- Corrected DSC encoder width for DPUs < 8.x (2048 vs 2560)
- Link to v1: https://lore.kernel.org/r/20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com
---
Jessica Zhang (3):
drm/msm/dpu: Check mode against PINGPONG or DSC max width
drm/msm/dpu: Filter writeback modes using writeback maxlinewidth
drm/msm/dpu: Remove max_mixer_width from catalog
.../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 -
.../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 44 ++++++++++++++++++----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 9 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +----
33 files changed, 45 insertions(+), 47 deletions(-)
---
base-commit: 19eee9de953679506fd24a2db2613e165c6fe801
change-id: 20250401-max-mixer-width-9c3c02c48cb7
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 1/3] drm/msm/dpu: Check mode against PINGPONG or DSC max width
2026-01-03 13:45 [PATCH v2 0/3] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT Dmitry Baryshkov
@ 2026-01-03 13:45 ` Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 2/3] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 3/3] drm/msm/dpu: Remove max_mixer_width from catalog Dmitry Baryshkov
2 siblings, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2026-01-03 13:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Jessica Zhang,
Xilin Wu
From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Validate requested mode and topology based on the PINGPONG or DSC encoder
max width. In addition, drop MAX_HDISPLAY_SPLIT and base LM reservation
off of PINGPONG or DSC encoder max width
As noted in the patch, while DPU 8.x+ supports a max linewidth of 8960
for PINGPONG_0, there is some additional logic that needs to be added to
the resource manager to specifically try and reserve PINGPONG_0 for
modes that are greater than 5k.
Since this is out of the scope of this series, add a helper that will
get the overall minimum PINGPONG max linewidth for a given chipset.
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 44 ++++++++++++++++++++++----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 ++++
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index c39f1908ea65..0b74d85a6142 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -762,6 +762,22 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc)
_dpu_crtc_complete_flip(crtc);
}
+static int msm_display_get_max_pingpong_width(struct dpu_kms *dpu_kms)
+{
+ /*
+ * Note: While, for DPU 8.x+, PINGPONG_0 can technically support up to
+ * 8k resolutions, this requires reworking the RM to try to reserve
+ * PINGPONG_0 for modes greater than 5k.
+ *
+ * Once this additional logic is implemented, we can probably drop this
+ * helper and use the reserved PINGPONG's max_linewidth
+ */
+ if (dpu_kms->catalog->mdss_ver->core_major_ver < 6)
+ return DPU_1_x_MAX_PINGPONG_WIDTH;
+ else
+ return DPU_6_x_MAX_PINGPONG_WIDTH;
+}
+
static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -769,13 +785,14 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_display_mode *adj_mode = &state->adjusted_mode;
u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
+ int max_pingpong_width = msm_display_get_max_pingpong_width(dpu_kms);
int i;
/* if we cannot merge 2 LMs (no 3d mux) better to fail earlier
* before even checking the width after the split
*/
if (!dpu_kms->catalog->caps->has_3d_merge &&
- adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
+ adj_mode->hdisplay > max_pingpong_width)
return -E2BIG;
for (i = 0; i < cstate->num_mixers; i++) {
@@ -787,7 +804,7 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
- if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width)
+ if (drm_rect_width(r) > max_pingpong_width)
return -E2BIG;
}
@@ -1318,7 +1335,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
}
#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
-#define MAX_HDISPLAY_SPLIT 1080
static struct msm_display_topology dpu_crtc_get_topology(
struct drm_crtc *crtc,
@@ -1328,6 +1344,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
struct msm_display_topology topology = {0};
struct drm_encoder *drm_enc;
+ u32 max_hdisplay_split;
u32 num_rt_intf;
drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
@@ -1335,6 +1352,18 @@ static struct msm_display_topology dpu_crtc_get_topology(
&crtc_state->adjusted_mode);
topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state);
+ max_hdisplay_split = msm_display_get_max_pingpong_width(dpu_kms);
+
+ if (topology.num_dsc > 0) {
+ u32 max_dsc_encoder_width;
+
+ if (dpu_kms->catalog->mdss_ver->core_major_ver < 6)
+ max_dsc_encoder_width = DPU_1_x_MAX_DSC_ENCODER_WIDTH;
+ else
+ max_dsc_encoder_width = DPU_8_x_MAX_DSC_ENCODER_WIDTH;
+
+ max_hdisplay_split = min(max_hdisplay_split, max_dsc_encoder_width);
+ }
/*
* Datapath topology selection
@@ -1358,7 +1387,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
* count both the WB and real-time phys encoders.
*
* For non-DSC CWB usecases, have the num_lm be decided by the
- * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
+ * (mode->hdisplay > max_hdisplay_split) check.
*/
num_rt_intf = topology.num_intf;
@@ -1374,7 +1403,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
} else if (num_rt_intf == 2) {
topology.num_lm = 2;
} else if (dpu_kms->catalog->caps->has_3d_merge) {
- topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
+ topology.num_lm = (mode->hdisplay > max_hdisplay_split) ? 2 : 1;
} else {
topology.num_lm = 1;
}
@@ -1553,13 +1582,14 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
const struct drm_display_mode *mode)
{
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
+ int max_pingpong_width = msm_display_get_max_pingpong_width(dpu_kms);
u64 adjusted_mode_clk;
/* if there is no 3d_mux block we cannot merge LMs so we cannot
* split the large layer into 2 LMs, filter out such modes
*/
if (!dpu_kms->catalog->caps->has_3d_merge &&
- mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
+ mode->hdisplay > max_pingpong_width)
return MODE_BAD_HVALUE;
adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock,
@@ -1579,7 +1609,7 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
* max crtc width is equal to the max mixer width * 2 and max height is 4K
*/
return drm_mode_validate_size(mode,
- 2 * dpu_kms->catalog->caps->max_mixer_width,
+ 2 * max_pingpong_width,
4096);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 336757103b5a..ee94d0ccb8a3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -24,6 +24,13 @@
#define DPU_MAX_IMG_WIDTH 0x3fff
#define DPU_MAX_IMG_HEIGHT 0x3fff
+#define DPU_1_x_MAX_PINGPONG_WIDTH 4096
+#define DPU_6_x_MAX_PINGPONG_WIDTH 5120
+#define DPU_8_x_MAX_PINGPONG_0_WIDTH 8960
+
+#define DPU_1_x_MAX_DSC_ENCODER_WIDTH 2048
+#define DPU_8_x_MAX_DSC_ENCODER_WIDTH 2560
+
#define CRTC_QUAD_MIXERS 4
#define MAX_XIN_COUNT 16
--
2.47.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/3] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth
2026-01-03 13:45 [PATCH v2 0/3] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 1/3] drm/msm/dpu: Check mode against PINGPONG or DSC max width Dmitry Baryshkov
@ 2026-01-03 13:45 ` Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 3/3] drm/msm/dpu: Remove max_mixer_width from catalog Dmitry Baryshkov
2 siblings, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2026-01-03 13:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Jessica Zhang
From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Since the max mixer width is not a strict hardware limit, use the actual
hardware limit (the writeback maxlinewidth) to filter modes.
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
index 7545c0293efb..209b1e27a84b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
@@ -14,14 +14,7 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector)
struct msm_drm_private *priv = dev->dev_private;
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
- /*
- * We should ideally be limiting the modes only to the maxlinewidth but
- * on some chipsets this will allow even 4k modes to be added which will
- * fail the per SSPP bandwidth checks. So, till we have dual-SSPP support
- * and source split support added lets limit the modes based on max_mixer_width
- * as 4K modes can then be supported.
- */
- return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width,
+ return drm_add_modes_noedid(connector, dpu_kms->catalog->wb->maxlinewidth,
dev->mode_config.max_height);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 3/3] drm/msm/dpu: Remove max_mixer_width from catalog
2026-01-03 13:45 [PATCH v2 0/3] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 1/3] drm/msm/dpu: Check mode against PINGPONG or DSC max width Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 2/3] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth Dmitry Baryshkov
@ 2026-01-03 13:45 ` Dmitry Baryshkov
2 siblings, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2026-01-03 13:45 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Jessica Zhang
From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Remove the now-unused max_mixer_width field from the HW catalog
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
31 files changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 56d3c38c8778..18866ca279df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -8,7 +8,6 @@
#define _DPU_10_0_SM8650_H
static const struct dpu_caps sm8650_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
index db8cc2d0112c..13cc84b28058 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
@@ -9,7 +9,6 @@
#define _DPU_12_0_SM8750_H
static const struct dpu_caps sm8750_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
index 13bb43ba67d3..59a4859ce67a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
@@ -7,7 +7,6 @@
#define _DPU_12_2_GLYMUR_H
static const struct dpu_caps glymur_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
index 29e0eba91930..c6923e0093cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
@@ -7,7 +7,6 @@
#define _DPU_1_14_MSM8937_H
static const struct dpu_caps msm8937_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
.pixel_ram_size = 40 * 1024,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
index cb1ee4b63f9f..14d0619c1479 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
@@ -7,7 +7,6 @@
#define _DPU_1_14_MSM8917_H
static const struct dpu_caps msm8917_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
.pixel_ram_size = 16 * 1024,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
index b44d02b48418..17f6d1ee90aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
@@ -7,7 +7,6 @@
#define _DPU_1_16_MSM8953_H
static const struct dpu_caps msm8953_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
.pixel_ram_size = 40 * 1024,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
index 8af63db315b4..1885ea92a808 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
@@ -9,7 +9,6 @@
#define _DPU_1_7_MSM8996_H
static const struct dpu_caps msm8996_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index f91220496082..3fafb10661cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -8,7 +8,6 @@
#define _DPU_3_0_MSM8998_H
static const struct dpu_caps msm8998_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
index 8f9a097147c0..b2bd87f4af43 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
@@ -7,7 +7,6 @@
#define _DPU_3_2_SDM660_H
static const struct dpu_caps sdm660_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
index 0ad18bd273ff..e4304ace8eb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
@@ -7,7 +7,6 @@
#define _DPU_3_3_SDM630_H
static const struct dpu_caps sdm630_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 5cc9f55d542b..ee3b78ce6bd1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -8,7 +8,6 @@
#define _DPU_4_0_SDM845_H
static const struct dpu_caps sdm845_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index ae1b2ed96e9f..02621def12b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -8,7 +8,6 @@
#define _DPU_5_0_SM8150_H
static const struct dpu_caps sm8150_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index b572cfa7ed35..04afc22d9fad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -8,7 +8,6 @@
#define _DPU_5_1_SC8180X_H
static const struct dpu_caps sc8180x_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index a56c288ac10c..371fcb7f7bef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -8,7 +8,6 @@
#define _DPU_5_2_SM7150_H
static const struct dpu_caps sm7150_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index 26883f6b66b3..a5a3944a5601 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -7,7 +7,6 @@
#define _DPU_5_3_SM6150_H
static const struct dpu_caps sm6150_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x9,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index fbf50f279e66..42d6d1a6cce4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -9,7 +9,6 @@
#define _DPU_5_4_SM6125_H
static const struct dpu_caps sm6125_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x6,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 7b8b7a1c2d76..d39ca9b287d4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -8,7 +8,6 @@
#define _DPU_6_0_SM8250_H
static const struct dpu_caps sm8250_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index c990ba3b5db0..afe83f5e4349 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -8,7 +8,6 @@
#define _DPU_6_2_SC7180_H
static const struct dpu_caps sc7180_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x9,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 343ff5482382..90d696707227 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -8,7 +8,6 @@
#define _DPU_6_3_SM6115_H
static const struct dpu_caps sm6115_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 093d16bdc450..d7a94b7c69f1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -9,7 +9,6 @@
#define _DPU_6_4_SM6350_H
static const struct dpu_caps sm6350_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 47053bf9b0a2..fadbfd4f9f95 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -8,7 +8,6 @@
#define _DPU_6_5_QCM2290_H
static const struct dpu_caps qcm2290_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 98190ee7ec7a..9427ec024d60 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -9,7 +9,6 @@
#define _DPU_6_9_SM6375_H
static const struct dpu_caps sm6375_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 85aae40c210f..5fe2673fa8d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -8,7 +8,6 @@
#define _DPU_7_0_SM8350_H
static const struct dpu_caps sm8350_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 8f978b9c3452..80233a687f35 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -8,7 +8,6 @@
#define _DPU_7_2_SC7280_H
static const struct dpu_caps sc7280_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
.has_dim_layer = true,
.has_idle_pc = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 303d33dc7783..37a539a195df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -8,7 +8,6 @@
#define _DPU_8_0_SC8280XP_H
static const struct dpu_caps sc8280xp_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 11,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index b09a6af4c474..bda58b5c48df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -8,7 +8,6 @@
#define _DPU_8_1_SM8450_H
static const struct dpu_caps sm8450_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 0f7b4a224e4c..c5affbb42ecb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -7,7 +7,6 @@
#define _DPU_8_4_SA8775P_H
static const struct dpu_caps sa8775p_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 465b6460f875..a34d85a82e99 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -8,7 +8,6 @@
#define _DPU_9_0_SM8550_H
static const struct dpu_caps sm8550_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 6caa7d40f368..21e40f098d6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -8,7 +8,6 @@
#define _DPU_9_1_SAR2130P_H
static const struct dpu_caps sar2130p_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 7243eebb85f3..6906fb060c19 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -7,7 +7,6 @@
#define _DPU_9_2_X1E80100_H
static const struct dpu_caps x1e80100_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.has_src_split = true,
.has_dim_layer = true,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index ee94d0ccb8a3..67a97d62ed54 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -259,7 +259,6 @@ struct dpu_rotation_cfg {
/**
* struct dpu_caps - define DPU capabilities
- * @max_mixer_width max layer mixer line width support.
* @max_mixer_blendstages max layer mixer blend stages or
* supported z order
* @has_src_split source split feature status
@@ -272,7 +271,6 @@ struct dpu_rotation_cfg {
* @max_vdeci_exp max vertical decimation supported (max is 2^value)
*/
struct dpu_caps {
- u32 max_mixer_width;
u32 max_mixer_blendstages;
bool has_src_split;
bool has_dim_layer;
--
2.47.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-01-03 13:45 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2026-01-03 13:45 [PATCH v2 0/3] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 1/3] drm/msm/dpu: Check mode against PINGPONG or DSC max width Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 2/3] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth Dmitry Baryshkov
2026-01-03 13:45 ` [PATCH v2 3/3] drm/msm/dpu: Remove max_mixer_width from catalog Dmitry Baryshkov
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