[PATCH 0/3] drm/msm: add RGB101010 pixel format and fix 10-bit DSC timing

[PATCH 0/3] drm/msm: add RGB101010 pixel format and fix 10-bit DSC timing

[Alexander Koskovich]

This series adds support for the RGB101010 (30bpp) pixel format and
fixes a DSC timing bug exposed by non 8 bit panels.

Tested on the BOE BF068MWM-TD0 panel (10 bit DSC) on the Nothing
Phone (3a).

Note, I'd appreciate a comment on the INTF timing change from someone
at QCOM who knows the DPU hardware a bit better, this appears to be
what downstream is doing regardless of bpp, but let me know if there's
a better solution here.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
Alexander Koskovich (3):
      drm/mipi-dsi: add RGB101010 pixel format
      drm/msm/dsi: Add support for RGB101010 pixel format
      drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels

 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++-----
 drivers/gpu/drm/msm/dsi/dsi_host.c                   |  2 ++
 drivers/gpu/drm/msm/registers/display/dsi.xml        |  4 +++-
 include/drm/drm_mipi_dsi.h                           |  4 ++++
 4 files changed, 16 insertions(+), 6 deletions(-)
---
base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
change-id: 20260318-dsi-rgb101010-support-4956b1cd8657

Best regards,
-- 
Alexander Koskovich <akoskovich@pm.me>

[PATCH 1/3] drm/mipi-dsi: add RGB101010 pixel format

[Alexander Koskovich]

Add MIPI_DSI_FMT_RGB101010 for 30 bit (10,10,10 RGB) pixel format,
corresponding to the packed 30 bit pixel stream defined in MIPI DSI
v1.3 Section 8.8.17.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 include/drm/drm_mipi_dsi.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 3aba7b380c8d..a822e9e876af 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -140,6 +140,7 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
 #define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
 
 enum mipi_dsi_pixel_format {
+	MIPI_DSI_FMT_RGB101010,
 	MIPI_DSI_FMT_RGB888,
 	MIPI_DSI_FMT_RGB666,
 	MIPI_DSI_FMT_RGB666_PACKED,
@@ -235,6 +236,9 @@ extern const struct bus_type mipi_dsi_bus_type;
 static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
 {
 	switch (fmt) {
+	case MIPI_DSI_FMT_RGB101010:
+		return 30;
+
 	case MIPI_DSI_FMT_RGB888:
 	case MIPI_DSI_FMT_RGB666:
 		return 24;

-- 
2.53.0

Re: [PATCH 1/3] drm/mipi-dsi: add RGB101010 pixel format

[Dmitry Baryshkov]

On Wed, Mar 18, 2026 at 09:41:00AM +0000, Alexander Koskovich wrote:
> Add MIPI_DSI_FMT_RGB101010 for 30 bit (10,10,10 RGB) pixel format,
> corresponding to the packed 30 bit pixel stream defined in MIPI DSI
> v1.3 Section 8.8.17.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  include/drm/drm_mipi_dsi.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 1/3] drm/mipi-dsi: add RGB101010 pixel format

[kernel test robot]

Hi Alexander,

kernel test robot noticed the following build warnings:

[auto build test WARNING on f338e77383789c0cae23ca3d48adcc5e9e137e3c]

url:    https://github.com/intel-lab-lkp/linux/commits/Alexander-Koskovich/drm-mipi-dsi-add-RGB101010-pixel-format/20260318-220726
base:   f338e77383789c0cae23ca3d48adcc5e9e137e3c
patch link:    https://lore.kernel.org/r/20260318-dsi-rgb101010-support-v1-1-6021eb79e796%40pm.me
patch subject: [PATCH 1/3] drm/mipi-dsi: add RGB101010 pixel format
config: nios2-allmodconfig (https://download.01.org/0day-ci/archive/20260319/202603190805.7UiuBASq-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260319/202603190805.7UiuBASq-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603190805.7UiuBASq-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/meson/meson_dw_mipi_dsi.c: In function 'dw_mipi_dsi_phy_init':
>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c:113:9: warning: enumeration value 'MIPI_DSI_FMT_RGB101010' not handled in switch [-Wswitch]
     113 |         switch (mipi_dsi->dsi_device->format) {
         |         ^~~~~~
   drivers/gpu/drm/meson/meson_dw_mipi_dsi.c: In function 'meson_dw_mipi_dsi_host_attach':
   drivers/gpu/drm/meson/meson_dw_mipi_dsi.c:230:9: warning: enumeration value 'MIPI_DSI_FMT_RGB101010' not handled in switch [-Wswitch]
     230 |         switch (device->format) {
         |         ^~~~~~


vim +/MIPI_DSI_FMT_RGB101010 +113 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c

77d9e1e6b8468f Neil Armstrong 2023-05-30   74  
77d9e1e6b8468f Neil Armstrong 2023-05-30   75  static int dw_mipi_dsi_phy_init(void *priv_data)
77d9e1e6b8468f Neil Armstrong 2023-05-30   76  {
77d9e1e6b8468f Neil Armstrong 2023-05-30   77  	struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
77d9e1e6b8468f Neil Armstrong 2023-05-30   78  	unsigned int dpi_data_format, venc_data_width;
77d9e1e6b8468f Neil Armstrong 2023-05-30   79  	int ret;
77d9e1e6b8468f Neil Armstrong 2023-05-30   80  
77d9e1e6b8468f Neil Armstrong 2023-05-30   81  	/* Set the bit clock rate to hs_clk_rate */
77d9e1e6b8468f Neil Armstrong 2023-05-30   82  	ret = clk_set_rate(mipi_dsi->bit_clk,
77d9e1e6b8468f Neil Armstrong 2023-05-30   83  			   mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
77d9e1e6b8468f Neil Armstrong 2023-05-30   84  	if (ret) {
77d9e1e6b8468f Neil Armstrong 2023-05-30   85  		dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n",
77d9e1e6b8468f Neil Armstrong 2023-05-30   86  			mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, ret);
77d9e1e6b8468f Neil Armstrong 2023-05-30   87  		return ret;
77d9e1e6b8468f Neil Armstrong 2023-05-30   88  	}
77d9e1e6b8468f Neil Armstrong 2023-05-30   89  
77d9e1e6b8468f Neil Armstrong 2023-05-30   90  	/* Make sure the rate of the bit clock is not modified by someone else */
77d9e1e6b8468f Neil Armstrong 2023-05-30   91  	ret = clk_rate_exclusive_get(mipi_dsi->bit_clk);
77d9e1e6b8468f Neil Armstrong 2023-05-30   92  	if (ret) {
77d9e1e6b8468f Neil Armstrong 2023-05-30   93  		dev_err(mipi_dsi->dev,
77d9e1e6b8468f Neil Armstrong 2023-05-30   94  			"Failed to set the exclusivity on the bit clock rate (ret %d)\n", ret);
77d9e1e6b8468f Neil Armstrong 2023-05-30   95  		return ret;
77d9e1e6b8468f Neil Armstrong 2023-05-30   96  	}
77d9e1e6b8468f Neil Armstrong 2023-05-30   97  
5c9837374ecf55 Neil Armstrong 2024-04-03   98  	clk_disable_unprepare(mipi_dsi->px_clk);
77d9e1e6b8468f Neil Armstrong 2023-05-30   99  	ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000);
77d9e1e6b8468f Neil Armstrong 2023-05-30  100  
77d9e1e6b8468f Neil Armstrong 2023-05-30  101  	if (ret) {
77d9e1e6b8468f Neil Armstrong 2023-05-30  102  		dev_err(mipi_dsi->dev, "Failed to set DSI Pixel clock rate %u (%d)\n",
77d9e1e6b8468f Neil Armstrong 2023-05-30  103  			mipi_dsi->mode->clock * 1000, ret);
77d9e1e6b8468f Neil Armstrong 2023-05-30  104  		return ret;
77d9e1e6b8468f Neil Armstrong 2023-05-30  105  	}
77d9e1e6b8468f Neil Armstrong 2023-05-30  106  
5c9837374ecf55 Neil Armstrong 2024-04-03  107  	ret = clk_prepare_enable(mipi_dsi->px_clk);
5c9837374ecf55 Neil Armstrong 2024-04-03  108  	if (ret) {
5c9837374ecf55 Neil Armstrong 2024-04-03  109  		dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret);
5c9837374ecf55 Neil Armstrong 2024-04-03  110  		return ret;
5c9837374ecf55 Neil Armstrong 2024-04-03  111  	}
5c9837374ecf55 Neil Armstrong 2024-04-03  112  
77d9e1e6b8468f Neil Armstrong 2023-05-30 @113  	switch (mipi_dsi->dsi_device->format) {
77d9e1e6b8468f Neil Armstrong 2023-05-30  114  	case MIPI_DSI_FMT_RGB888:
77d9e1e6b8468f Neil Armstrong 2023-05-30  115  		dpi_data_format = DPI_COLOR_24BIT;
77d9e1e6b8468f Neil Armstrong 2023-05-30  116  		venc_data_width = VENC_IN_COLOR_24B;
77d9e1e6b8468f Neil Armstrong 2023-05-30  117  		break;
77d9e1e6b8468f Neil Armstrong 2023-05-30  118  	case MIPI_DSI_FMT_RGB666:
77d9e1e6b8468f Neil Armstrong 2023-05-30  119  		dpi_data_format = DPI_COLOR_18BIT_CFG_2;
77d9e1e6b8468f Neil Armstrong 2023-05-30  120  		venc_data_width = VENC_IN_COLOR_18B;
77d9e1e6b8468f Neil Armstrong 2023-05-30  121  		break;
77d9e1e6b8468f Neil Armstrong 2023-05-30  122  	case MIPI_DSI_FMT_RGB666_PACKED:
77d9e1e6b8468f Neil Armstrong 2023-05-30  123  	case MIPI_DSI_FMT_RGB565:
77d9e1e6b8468f Neil Armstrong 2023-05-30  124  		return -EINVAL;
e96f099c8544a5 Yang Li        2023-06-02  125  	}
77d9e1e6b8468f Neil Armstrong 2023-05-30  126  
77d9e1e6b8468f Neil Armstrong 2023-05-30  127  	/* Configure color format for DPI register */
77d9e1e6b8468f Neil Armstrong 2023-05-30  128  	writel_relaxed(FIELD_PREP(MIPI_DSI_TOP_DPI_COLOR_MODE, dpi_data_format) |
77d9e1e6b8468f Neil Armstrong 2023-05-30  129  		       FIELD_PREP(MIPI_DSI_TOP_IN_COLOR_MODE, venc_data_width) |
77d9e1e6b8468f Neil Armstrong 2023-05-30  130  		       FIELD_PREP(MIPI_DSI_TOP_COMP2_SEL, 2) |
77d9e1e6b8468f Neil Armstrong 2023-05-30  131  		       FIELD_PREP(MIPI_DSI_TOP_COMP1_SEL, 1) |
77d9e1e6b8468f Neil Armstrong 2023-05-30  132  		       FIELD_PREP(MIPI_DSI_TOP_COMP0_SEL, 0),
77d9e1e6b8468f Neil Armstrong 2023-05-30  133  			mipi_dsi->base + MIPI_DSI_TOP_CNTL);
77d9e1e6b8468f Neil Armstrong 2023-05-30  134  
77d9e1e6b8468f Neil Armstrong 2023-05-30  135  	return phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
77d9e1e6b8468f Neil Armstrong 2023-05-30  136  }
77d9e1e6b8468f Neil Armstrong 2023-05-30  137  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 2/3] drm/msm/dsi: Add support for RGB101010 pixel format

[Alexander Koskovich]

Add video and command mode destination format mappings for
RGB101010, and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits
to accommodate the new format value.

Required for 10 bit panels such as the BOE BF068MWM-TD0.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c            | 2 ++
 drivers/gpu/drm/msm/registers/display/dsi.xml | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index db6da99375a1..3e3d61b9390f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -757,6 +757,7 @@ static inline enum dsi_vid_dst_format
 dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt)
 {
 	switch (mipi_fmt) {
+	case MIPI_DSI_FMT_RGB101010:	return VID_DST_FORMAT_RGB101010;
 	case MIPI_DSI_FMT_RGB888:	return VID_DST_FORMAT_RGB888;
 	case MIPI_DSI_FMT_RGB666:	return VID_DST_FORMAT_RGB666_LOOSE;
 	case MIPI_DSI_FMT_RGB666_PACKED:	return VID_DST_FORMAT_RGB666;
@@ -769,6 +770,7 @@ static inline enum dsi_cmd_dst_format
 dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt)
 {
 	switch (mipi_fmt) {
+	case MIPI_DSI_FMT_RGB101010:	return CMD_DST_FORMAT_RGB101010;
 	case MIPI_DSI_FMT_RGB888:	return CMD_DST_FORMAT_RGB888;
 	case MIPI_DSI_FMT_RGB666_PACKED:
 	case MIPI_DSI_FMT_RGB666:	return CMD_DST_FORMAT_RGB666;
diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/drm/msm/registers/display/dsi.xml
index c7a7b633d747..7636e9914078 100644
--- a/drivers/gpu/drm/msm/registers/display/dsi.xml
+++ b/drivers/gpu/drm/msm/registers/display/dsi.xml
@@ -15,6 +15,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 		<value name="VID_DST_FORMAT_RGB666" value="1"/>
 		<value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
 		<value name="VID_DST_FORMAT_RGB888" value="3"/>
+		<value name="VID_DST_FORMAT_RGB101010" value="4"/>
 	</enum>
 	<enum name="dsi_rgb_swap">
 		<value name="SWAP_RGB" value="0"/>
@@ -39,6 +40,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 		<value name="CMD_DST_FORMAT_RGB565" value="6"/>
 		<value name="CMD_DST_FORMAT_RGB666" value="7"/>
 		<value name="CMD_DST_FORMAT_RGB888" value="8"/>
+		<value name="CMD_DST_FORMAT_RGB101010" value="9"/>
 	</enum>
 	<enum name="dsi_lane_swap">
 		<value name="LANE_SWAP_0123" value="0"/>
@@ -142,7 +144,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 	</reg32>
 	<reg32 offset="0x0000c" name="VID_CFG0">
 		<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/>  <!-- always zero? -->
-		<bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
+		<bitfield name="DST_FORMAT" low="4" high="6" type="dsi_vid_dst_format"/>
 		<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
 		<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
 		<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>

-- 
2.53.0

Re: [PATCH 2/3] drm/msm/dsi: Add support for RGB101010 pixel format

[Dmitry Baryshkov]

On Wed, Mar 18, 2026 at 09:41:05AM +0000, Alexander Koskovich wrote:
> Add video and command mode destination format mappings for
> RGB101010, and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits
> to accommodate the new format value.

It's only available since DSI 6G 2.1.0. Could you please add the
corresponding check (I think having something like .has_rgb30 as a part
of struct msm_dsi_config is a good enough approach).

> 
> Required for 10 bit panels such as the BOE BF068MWM-TD0.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c            | 2 ++
>  drivers/gpu/drm/msm/registers/display/dsi.xml | 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index db6da99375a1..3e3d61b9390f 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -757,6 +757,7 @@ static inline enum dsi_vid_dst_format
>  dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt)
>  {
>  	switch (mipi_fmt) {
> +	case MIPI_DSI_FMT_RGB101010:	return VID_DST_FORMAT_RGB101010;
>  	case MIPI_DSI_FMT_RGB888:	return VID_DST_FORMAT_RGB888;
>  	case MIPI_DSI_FMT_RGB666:	return VID_DST_FORMAT_RGB666_LOOSE;
>  	case MIPI_DSI_FMT_RGB666_PACKED:	return VID_DST_FORMAT_RGB666;
> @@ -769,6 +770,7 @@ static inline enum dsi_cmd_dst_format
>  dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt)
>  {
>  	switch (mipi_fmt) {
> +	case MIPI_DSI_FMT_RGB101010:	return CMD_DST_FORMAT_RGB101010;
>  	case MIPI_DSI_FMT_RGB888:	return CMD_DST_FORMAT_RGB888;
>  	case MIPI_DSI_FMT_RGB666_PACKED:
>  	case MIPI_DSI_FMT_RGB666:	return CMD_DST_FORMAT_RGB666;
> diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/drm/msm/registers/display/dsi.xml
> index c7a7b633d747..7636e9914078 100644
> --- a/drivers/gpu/drm/msm/registers/display/dsi.xml
> +++ b/drivers/gpu/drm/msm/registers/display/dsi.xml
> @@ -15,6 +15,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
>  		<value name="VID_DST_FORMAT_RGB666" value="1"/>
>  		<value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
>  		<value name="VID_DST_FORMAT_RGB888" value="3"/>
> +		<value name="VID_DST_FORMAT_RGB101010" value="4"/>
>  	</enum>
>  	<enum name="dsi_rgb_swap">
>  		<value name="SWAP_RGB" value="0"/>
> @@ -39,6 +40,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
>  		<value name="CMD_DST_FORMAT_RGB565" value="6"/>
>  		<value name="CMD_DST_FORMAT_RGB666" value="7"/>
>  		<value name="CMD_DST_FORMAT_RGB888" value="8"/>
> +		<value name="CMD_DST_FORMAT_RGB101010" value="9"/>
>  	</enum>
>  	<enum name="dsi_lane_swap">
>  		<value name="LANE_SWAP_0123" value="0"/>
> @@ -142,7 +144,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
>  	</reg32>
>  	<reg32 offset="0x0000c" name="VID_CFG0">
>  		<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/>  <!-- always zero? -->
> -		<bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
> +		<bitfield name="DST_FORMAT" low="4" high="6" type="dsi_vid_dst_format"/>

Please comment that it had high=5 before DSI 6G 2.1.0

>  		<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
>  		<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
>  		<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
> 
> -- 
> 2.53.0
> 
> 

-- 
With best wishes
Dmitry

[PATCH 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels

[Alexander Koskovich]

Using bits_per_component * 3 as the divisor for the compressed INTF
timing width produces constant FIFO errors for panels such as the BOE
BF068MWM-TD0 which is a 10 bit panel.

The downstream driver calculates the compressed timing width by
dividing the total compressed bytes per line by 3 which does not depend
on bits_per_component. Switch the divisor to 24 to match downstream.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0ba777bda253..9b046a0e77aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params(
 	}
 
 	/*
-	 * for DSI, if compression is enabled, then divide the horizonal active
-	 * timing parameters by compression ratio. bits of 3 components(R/G/B)
-	 * is compressed into bits of 1 pixel.
+	 * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than
+	 * bits_per_component * 3 when calculating the compressed timing width.
+	 *
+	 * This matches the downstream driver and is required for panels with
+	 * bits_per_component != 8.
 	 */
 	if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
 		struct drm_dsc_config *dsc =
 		       dpu_encoder_get_dsc_config(phys_enc->parent);
+
 		/*
 		 * TODO: replace drm_dsc_get_bpp_int with logic to handle
 		 * fractional part if there is fraction
 		 */
-		timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
-				(dsc->bits_per_component * 3);
+		timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24;
 		timing->xres = timing->width;
 	}
 }

-- 
2.53.0

Re: [PATCH 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels

[Dmitry Baryshkov]

On Wed, Mar 18, 2026 at 09:41:09AM +0000, Alexander Koskovich wrote:
> Using bits_per_component * 3 as the divisor for the compressed INTF
> timing width produces constant FIFO errors for panels such as the BOE
> BF068MWM-TD0 which is a 10 bit panel.
> 
> The downstream driver calculates the compressed timing width by
> dividing the total compressed bytes per line by 3 which does not depend
> on bits_per_component. Switch the divisor to 24 to match downstream.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 0ba777bda253..9b046a0e77aa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params(
>  	}
>  
>  	/*
> -	 * for DSI, if compression is enabled, then divide the horizonal active
> -	 * timing parameters by compression ratio. bits of 3 components(R/G/B)
> -	 * is compressed into bits of 1 pixel.
> +	 * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than
> +	 * bits_per_component * 3 when calculating the compressed timing width.
> +	 *
> +	 * This matches the downstream driver and is required for panels with
> +	 * bits_per_component != 8.
>  	 */
>  	if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
>  		struct drm_dsc_config *dsc =
>  		       dpu_encoder_get_dsc_config(phys_enc->parent);
> +
>  		/*
>  		 * TODO: replace drm_dsc_get_bpp_int with logic to handle
>  		 * fractional part if there is fraction
>  		 */
> -		timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
> -				(dsc->bits_per_component * 3);
> +		timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24;
>  		timing->xres = timing->width;
>  	}
>  }

It's already a third patch touching this part of code. I hope Marijn can
comment here.

-- 
With best wishes
Dmitry