Linux ARM-MSM sub-architecture
 help / color / mirror / Atom feed
From: Mayank Rana <mayank.rana@oss.qualcomm.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: linux-pci@vger.kernel.org, lpieralisi@kernel.org, kw@linux.com,
	robh@kernel.org, bhelgaas@google.com, andersson@kernel.org,
	manivannan.sadhasivam@linaro.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	quic_ramkri@quicinc.com, quic_shazhuss@quicinc.com,
	quic_msarkar@quicinc.com, quic_nitegupt@quicinc.com
Subject: Re: [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex
Date: Mon, 16 Jun 2025 11:08:04 -0700	[thread overview]
Message-ID: <20a4c01e-d2be-4846-abc6-b2d477975249@oss.qualcomm.com> (raw)
In-Reply-To: <4yscxqds72lsrdld7tadnlcuk7q6hir3t6mwliu35aljn34veb@hme5q4dpind7>

Hi Mani

On 6/13/2025 2:29 AM, Manivannan Sadhasivam wrote:
> On Thu, Jun 12, 2025 at 02:24:04PM -0700, Mayank Rana wrote:
>> Hi Mani
>>
>> Gentle reminder for review.
>>
> 
> These patches are not applying on top of v6.16-rc1. Please post the rebased
> version.
ok. will rebase changes and resend it.

Thanks.

Regards,
Mayank

> - Mani
> 
>> Regards
>> Mayank
>>
>> On 6/4/2025 10:38 AM, Mayank Rana wrote:
>>> Hi Mani
>>>
>>> As we discussed previously, I resumed working on this functionality.
>>> Please help with reviewing this patchset.
>>>
>>> Regards,
>>> Mayank
>>> On 5/21/2025 5:14 PM, Mayank Rana wrote:
>>>> Based on received feedback, this patch series adds support with existing
>>>> Linux qcom-pcie.c driver to get PCIe host root complex functionality on
>>>> Qualcomm SA8255P auto platform.
>>>>
>>>> 1. Interface to allow requesting firmware to manage system resources and
>>>> performing PCIe Link up (devicetree binding in terms of power domain and
>>>> runtime PM APIs is used in driver)
>>>>
>>>> 2. SA8255P is using Synopsys Designware PCIe controller which
>>>> supports MSI
>>>> controller. Using existing MSI controller based functionality by
>>>> exporting
>>>> important pcie dwc core driver based MSI APIs, and using those from
>>>> pcie-qcom.c driver.
>>>>
>>>> Below architecture is used on Qualcomm SA8255P auto platform to get ECAM
>>>> compliant PCIe controller based functionality. Here firmware VM
>>>> based PCIe
>>>> driver takes care of resource management and performing PCIe link related
>>>> handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to
>>>> request firmware VM to perform these operations using SCMI interface.
>>>> --------------------
>>>>
>>>>
>>>>                                      ┌────────────────────────┐
>>>>                                      │                        │
>>>>     ┌──────────────────────┐         │     SHARED MEMORY
>>>> │            ┌──────────────────────────┐
>>>>     │     Firmware VM      │         │
>>>> │            │         Linux VM         │
>>>>     │ ┌─────────┐          │         │
>>>> │            │    ┌────────────────┐    │
>>>>     │ │ Drivers │ ┌──────┐ │         │
>>>> │            │    │   PCIE Qcom    │    │
>>>>     │ │ PCIE PHY◄─┤      │ │         │   ┌────────────────┐
>>>> │            │    │    driver      │    │
>>>>     │ │         │ │ SCMI │ │         │   │                │
>>>> │            │    │                │    │
>>>>     │ │PCIE CTL │ │      │ ├─────────┼───►    PCIE
>>>> ◄───┼─────┐      │    └──┬──────────▲──┘    │
>>>>     │ │         ├─►Server│ │         │   │    SHMEM       │   │
>>>> │      │       │          │       │
>>>>     │ │Clk, Vreg│ │      │ │         │   │                │   │
>>>> │      │    ┌──▼──────────┴──┐    │
>>>>     │ │GPIO,GDSC│ └─▲──┬─┘ │         │   └────────────────┘   │
>>>> └──────┼────┤PCIE SCMI Inst  │    │
>>>>     │ └─────────┘   │  │   │         │
>>>> │            │    └──▲──────────┬──┘    │
>>>>     │               │  │   │         │
>>>> │            │       │          │       │
>>>>     └───────────────┼──┼───┘         │
>>>> │            └───────┼──────────┼───────┘
>>>>                     │  │             │
>>>> │                    │          │
>>>>                     │  │
>>>> └────────────────────────┘                    │          │
>>>>                     │
>>>> │
>>>> │          │
>>>>                     │
>>>> │
>>>> │          │
>>>>                     │
>>>> │
>>>> │          │
>>>>                     │
>>>> │                                                           │IRQ
>>>> │HVC
>>>>                 IRQ │
>>>> │HVC
>>>> │          │
>>>>                     │
>>>> │
>>>> │          │
>>>>                     │
>>>> │
>>>> │          │
>>>>                     │
>>>> │
>>>> │          │
>>>> ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐
>>>> │                                                                                                          │
>>>> │                                                                                                          │
>>>> │
>>>> HYPERVISOR
>>>> │
>>>> │                                                                                                          │
>>>> │                                                                                                          │
>>>> │                                                                                                          │
>>>> └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
>>>>     ┌─────────────┐    ┌─────────────┐  ┌──────────┐   ┌───────────┐
>>>> ┌─────────────┐  ┌────────────┐
>>>>     │             │    │             │  │          │   │           │
>>>> │  PCIE       │  │   PCIE     │
>>>>     │   CLOCK     │    │   REGULATOR │  │   GPIO   │   │   GDSC    │
>>>> │  PHY        │  │ controller │
>>>>     └─────────────┘    └─────────────┘  └──────────┘   └───────────┘
>>>> └─────────────┘  └────────────┘
>>>> -----------------
>>>> Changes in v4:
>>>> - Addressed provided review comments from reviewers
>>>> Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-
>>>> quic_mrana@quicinc.com/
>>>>
>>>> Changes in v3:
>>>> - Drop usage of PCIE host generic driver usage, and splitting of MSI
>>>> functionality
>>>> - Modified existing pcie-qcom.c driver to add support for getting
>>>> ECAM compliant and firmware managed
>>>> PCIe root complex functionality
>>>> Link to v2: https://lore.kernel.org/linux-arm-
>>>> kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/
>>>>
>>>> Changes in v2:
>>>> - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware
>>>> based MSI functionality
>>>> - Add power domain based functionality within existing ECAM driver
>>>> Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-
>>>> a0a4d067341f@quicinc.com/T/
>>>>
>>>> Tested:
>>>> - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform
>>>>
>>>> Mayank Rana (4):
>>>>     PCI: dwc: Export dwc MSI controller related APIs
>>>>     PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM
>>>>       creation
>>>>     dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root
>>>>       complex
>>>>     PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality
>>>>
>>>>    .../bindings/pci/qcom,pcie-sa8255p.yaml       | 103 ++++++++++++++++
>>>>    drivers/pci/controller/dwc/Kconfig            |   1 +
>>>>    .../pci/controller/dwc/pcie-designware-host.c |  38 +++---
>>>>    drivers/pci/controller/dwc/pcie-designware.h  |  14 +++
>>>>    drivers/pci/controller/dwc/pcie-qcom.c        | 114 ++++++++++++++++--
>>>>    drivers/pci/controller/pci-host-common.c      |   5 +-
>>>>    include/linux/pci-ecam.h                      |   2 +
>>>>    7 files changed, 248 insertions(+), 29 deletions(-)
>>>>    create mode 100644
>>>> Documentation/devicetree/bindings/pci/qcom,pcie- sa8255p.yaml
>>>>
>>>
>>
> 


      reply	other threads:[~2025-06-16 18:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-22  0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
2025-05-22  0:14 ` [PATCH v4 1/4] PCI: dwc: Export dwc MSI controller related APIs Mayank Rana
2025-05-22  0:14 ` [PATCH v4 2/4] PCI: host-generic: Rename and export gen_pci_init() to allow ECAM creation Mayank Rana
2025-05-22  0:14 ` [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex Mayank Rana
2025-06-04 17:42   ` Mayank Rana
2025-06-05 17:28   ` Rob Herring (Arm)
2025-05-22  0:14 ` [PATCH v4 4/4] PCI: qcom: Add support for Qualcomm SA8255p based " Mayank Rana
2025-06-04 17:38 ` [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed " Mayank Rana
2025-06-12 21:24   ` Mayank Rana
2025-06-13  9:29     ` Manivannan Sadhasivam
2025-06-16 18:08       ` Mayank Rana [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20a4c01e-d2be-4846-abc6-b2d477975249@oss.qualcomm.com \
    --to=mayank.rana@oss.qualcomm.com \
    --cc=andersson@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=kw@linux.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=mani@kernel.org \
    --cc=manivannan.sadhasivam@linaro.org \
    --cc=quic_msarkar@quicinc.com \
    --cc=quic_nitegupt@quicinc.com \
    --cc=quic_ramkri@quicinc.com \
    --cc=quic_shazhuss@quicinc.com \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox