* [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 2:05 [PATCH v3 0/5] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
@ 2026-03-23 2:05 ` Aaron Kling via B4 Relay
2026-03-23 7:51 ` Krzysztof Kozlowski
2026-03-23 2:05 ` [PATCH v3 2/5] arm64: dts: qcom: Add AYN QCS8550 Common Aaron Kling via B4 Relay
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-03-23 2:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling
From: Aaron Kling <webgeek1234@gmail.com>
Namely:
* Odin 2
* Odin 2 Mini
* Odin 2 Portal
* Thor
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index d054a8f5632d853509b7cd37f07f02473cf6bf71..ee68963c30eae10fd3b3a5e21bda63ab941893fa 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1075,6 +1075,15 @@ properties:
- const: qcom,qcs8550
- const: qcom,sm8550
+ - items:
+ - enum:
+ - ayntec,odin2
+ - ayntec,odin2mini
+ - ayntec,odin2portal
+ - ayntec,thor
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- qcom,sm8650-hdk
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 2:05 ` [PATCH v3 1/5] dt-bindings: arm: qcom: Add " Aaron Kling via B4 Relay
@ 2026-03-23 7:51 ` Krzysztof Kozlowski
2026-03-23 8:39 ` Aaron Kling
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-23 7:51 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Sun, Mar 22, 2026 at 09:05:18PM -0500, Aaron Kling wrote:
> Namely:
> * Odin 2
> * Odin 2 Mini
> * Odin 2 Portal
> * Thor
>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index d054a8f5632d853509b7cd37f07f02473cf6bf71..ee68963c30eae10fd3b3a5e21bda63ab941893fa 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -1075,6 +1075,15 @@ properties:
> - const: qcom,qcs8550
> - const: qcom,sm8550
>
> + - items:
> + - enum:
> + - ayntec,odin2
> + - ayntec,odin2mini
> + - ayntec,odin2portal
> + - ayntec,thor
I already commented on vendor prefix patch, that you incorrectly moved
it out from this set. This only stalls your patchsets, because none of
the trees will have it thus none will pass any checks.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 7:51 ` Krzysztof Kozlowski
@ 2026-03-23 8:39 ` Aaron Kling
2026-03-23 9:00 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Aaron Kling @ 2026-03-23 8:39 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Mon, Mar 23, 2026 at 2:51 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Sun, Mar 22, 2026 at 09:05:18PM -0500, Aaron Kling wrote:
> > Namely:
> > * Odin 2
> > * Odin 2 Mini
> > * Odin 2 Portal
> > * Thor
> >
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> > Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> > index d054a8f5632d853509b7cd37f07f02473cf6bf71..ee68963c30eae10fd3b3a5e21bda63ab941893fa 100644
> > --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> > +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> > @@ -1075,6 +1075,15 @@ properties:
> > - const: qcom,qcs8550
> > - const: qcom,sm8550
> >
> > + - items:
> > + - enum:
> > + - ayntec,odin2
> > + - ayntec,odin2mini
> > + - ayntec,odin2portal
> > + - ayntec,thor
>
> I already commented on vendor prefix patch, that you incorrectly moved
> it out from this set. This only stalls your patchsets, because none of
> the trees will have it thus none will pass any checks.
You mean the checks that passed just fine on v2? This is documented in
the cover letter, which apparently no one ever reads so I wonder why
we even write them; and listed as a dep, which said checks pick up
just fine.
As I have mentioned multiple times, the vendor patch is separate
because I have multiple open series that depend on the vendor and
there's no telling which one will be picked up first.
Aaron
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 8:39 ` Aaron Kling
@ 2026-03-23 9:00 ` Krzysztof Kozlowski
2026-03-23 9:04 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-23 9:00 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 23/03/2026 09:39, Aaron Kling wrote:
> On Mon, Mar 23, 2026 at 2:51 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On Sun, Mar 22, 2026 at 09:05:18PM -0500, Aaron Kling wrote:
>>> Namely:
>>> * Odin 2
>>> * Odin 2 Mini
>>> * Odin 2 Portal
>>> * Thor
>>>
>>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>>> 1 file changed, 9 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> index d054a8f5632d853509b7cd37f07f02473cf6bf71..ee68963c30eae10fd3b3a5e21bda63ab941893fa 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> @@ -1075,6 +1075,15 @@ properties:
>>> - const: qcom,qcs8550
>>> - const: qcom,sm8550
>>>
>>> + - items:
>>> + - enum:
>>> + - ayntec,odin2
>>> + - ayntec,odin2mini
>>> + - ayntec,odin2portal
>>> + - ayntec,thor
>>
>> I already commented on vendor prefix patch, that you incorrectly moved
>> it out from this set. This only stalls your patchsets, because none of
>> the trees will have it thus none will pass any checks.
>
> You mean the checks that passed just fine on v2? This is documented in
> the cover letter, which apparently no one ever reads so I wonder why
> we even write them; and listed as a dep, which said checks pick up
> just fine.
Checks will not be fine, imagine this scenario: Bjorn will pick up this
patchset and next will have failures, because there is no vendor prefix
documented in the next.
>
> As I have mentioned multiple times, the vendor patch is separate
And as I answered to you already twice...
> because I have multiple open series that depend on the vendor and
> there's no telling which one will be picked up first.
...no one will pick up vendor prefix thus your goal will not be
achieved. Nothing in vendor prefix patch explains how should take it to
solve it. People do not take random patches, so if you wanted Rob to
take it, you should have been explicit.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 9:00 ` Krzysztof Kozlowski
@ 2026-03-23 9:04 ` Krzysztof Kozlowski
2026-03-23 16:03 ` Aaron Kling
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-23 9:04 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 23/03/2026 10:00, Krzysztof Kozlowski wrote:
> On 23/03/2026 09:39, Aaron Kling wrote:
>> On Mon, Mar 23, 2026 at 2:51 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>
>>> On Sun, Mar 22, 2026 at 09:05:18PM -0500, Aaron Kling wrote:
>>>> Namely:
>>>> * Odin 2
>>>> * Odin 2 Mini
>>>> * Odin 2 Portal
>>>> * Thor
>>>>
>>>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
>>>> ---
>>>> Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>>>> 1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> index d054a8f5632d853509b7cd37f07f02473cf6bf71..ee68963c30eae10fd3b3a5e21bda63ab941893fa 100644
>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> @@ -1075,6 +1075,15 @@ properties:
>>>> - const: qcom,qcs8550
>>>> - const: qcom,sm8550
>>>>
>>>> + - items:
>>>> + - enum:
>>>> + - ayntec,odin2
>>>> + - ayntec,odin2mini
>>>> + - ayntec,odin2portal
>>>> + - ayntec,thor
>>>
>>> I already commented on vendor prefix patch, that you incorrectly moved
>>> it out from this set. This only stalls your patchsets, because none of
>>> the trees will have it thus none will pass any checks.
>>
>> You mean the checks that passed just fine on v2? This is documented in
>> the cover letter, which apparently no one ever reads so I wonder why
>> we even write them; and listed as a dep, which said checks pick up
>> just fine.
>
> Checks will not be fine, imagine this scenario: Bjorn will pick up this
> patchset and next will have failures, because there is no vendor prefix
> documented in the next.
There are also more subtle problems here.
Because you included it as b4 deps, multiple maintainers might pull the
same patchset if they are not careful and do not notice the pull of
dependency. If that happens, you achieved nothing by decoupling it and
it is the same as it was included in every patchset.
I, for example, do not take patches with dependencies, so that would be
a blocker, so again you achieved nothing. I don't know about Bjorn, though.
OTOH, since you have a b4 dep here and bot checks supposedly pass,
maintainer might just pull this patchset (without dependency in cherry
pick mode of b4) and not notice the failures.
>
>>
>> As I have mentioned multiple times, the vendor patch is separate
>
> And as I answered to you already twice...
>
>> because I have multiple open series that depend on the vendor and
>> there's no telling which one will be picked up first.
>
> ...no one will pick up vendor prefix thus your goal will not be
> achieved. Nothing in vendor prefix patch explains how should take it to
> solve it. People do not take random patches, so if you wanted Rob to
> take it, you should have been explicit.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 9:04 ` Krzysztof Kozlowski
@ 2026-03-23 16:03 ` Aaron Kling
2026-03-23 16:12 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Aaron Kling @ 2026-03-23 16:03 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Mon, Mar 23, 2026 at 4:04 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 23/03/2026 10:00, Krzysztof Kozlowski wrote:
> > On 23/03/2026 09:39, Aaron Kling wrote:
> >> On Mon, Mar 23, 2026 at 2:51 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>
> >>> On Sun, Mar 22, 2026 at 09:05:18PM -0500, Aaron Kling wrote:
> >>>> Namely:
> >>>> * Odin 2
> >>>> * Odin 2 Mini
> >>>> * Odin 2 Portal
> >>>> * Thor
> >>>>
> >>>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> >>>> ---
> >>>> Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
> >>>> 1 file changed, 9 insertions(+)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> >>>> index d054a8f5632d853509b7cd37f07f02473cf6bf71..ee68963c30eae10fd3b3a5e21bda63ab941893fa 100644
> >>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> >>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> >>>> @@ -1075,6 +1075,15 @@ properties:
> >>>> - const: qcom,qcs8550
> >>>> - const: qcom,sm8550
> >>>>
> >>>> + - items:
> >>>> + - enum:
> >>>> + - ayntec,odin2
> >>>> + - ayntec,odin2mini
> >>>> + - ayntec,odin2portal
> >>>> + - ayntec,thor
> >>>
> >>> I already commented on vendor prefix patch, that you incorrectly moved
> >>> it out from this set. This only stalls your patchsets, because none of
> >>> the trees will have it thus none will pass any checks.
> >>
> >> You mean the checks that passed just fine on v2? This is documented in
> >> the cover letter, which apparently no one ever reads so I wonder why
> >> we even write them; and listed as a dep, which said checks pick up
> >> just fine.
> >
> > Checks will not be fine, imagine this scenario: Bjorn will pick up this
> > patchset and next will have failures, because there is no vendor prefix
> > documented in the next.
>
> There are also more subtle problems here.
>
> Because you included it as b4 deps, multiple maintainers might pull the
> same patchset if they are not careful and do not notice the pull of
> dependency. If that happens, you achieved nothing by decoupling it and
> it is the same as it was included in every patchset.
>
> I, for example, do not take patches with dependencies, so that would be
> a blocker, so again you achieved nothing. I don't know about Bjorn, though.
>
> OTOH, since you have a b4 dep here and bot checks supposedly pass,
> maintainer might just pull this patchset (without dependency in cherry
> pick mode of b4) and not notice the failures.
>
> >
> >>
> >> As I have mentioned multiple times, the vendor patch is separate
> >
> > And as I answered to you already twice...
> >
> >> because I have multiple open series that depend on the vendor and
> >> there's no telling which one will be picked up first.
> >
> > ...no one will pick up vendor prefix thus your goal will not be
> > achieved. Nothing in vendor prefix patch explains how should take it to
> > solve it. People do not take random patches, so if you wanted Rob to
> > take it, you should have been explicit.
You told me on multiple tegra series to split things and list merge
dependencies in the cover letter. I have listed in this cover letter
that the vendor patch must be merged before anything from this series
is picked up. Why is this any different from what you kept telling me
before? Whichever binding patch gets cleared for merge first will
trigger the dependency of merging the vendor patch. And as long as a
message is generated on that patch that it has been picked up, other
series with that dependency would not cause a duplicate.
What would the alternative be? Say the vendor patch gets added to this
series. Then I would have a driver series that would have to list this
as a b4 dep for checks to continue to pass. Making a dt series that is
otherwise unrelated a requirement for that driver to be merged. That
seems even worse. Or much worse, I would be unable to submit such
drivers at all until this has been picked up.
Aaron
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-03-23 16:03 ` Aaron Kling
@ 2026-03-23 16:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-23 16:12 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 23/03/2026 17:03, Aaron Kling wrote:
>>>>
>>>> As I have mentioned multiple times, the vendor patch is separate
>>>
>>> And as I answered to you already twice...
>>>
>>>> because I have multiple open series that depend on the vendor and
>>>> there's no telling which one will be picked up first.
>>>
>>> ...no one will pick up vendor prefix thus your goal will not be
>>> achieved. Nothing in vendor prefix patch explains how should take it to
>>> solve it. People do not take random patches, so if you wanted Rob to
>>> take it, you should have been explicit.
>
> You told me on multiple tegra series to split things and list merge
> dependencies in the cover letter. I have listed in this cover letter
> that the vendor patch must be merged before anything from this series
> is picked up. Why is this any different from what you kept telling me
> before? Whichever binding patch gets cleared for merge first will
Because these patches in tegra will be picked up. Vendor prefix won't.
Let's reverse the problem - who should pick up such vendor prefix patch
without user and explanation, and why anyone should do it?
> trigger the dependency of merging the vendor patch. And as long as a
> message is generated on that patch that it has been picked up, other
> series with that dependency would not cause a duplicate.
>
> What would the alternative be? Say the vendor patch gets added to this
> series. Then I would have a driver series that would have to list this
Could be. I gave you other alternative - "you should have been explicit".
> as a b4 dep for checks to continue to pass. Making a dt series that is
> otherwise unrelated a requirement for that driver to be merged. That
> seems even worse. Or much worse, I would be unable to submit such
> drivers at all until this has been picked up.
>
> Aaron
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/5] arm64: dts: qcom: Add AYN QCS8550 Common
2026-03-23 2:05 [PATCH v3 0/5] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 1/5] dt-bindings: arm: qcom: Add " Aaron Kling via B4 Relay
@ 2026-03-23 2:05 ` Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 3/5] arm64: dts: qcom: Add AYN Odin 2 Mini Aaron Kling via B4 Relay
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-03-23 2:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin
From: Teguh Sobirin <teguh@sobir.in>
This contains everything common between the AYN QCS8550 devices. It will
be included by device specific dts'.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
.../arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi | 1762 ++++++++++++++++++++
1 file changed, 1762 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..f46672cca66b8a37bb8c514643273a2d915049ed
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi
@@ -0,0 +1,1762 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/delete-node/ &aop_image_mem;
+/delete-node/ &aop_config_mem;
+/delete-node/ &camera_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &q6_mpss_dtb_mem;
+/delete-node/ &remoteproc_mpss;
+
+/ {
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ serial1 = &uart14;
+ };
+
+ // The tzlog label is required by ABL to apply a dtbo, but it can be on any node
+ qcom_tzlog: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&usb0_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ pwm_fan: pwm-fan {
+ compatible = "pwm-fan";
+
+ fan-supply = <&vdd_fan_5v0>;
+ pwms = <&pm8550_pwm 3 50000>;
+
+ pinctrl-0 = <&fan_pwm_active>, <&fan_int>;
+ pinctrl-names = "default";
+
+ pulses-per-revolution = <4>;
+ interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
+
+ cooling-levels = <0 40 65 75 90 100 120 150 175>;
+ #cooling-cells = <2>;
+ };
+
+ reserved-memory {
+ hyp_mem: hyp-region@80000000 {
+ reg = <0 0x80000000 0 0xa00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm-region@80a00000 {
+ reg = <0 0x80a00000 0 0x400000>;
+ no-map;
+ };
+
+ hyp_tags_mem: hyp-tags-region@80e00000 {
+ reg = <0 0x80e00000 0 0x3d0000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc-region@d8100000 {
+ reg = <0 0xd8100000 0 0x40000>;
+ no-map;
+ };
+
+ hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
+ reg = <0 0x811d0000 0 0x30000>;
+ no-map;
+ };
+
+ xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
+ reg = <0 0x81a00000 0 0x260000>;
+ no-map;
+ };
+
+ aop_config_merged_mem: aop-config-merged-region@81c80000 {
+ reg = <0 0x81c80000 0 0x74000>;
+ no-map;
+ };
+
+ chipinfo_mem: chipinfo-region@81cf4000 {
+ reg = <0 0x81cf4000 0 0x1000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync-region@82600000 {
+ reg = <0 0x82600000 0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@82700000 {
+ reg = <0 0x82700000 0 0x100000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@d8140000 {
+ reg = <0 0xd8140000 0 0x1c0000>;
+ no-map;
+ };
+
+ qtee_mem: qtee-region@d8300000 {
+ reg = <0 0xd8300000 0 0x500000>;
+ no-map;
+ };
+
+ hwfence_shbuf: hwfence-shbuf-region@e6440000 {
+ reg = <0 0xe6440000 0 0x2dd000>;
+ no-map;
+ };
+
+ hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
+ reg = <0 0xff700000 0 0x100000>;
+ no-map;
+ };
+
+ llcc_lpi_mem: llcc_lpi_region@ff800000 {
+ reg = <0 0xff800000 0 0x600000>;
+ no-map;
+ };
+
+ hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
+ reg = <0 0xfce00000 0 0x2900000>;
+ no-map;
+ };
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ pinctrl-0 = <&lpi_i2s3_active>;
+ pinctrl-names = "default";
+
+ model = "AYN-Odin2";
+ audio-routing = "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "TX SWR_INPUT1", "ADC2_OUTPUT";
+
+ speaker-i2s-dai-link {
+ link-name = "Primary MI2S Playback";
+
+ codec {
+ sound-dai = <&spk_amp_l>, <&spk_amp_r>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ dp0-dai-link {
+ link-name = "DP0 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu0-thermal {
+ polling-delay = <200>;
+
+ trips {
+ cpuss0_active0: cpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active1: cpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active2: cpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active3: cpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active4: cpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active5: cpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active6: cpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active7: cpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&cpuss0_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&cpuss0_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&cpuss0_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&cpuss0_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&cpuss0_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&cpuss0_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&cpuss0_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&cpuss0_active7>;
+ };
+ };
+ };
+
+ cpu3-bottom-thermal {
+ polling-delay = <200>;
+
+ trips {
+ cpuss3_active0: cpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active1: cpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active2: cpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active3: cpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active4: cpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active5: cpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active6: cpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active7: cpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&cpuss3_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&cpuss3_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&cpuss3_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&cpuss3_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&cpuss3_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&cpuss3_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&cpuss3_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&cpuss3_active7>;
+ };
+ };
+ };
+
+ cpu7-bottom-thermal {
+ polling-delay = <200>;
+
+ trips {
+ cpuss7_active0: cpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active1: cpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active2: cpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active3: cpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active4: cpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active5: cpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active6: cpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active7: cpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&cpuss7_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&cpuss7_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&cpuss7_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&cpuss7_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&cpuss7_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&cpuss7_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&cpuss7_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&cpuss7_active7>;
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ polling-delay = <200>;
+
+ trips {
+ gpuss0_active0: gpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active1: gpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active2: gpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active3: gpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active4: gpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active5: gpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active6: gpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active7: gpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&gpuss0_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&gpuss0_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&gpuss0_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&gpuss0_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&gpuss0_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&gpuss0_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&gpuss0_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&gpuss0_active7>;
+ };
+ };
+ };
+ };
+
+ usb0-sbu-mux {
+ compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+ enable-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
+ select-gpios = <&tlmm 141 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&usb0_sbu_default>;
+ pinctrl-names = "default";
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ usb0_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ vdd_fan_5v0: vdd-fan-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_fan_5v0";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&fan_pwr_active>;
+ pinctrl-names = "default";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_mcu_3v3: vdd-mcu-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mcu_3v3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000
+ 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
+ pinctrl-names = "default";
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s5g_0p8>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p8>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p3>;
+ vddrfa1p8-supply = <&vreg_s6g_1p8>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+
+ // The arch_timer label is unused here, but is required by ABL to apply a dtbo
+ arch_timer: timer { };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p3>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p3>;
+ vdd-l12-supply = <&vreg_s6g_1p8>;
+ vdd-l15-supply = <&vreg_s6g_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p3>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p3>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p3>;
+ vdd-l2-supply = <&vreg_s4g_1p3>;
+ vdd-l3-supply = <&vreg_s4g_1p3>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_s1g_1p2: smps1 {
+ regulator-name = "vreg_s1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p8: smps2 {
+ regulator-name = "vreg_s2g_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p7: smps3 {
+ regulator-name = "vreg_s3g_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p3: smps4 {
+ regulator-name = "vreg_s4g_1p3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p8: smps5 {
+ regulator-name = "vreg_s5g_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p8: smps6 {
+ regulator-name = "vreg_s6g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&i2c_hub_2 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ spk_amp_l: amplifier@34 {
+ compatible = "awinic,aw88166";
+ reg = <0x34>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>;
+ awinic,audio-channel = <0>;
+ awinic,sync-flag;
+ sound-name-prefix = "SPK_L";
+ };
+
+ spk_amp_r: amplifier@35 {
+ compatible = "awinic,aw88166";
+ reg = <0x35>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
+ awinic,audio-channel = <1>;
+ awinic,sync-flag;
+ sound-name-prefix = "SPK_R";
+ };
+};
+
+&iris {
+ status = "okay";
+};
+
+&lpass_tlmm {
+ lpi_i2s3_active: lpi_i2s3-active-state {
+ sck-pins {
+ pins = "gpio12";
+ function = "i2s3_clk";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ ws-pins {
+ pins = "gpio13";
+ function = "i2s3_ws";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data0-pins {
+ pins = "gpio17";
+ function = "i2s3_data";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data1-pins {
+ pins = "gpio18";
+ function = "i2s3_data";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&lpass_vamacro {
+ qcom,dmic-sample-rate = <4800000>;
+};
+
+&lpass_wsamacro {
+ status = "disabled";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dsi1 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+
+ display_panel: panel@0 {
+ reg = <0>;
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&mdss_dsi1_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi1_out {
+ remote-endpoint = <&panel1_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi1_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ fan_pwm_active: fan-pwm-active-state {
+ pins = "gpio8";
+ function = "func1";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <1>;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-n-state {
+ pins = "gpio12";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-up;
+ power-source = <1>;
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0xb>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x3>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+
+ pwm_backlight_default: pwm-backlight-default-state {
+ pins = "gpio5";
+ function = "func3";
+ input-disable;
+ output-low;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <2>;
+ };
+};
+
+&pmk8550_rtc {
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "offset";
+};
+
+&pmk8550_sdam_2 {
+ rtc_offset: rtc-offset@bc {
+ reg = <0xbc 0x4>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/ayntec/cdsp.mbn",
+ "qcom/sm8550/ayntec/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ no-sdio;
+ no-mmc;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ mcu_en_active: mcu-en-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ fan_int: fan-int-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_s_rst_default: ts-s-rst-default-state {
+ pins = "gpio14";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_s_rst_sleep: ts-s-rst-sleep-state {
+ pins = "gpio14";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ ts_s_int_default: ts-s-int-default-state {
+ pins = "gpio15";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_s_int_sleep: ts-s-int-sleep-state {
+ pins = "gpio15";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ ts_p_rst_default: ts-p-rst-default-state {
+ pins = "gpio24";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_p_rst_sleep: ts-p-rst-sleep-state {
+ pins = "gpio24";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ ts_p_int_default: ts-p-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_p_int_sleep: ts-p-int-sleep-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ dsi_p_te_active: dsi-p-te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_p_te_suspend: dsi-s-te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_s_te_active: dsi-s-te-active-state {
+ pins = "gpio87";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_s_te_suspend: dsi-s-te-suspend-state {
+ pins = "gpio87";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio108";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ fan_pwr_active: fan-pwr-active-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ dsi_p_rst_active: dsi-p-rst-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_p_rst_suspend: dsi-p-rst-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_s_rst_active: dsi-s-rst-active-state {
+ pins = "gpio137";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_s_rst_suspend: dsi-s-rst-suspend-state {
+ pins = "gpio137";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ usb0_sbu_default: usb0-sbu-state {
+ oe-n-pins {
+ pins = "gpio140";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ output-high;
+ };
+
+ sel-pins {
+ pins = "gpio141";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+ max-speed = <3200000>;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ phys = <&pm8550b_eusb2_repeater>;
+
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 3/5] arm64: dts: qcom: Add AYN Odin 2 Mini
2026-03-23 2:05 [PATCH v3 0/5] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 1/5] dt-bindings: arm: qcom: Add " Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 2/5] arm64: dts: qcom: Add AYN QCS8550 Common Aaron Kling via B4 Relay
@ 2026-03-23 2:05 ` Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 4/5] arm64: dts: qcom: Add AYN Odin 2 Portal Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 5/5] arm64: dts: qcom: Add AYN Thor Aaron Kling via B4 Relay
4 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-03-23 2:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin
From: Teguh Sobirin <teguh@sobir.in>
The AYN Odin 2 Mini is a high-performance Android-based handheld gaming
console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring a
5-inch mini-led touchscreen.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-ayntec-odin2mini.dts | 140 +++++++++++++++++++++
2 files changed, 141 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..b42b7ef0a670b76234c063fa1aaf14a4691dba61 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -163,6 +163,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2mini.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts
new file mode 100644
index 0000000000000000000000000000000000000000..c2a1b85b66e314e277181f0036a0988060368243
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "qcs8550-ayntec-common.dtsi"
+
+&{/} {
+ model = "AYN Odin 2 Mini";
+ compatible = "ayntec,odin2mini", "qcom,qcs8550", "qcom,sm8550";
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+ hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
+ hdmi-pwr-supply = <&vdd_hdmi_1v8>;
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+
+ vcc_hdmi_1v8: vcc-hdmi-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_hdmi_1v8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp_2v8: vdd-disp-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_hdmi_1v8: vdd-hdmi-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_hdmi_1v8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&i2c_hub_0 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lt8912_codec: hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&vdd_hdmi_1v8>;
+ vccmipirx-supply = <&vcc_hdmi_1v8>;
+ vccsysclk-supply = <&vcc_hdmi_1v8>;
+ vcclvdstx-supply = <&vcc_hdmi_1v8>;
+ vcchdmitx-supply = <&vcc_hdmi_1v8>;
+ vcclvdspll-supply = <&vcc_hdmi_1v8>;
+ vcchdmipll-supply = <&vcc_hdmi_1v8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&hdmi_out_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayntec/odin2mini/adsp.mbn",
+ "qcom/sm8550/ayntec/odin2mini/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&spk_amp_l {
+ firmware-name = "qcom/sm8550/ayntec/odin2mini/aw883xx_acf.bin";
+};
+
+&spk_amp_r {
+ firmware-name = "qcom/sm8550/ayntec/odin2mini/aw883xx_acf.bin";
+};
+
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 4/5] arm64: dts: qcom: Add AYN Odin 2 Portal
2026-03-23 2:05 [PATCH v3 0/5] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
` (2 preceding siblings ...)
2026-03-23 2:05 ` [PATCH v3 3/5] arm64: dts: qcom: Add AYN Odin 2 Mini Aaron Kling via B4 Relay
@ 2026-03-23 2:05 ` Aaron Kling via B4 Relay
2026-03-23 2:05 ` [PATCH v3 5/5] arm64: dts: qcom: Add AYN Thor Aaron Kling via B4 Relay
4 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-03-23 2:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin
From: Teguh Sobirin <teguh@sobir.in>
The AYN Odin 2 Portal is a high-performance Android-based handheld gaming
console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring a
7-inch OLED touchscreen.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-ayntec-odin2portal.dts | 84 ++++++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index b42b7ef0a670b76234c063fa1aaf14a4691dba61..10e0506a52bdbfefbed2f06899cbe2f5a1894f63 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -164,6 +164,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2mini.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2portal.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts
new file mode 100644
index 0000000000000000000000000000000000000000..bd6ba0ab941d3325f76f53e7ed65478c67b9d028
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "qcs8550-ayntec-common.dtsi"
+
+&{/} {
+ model = "AYN Odin 2 Portal";
+ compatible = "ayntec,odin2portal", "qcom,qcs8550", "qcom,sm8550";
+
+ vdd_bl_5v0: vdd-bl-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl_5v0";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp_2v8: vdd-disp-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft5426";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l14b_3p2>;
+ iovcc-supply = <&vreg_l12b_1p8>;
+
+ pinctrl-0 = <&ts_p_rst_default &ts_p_int_default>;
+ pinctrl-1 = <&ts_p_rst_sleep &ts_p_int_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-y;
+ };
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayntec/odin2portal/adsp.mbn",
+ "qcom/sm8550/ayntec/odin2portal/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&spk_amp_l {
+ firmware-name = "qcom/sm8550/ayntec/odin2portal/aw883xx_acf.bin";
+};
+
+&spk_amp_r {
+ firmware-name = "qcom/sm8550/ayntec/odin2portal/aw883xx_acf.bin";
+};
+
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 5/5] arm64: dts: qcom: Add AYN Thor
2026-03-23 2:05 [PATCH v3 0/5] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
` (3 preceding siblings ...)
2026-03-23 2:05 ` [PATCH v3 4/5] arm64: dts: qcom: Add AYN Odin 2 Portal Aaron Kling via B4 Relay
@ 2026-03-23 2:05 ` Aaron Kling via B4 Relay
4 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-03-23 2:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin
From: Teguh Sobirin <teguh@sobir.in>
The AYN Thor is a high-performance Android-based handheld gaming console
powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring dual
AMOLED touchscreens.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts | 230 +++++++++++++++++++++++
2 files changed, 231 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 10e0506a52bdbfefbed2f06899cbe2f5a1894f63..bef7c472868c2463ab0c0d533cdbe831e8663dda 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -165,6 +165,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2mini.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2portal.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-thor.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts
new file mode 100644
index 0000000000000000000000000000000000000000..00f4032628df2e8d8729a1e93f5cf6dda9420a6d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "qcs8550-ayntec-common.dtsi"
+
+&{/} {
+ model = "AYN Thor";
+ compatible = "ayntec,thor", "qcom,qcs8550", "qcom,sm8550";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n &key_ayn_n>;
+
+ key-ayn {
+ label = "AYN Key";
+ debounce-interval = <15>;
+ gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F24>;
+ linux,can-disable;
+ };
+
+ switch-lid {
+ label = "Hall Lid Sensor";
+ gpios = <&tlmm 17 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ vdd_bl_5v0: vdd-bl-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl_5v0";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp_1v8: vdd-disp-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp_1v8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp1_2v8: vdd-disp1-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp1_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp2_2v8: vdd-disp2-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp2_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 143 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_ts_3v0: vdd-ts-3v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ts_3v0";
+
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ gpio = <&tlmm 144 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_ts_1v8: vdd-ts-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ts_1v8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft5426";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l14b_3p2>;
+ iovcc-supply = <&vreg_l12b_1p8>;
+
+ pinctrl-0 = <&ts_p_rst_default &ts_p_int_default>;
+ pinctrl-1 = <&ts_p_rst_sleep &ts_p_int_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
+ };
+};
+
+&i2c_hub_3 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft5452";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 14 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vdd_ts_3v0>;
+ iovcc-supply = <&vdd_ts_1v8>;
+
+ pinctrl-0 = <&ts_s_rst_default &ts_s_int_default>;
+ pinctrl-1 = <&ts_s_rst_sleep &ts_s_int_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1240>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
+ };
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ reg = <0>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&mdss_dsi1_out {
+ qcom,te-source = "mdp_vsync_s";
+};
+
+&pm8550_pwm {
+ multi-led {
+ status = "disabled";
+ };
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayntec/thor/adsp.mbn",
+ "qcom/sm8550/ayntec/thor/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&spk_amp_l {
+ firmware-name = "qcom/sm8550/ayntec/thor/aw883xx_acf.bin";
+};
+
+&spk_amp_r {
+ firmware-name = "qcom/sm8550/ayntec/thor/aw883xx_acf.bin";
+};
+
+&tlmm {
+ key_ayn_n: key-ayn-n-state {
+ pins = "gpio41";
+ function = "gpio";
+ bias-pull-up;
+ output-disable;
+ };
+};
--
2.53.0
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