[PATCH 0/5] Add eDP reference clock voting support

[PATCH 0/5] Add eDP reference clock voting support

[Ritesh Kumar]

eDP reference clock is required to be enabled before eDP PHY
initialization. On lemans chipset it is being voted from
qmp ufs phy driver. This series adds support for voting the clock
from eDP PHY driver.

---
Ritesh Kumar (5):
  dt-bindings: phy: Add edp reference clock for qcom,edp-phy
  dt-bindings: display/msm: update edp phy example
  phy: qcom: edp: Add support for edp reference clock vote
  arm64: dts: qcom: Add edp reference clock for edp phy
  arm64: dts: qcom: Add edp reference clock for edp phy

 .../display/msm/qcom,sa8775p-mdss.yaml        |  6 ++--
 .../display/msm/qcom,sc7280-mdss.yaml         |  6 ++--
 .../devicetree/bindings/phy/qcom,edp-phy.yaml |  7 ++--
 arch/arm64/boot/dts/qcom/lemans.dtsi          | 12 ++++---
 arch/arm64/boot/dts/qcom/sc7280.dtsi          |  6 ++--
 arch/arm64/boot/dts/qcom/sc8180x.dtsi         | 11 ++++--
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        | 36 ++++++++++++-------
 arch/arm64/boot/dts/qcom/x1e80100.dtsi        | 12 ++++---
 drivers/phy/qualcomm/phy-qcom-edp.c           |  3 +-
 9 files changed, 67 insertions(+), 32 deletions(-)

-- 
2.17.1

[PATCH 1/5] dt-bindings: phy: Add edp reference clock for qcom,edp-phy

[Ritesh Kumar]

Add edp reference clock for qcom,edp-phy which is required
to be enabled before eDP PHY initialization.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
index eb97181cbb95..95e9210f4163 100644
--- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
@@ -37,12 +37,13 @@ properties:
       - description: PLL register block
 
   clocks:
-    maxItems: 2
+    maxItems: 3
 
   clock-names:
     items:
       - const: aux
       - const: cfg_ahb
+      - const: edp_ref
 
   "#clock-cells":
     const: 1
@@ -75,8 +76,8 @@ examples:
             <0x0aec2600 0xa0>,
             <0x0aec2000 0x19c>;
 
-      clocks = <&dispcc 0>, <&dispcc 1>;
-      clock-names = "aux", "cfg_ahb";
+      clocks = <&dispcc 0>, <&dispcc 1>, <&dispcc 2>;
+      clock-names = "aux", "cfg_ahb", "edp_ref";
 
       #clock-cells = <1>;
       #phy-cells = <0>;
-- 
2.17.1

Re: [PATCH 1/5] dt-bindings: phy: Add edp reference clock for qcom,edp-phy

[Krzysztof Kozlowski]

On 09/10/2025 16:11, Ritesh Kumar wrote:
> Add edp reference clock for qcom,edp-phy which is required
> to be enabled before eDP PHY initialization.
> 

No, you need to first look what is happening in community.

https://lore.kernel.org/all/20250909-phy-qcom-edp-add-missing-refclk-v3-1-4ec55a0512ab@linaro.org/

Best regards,
Krzysztof

Re: [PATCH 1/5] dt-bindings: phy: Add edp reference clock for qcom,edp-phy

[Ritesh Kumar]

On 10/9/2025 2:57 PM, Krzysztof Kozlowski wrote:
> On 09/10/2025 16:11, Ritesh Kumar wrote:
> > Add edp reference clock for qcom,edp-phy which is required
> > to be enabled before eDP PHY initialization.
> > 
>
> No, you need to first look what is happening in community.
>
> https://lore.kernel.org/all/20250909-phy-qcom-edp-add-missing-refclk-v3-1-4ec55a0512ab@linaro.org/

Thanks for the patch. I will pick this and add support for lemans and 
post v2.

>
> Best regards,
> Krzysztof

Re: [PATCH 1/5] dt-bindings: phy: Add edp reference clock for qcom,edp-phy

[Rob Herring (Arm)]

On Thu, 09 Oct 2025 12:41:23 +0530, Ritesh Kumar wrote:
> Add edp reference clock for qcom,edp-phy which is required
> to be enabled before eDP PHY initialization.
> 
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> ---
>  Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.example.dtb: phy@aec2a00 (qcom,sa8775p-edp-phy): clock-names: ['aux', 'cfg_ahb'] is too short
	from schema $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.example.dtb: phy@aec2a00 (qcom,sa8775p-edp-phy): clocks: [[4294967295, 11], [4294967295, 1]] is too short
	from schema $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.example.dtb: phy@aec2a00 (qcom,sc7280-edp-phy): clock-names: ['aux', 'cfg_ahb'] is too short
	from schema $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.example.dtb: phy@aec2a00 (qcom,sc7280-edp-phy): clocks: [[4294967295, 0], [4294967295, 183]] is too short
	from schema $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20251009071127.26026-2-quic_riteshk@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH 2/5] dt-bindings: display/msm: update edp phy example

[Ritesh Kumar]

Update clock entry in edp phy example node of sa8775p and
sc7280 to add edp referece clock.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml  | 6 ++++--
 .../devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml   | 6 ++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index e2730a2f25cf..5c0fa95244d7 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -200,9 +200,11 @@ examples:
                   <0x0aec2000 0x1c8>;
 
             clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
-                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                     <&gcc GCC_EDP_REF_CLKREF_EN>;
             clock-names = "aux",
-                          "cfg_ahb";
+                          "cfg_ahb",
+                          "edp_ref";
 
             #clock-cells = <1>;
             #phy-cells = <0>;
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
index b643d3adf669..02568b6e349e 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
@@ -357,10 +357,12 @@ examples:
                   <0xaec2600 0xa0>,
                   <0xaec2000 0x1c0>;
 
-            clocks = <&rpmhcc RPMH_CXO_CLK>,
+            clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
+                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                      <&gcc GCC_EDP_CLKREF_EN>;
             clock-names = "aux",
-                          "cfg_ahb";
+                          "cfg_ahb",
+                          "edp_ref";
 
             #clock-cells = <1>;
             #phy-cells = <0>;
-- 
2.17.1

[PATCH 3/5] phy: qcom: edp: Add support for edp reference clock vote

[Ritesh Kumar]

Commit 77d2fa54a9457 ("scsi: ufs: qcom : Refactor phy_power_on/off
calls") lead to edp reference clock to be turned off, leading to
below phy poweron failure on lemans edp phy.

phy phy-aec2a00.phy.10: phy poweron failed --> -110

edp reference clock is required to be enabled before edp PHY
initialization. This change adds support for voting the clock
from edp phy driver.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 drivers/phy/qualcomm/phy-qcom-edp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index f1b51018683d..b544b5988fa6 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -103,7 +103,7 @@ struct qcom_edp {
 
 	struct phy_configure_opts_dp dp_opts;
 
-	struct clk_bulk_data clks[2];
+	struct clk_bulk_data clks[3];
 	struct regulator_bulk_data supplies[2];
 
 	bool is_edp;
@@ -1094,6 +1094,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev)
 
 	edp->clks[0].id = "aux";
 	edp->clks[1].id = "cfg_ahb";
+	edp->clks[2].id = "edp_ref";
 	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks);
 	if (ret)
 		return ret;
-- 
2.17.1

Re: [PATCH 3/5] phy: qcom: edp: Add support for edp reference clock vote

[Krzysztof Kozlowski]

On 09/10/2025 16:11, Ritesh Kumar wrote:
> Commit 77d2fa54a9457 ("scsi: ufs: qcom : Refactor phy_power_on/off
> calls") lead to edp reference clock to be turned off, leading to
> below phy poweron failure on lemans edp phy.
> 

Also NAK, duplicated work.

Best regards,
Krzysztof

[PATCH 4/5] arm64: dts: qcom: Add edp reference clock for edp phy

[Ritesh Kumar]

Add edp reference clock for edp phy on lemans, sc7280
and x1e80100 chipsets.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi   | 12 ++++++++----
 arch/arm64/boot/dts/qcom/sc7280.dtsi   |  6 ++++--
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++----
 3 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index cf685cb186ed..e8deb50f248b 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5034,9 +5034,11 @@
 				      <0x0 0x0aec2000 0x0 0x1c8>;
 
 				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
-					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_EDP_REF_CLKREF_EN>;
 				clock-names = "aux",
-					      "cfg_ahb";
+					      "cfg_ahb",
+					      "edp_ref";
 
 				#clock-cells = <1>;
 				#phy-cells = <0>;
@@ -5053,9 +5055,11 @@
 				      <0x0 0x0aec5000 0x0 0x1c8>;
 
 				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
-					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_EDP_REF_CLKREF_EN>;
 				clock-names = "aux",
-					      "cfg_ahb";
+					      "cfg_ahb",
+					      "edp_ref";
 
 				#clock-cells = <1>;
 				#phy-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4b04dea57ec8..1af79bddcf38 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5222,10 +5222,12 @@
 				      <0 0x0aec2600 0 0xa0>,
 				      <0 0x0aec2000 0 0x1c0>;
 
-				clocks = <&rpmhcc RPMH_CXO_CLK>,
+				clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
 					 <&gcc GCC_EDP_CLKREF_EN>;
 				clock-names = "aux",
-					      "cfg_ahb";
+					      "cfg_ahb",
+					      "edp_ref";
 
 				#clock-cells = <1>;
 				#phy-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 51576d9c935d..c42c292267cc 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5817,9 +5817,11 @@
 			      <0 0x0aec2000 0 0x1c8>;
 
 			clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
-				 <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&tcsr TCSR_EDP_CLKREF_EN>;
 			clock-names = "aux",
-				      "cfg_ahb";
+				      "cfg_ahb",
+				      "edp_ref";
 
 			power-domains = <&rpmhpd RPMHPD_MX>;
 
@@ -5837,9 +5839,11 @@
 			      <0 0x0aec5000 0 0x1c8>;
 
 			clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
-				 <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&tcsr TCSR_EDP_CLKREF_EN>;
 			clock-names = "aux",
-				      "cfg_ahb";
+				      "cfg_ahb",
+				      "edp_ref";
 
 			power-domains = <&rpmhpd RPMHPD_MX>;
 
-- 
2.17.1

[PATCH 5/5] arm64: dts: qcom: Add edp reference clock for edp phy

[Ritesh Kumar]

Define edp reference clock as fixed clock and add it for
edp phy on sc8180x and sc8280xp chipsets.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8180x.dtsi  | 11 ++++++--
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 36 +++++++++++++++++---------
 2 files changed, 33 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 85c2afcb417d..392cc9eede48 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -27,6 +27,12 @@
 	#size-cells = <2>;
 
 	clocks {
+		edp_ref_clk: edp-ref-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
 		xo_board_clk: xo-board {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -3492,8 +3498,9 @@
 			      <0 0x0aec2000 0 0x19c>;
 
 			clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
-				 <&dispcc DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 
 			power-domains = <&rpmhpd SC8180X_MX>;
 
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 279e5e6beae2..d0a976aea46d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -29,6 +29,12 @@
 	#size-cells = <2>;
 
 	clocks {
+		edp_ref_clk: edp-ref-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
 		xo_board_clk: xo-board-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -3792,8 +3798,9 @@
 			      <0 0x08909000 0 0x1c8>;
 
 			clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
-				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 			power-domains = <&rpmhpd SC8280XP_MX>;
 
 			#clock-cells = <1>;
@@ -3810,8 +3817,9 @@
 			      <0 0x0890c000 0 0x1c8>;
 
 			clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
-				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 			power-domains = <&rpmhpd SC8280XP_MX>;
 
 			#clock-cells = <1>;
@@ -5022,8 +5030,9 @@
 			      <0 0x0aec2000 0 0x1c8>;
 
 			clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
-				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 			power-domains = <&rpmhpd SC8280XP_MX>;
 
 			#clock-cells = <1>;
@@ -5040,8 +5049,9 @@
 			      <0 0x0aec5000 0 0x1c8>;
 
 			clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
-				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 			power-domains = <&rpmhpd SC8280XP_MX>;
 
 			#clock-cells = <1>;
@@ -6368,8 +6378,9 @@
 			      <0 0x220c2000 0 0x1c8>;
 
 			clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
-				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 			power-domains = <&rpmhpd SC8280XP_MX>;
 
 			#clock-cells = <1>;
@@ -6386,8 +6397,9 @@
 			      <0 0x220c5000 0 0x1c8>;
 
 			clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
-				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
-			clock-names = "aux", "cfg_ahb";
+				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+				 <&edp_ref_clk>;
+			clock-names = "aux", "cfg_ahb", "edp_ref";
 			power-domains = <&rpmhpd SC8280XP_MX>;
 
 			#clock-cells = <1>;
-- 
2.17.1

Re: [PATCH 0/5] Add eDP reference clock voting support

[Konrad Dybcio]

On 10/9/25 9:11 AM, Ritesh Kumar wrote:
> eDP reference clock is required to be enabled before eDP PHY
> initialization. On lemans chipset it is being voted from
> qmp ufs phy driver.

?????????????????????????????????????????????????????????

Konrad