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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Aaron Kling <webgeek1234@gmail.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
Date: Wed, 18 Feb 2026 12:09:18 +0100	[thread overview]
Message-ID: <2a348e2a-d065-4e87-9921-8a327c9a2b81@oss.qualcomm.com> (raw)
In-Reply-To: <CALHNRZ98kp_uymSrjAGyCSus17tP9iGMYZ6T5HaAecEFyrw3mg@mail.gmail.com>

On 2/18/26 3:06 AM, Aaron Kling wrote:
> On Thu, Feb 12, 2026 at 5:59 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 2/8/26 2:28 AM, Aaron Kling via B4 Relay wrote:
>>> From: Aaron Kling <webgeek1234@gmail.com>
>>>
>>> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
>>> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
>>> frequency by aggregating bandwidth requests of all CPU core with referenc
>>> to the current OPP they are configured in by the LMH/EPSS hardware.
>>>
>>> The effect is a proper caches & DDR frequency scaling when CPU cores
>>> changes frequency.
>>>
>>> The OPP tables were built using the downstream memlat ddr, llcc & l3
>>> tables for each cluster types with the actual EPSS cpufreq LUT tables
>>> from running a QCS8550 device.
>>>
>>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
>>> ---
>>
>> [...]
>>
>>> +     cpu0_opp_table: opp-table-cpu0 {
>>> +             compatible = "operating-points-v2";
>>> +             opp-shared;
>>> +
>>> +             opp-307200000 {
>>> +                     opp-hz = /bits/ 64 <307200000>;
>>> +                     opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
>>
>> I think that entries below the first in that memlat table should use the lowest
>> frequency (i.e. if (freq > tbl_entry.min_freq) { vote_for(tbl_entry.bw) }), etc.
> 
> Let me make sure I understand what you're saying. Given the following
> example from the downstream dt:
> 
>         silver {
>             qcom,cpufreq-memfreq-tbl =
>                 < 1113600  547000 >,
>                 < 1555200  768000 >,
>                 < 2016000 1555000 >;
>         };
> 
> you're saying that everything up to but not including 1555200 should
> using 547000? So in effect, round down instead of round up like I did?

Yes, that's my reading of what downstream does (msm-5.10 snippet):

static u32 cpufreq_to_memfreq(struct memlat_mon *mon, u32 cpu_mhz)
{
	struct cpufreq_memfreq_map *map = mon->freq_map;
	u32 mem_khz = 0;

	if (!map)
		goto out;

	while (map->cpufreq_mhz && map->cpufreq_mhz < cpu_mhz)
		map++;
	if (!map->cpufreq_mhz)
		map--;
	mem_khz = map->memfreq_khz;

out:
	return mem_khz;
}

Konrad

      reply	other threads:[~2026-02-18 11:09 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-08  1:28 [PATCH 0/3] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
2026-02-08  1:28 ` [PATCH 1/3] arm64: dts: qcom: sm8550: add OSM L3 node Aaron Kling via B4 Relay
2026-02-09  9:04   ` Konrad Dybcio
2026-02-11 22:36     ` Aaron Kling
2026-02-08  1:28 ` [PATCH 2/3] arm64: dts: qcom: sm8550: add cpu interconnect nodes Aaron Kling via B4 Relay
2026-02-08  9:05   ` Krzysztof Kozlowski
2026-02-08  1:28 ` [PATCH 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-02-09 16:56   ` Neil Armstrong
2026-02-12 11:59   ` Konrad Dybcio
2026-02-18  2:06     ` Aaron Kling
2026-02-18 11:09       ` Konrad Dybcio [this message]

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