Re: [PATCH 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 2/8/26 2:28 AM, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
> 
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
> 
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
> 
> The OPP tables were built using the downstream memlat ddr, llcc & l3
> tables for each cluster types with the actual EPSS cpufreq LUT tables
> from running a QCS8550 device.
> 
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---

[...]

> +	cpu0_opp_table: opp-table-cpu0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-307200000 {
> +			opp-hz = /bits/ 64 <307200000>;
> +			opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;

I think that entries below the first in that memlat table should use the lowest
frequency (i.e. if (freq > tbl_entry.min_freq) { vote_for(tbl_entry.bw) }), etc.

You can retrieve the list of supported frequencies through debugfs if you apply
patch1 from my my in-flight patchset:

https://lore.kernel.org/linux-arm-msm/20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com/

via /sys/kernel/debug/qcom_smem/dram_frequencies

Konrad