* [PATCH 0/2] drm/msm: remove struct msm_display_dsc_config
@ 2022-07-11 10:04 Dmitry Baryshkov
2022-07-11 10:04 ` [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config Dmitry Baryshkov
2022-07-11 10:04 ` [PATCH 2/2] drm/msm/dsi: " Dmitry Baryshkov
0 siblings, 2 replies; 7+ messages in thread
From: Dmitry Baryshkov @ 2022-07-11 10:04 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
The struct msm_display_dsc_config contains just a single member, a
pointer to struct drm_dsc_config. Use the later one directly instead of
wrapping it in the additional struct.
Dmitry Baryshkov (2):
drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config
drm/msm/dsi: use drm_dsc_config instead of msm_display_dsc_config
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 74 ++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 4 +-
drivers/gpu/drm/msm/dsi/dsi.c | 2 +-
drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 157 +++++++++-----------
drivers/gpu/drm/msm/msm_drv.h | 9 +-
8 files changed, 131 insertions(+), 144 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config
2022-07-11 10:04 [PATCH 0/2] drm/msm: remove struct msm_display_dsc_config Dmitry Baryshkov
@ 2022-07-11 10:04 ` Dmitry Baryshkov
2022-07-16 0:22 ` Abhinav Kumar
2022-07-16 10:30 ` Marijn Suijten
2022-07-11 10:04 ` [PATCH 2/2] drm/msm/dsi: " Dmitry Baryshkov
1 sibling, 2 replies; 7+ messages in thread
From: Dmitry Baryshkov @ 2022-07-11 10:04 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
There is no need to use the struct msm_display_dsc_config wrapper inside
the dpu driver, use the struct drm_dsc_config directly to pass pps data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 +++----
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 74 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
5 files changed, 54 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index c682d4e02d1b..07b22b7df2e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -162,7 +162,7 @@ enum dpu_enc_rc_states {
* @vsync_event_work: worker to handle vsync event for autorefresh
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
- * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
+ * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
*/
struct dpu_encoder_virt {
struct drm_encoder base;
@@ -208,7 +208,7 @@ struct dpu_encoder_virt {
bool wide_bus_en;
/* DSC configuration */
- struct msm_display_dsc_config *dsc;
+ struct drm_dsc_config *dsc;
};
#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
@@ -1791,12 +1791,12 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
}
static u32
-dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
+dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
u32 enc_ip_width)
{
int ssm_delay, total_pixels, soft_slice_per_enc;
- soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
+ soft_slice_per_enc = enc_ip_width / dsc->slice_width;
/*
* minimum number of initial line pixels is a sum of:
@@ -1808,16 +1808,16 @@ dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
* 5. 6 additional pixels as the output of the rate buffer is
* 48 bits wide
*/
- ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
- total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
+ ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
+ total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
if (soft_slice_per_enc > 1)
total_pixels += (ssm_delay * 3);
- return DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
+ return DIV_ROUND_UP(total_pixels, dsc->slice_width);
}
static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
struct dpu_hw_pingpong *hw_pp,
- struct msm_display_dsc_config *dsc,
+ struct drm_dsc_config *dsc,
u32 common_mode,
u32 initial_lines)
{
@@ -1835,7 +1835,7 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
}
static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
- struct msm_display_dsc_config *dsc)
+ struct drm_dsc_config *dsc)
{
/* coding only for 2LM, 2enc, 1 dsc config */
struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
@@ -1858,14 +1858,15 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
}
}
- pic_width = dsc->drm->pic_width;
+ dsc_common_mode = 0;
+ pic_width = dsc->pic_width;
dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
if (enc_master->intf_mode == INTF_MODE_VIDEO)
dsc_common_mode |= DSC_MODE_VIDEO;
- this_frame_slices = pic_width / dsc->drm->slice_width;
- intf_ip_w = this_frame_slices * dsc->drm->slice_width;
+ this_frame_slices = pic_width / dsc->slice_width;
+ intf_ip_w = this_frame_slices * dsc->slice_width;
/*
* dsc merge case: when using 2 encoders for the same stream,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index d4d1ecd416e3..9e7236ef34e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -36,7 +36,7 @@ struct msm_display_info {
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
bool is_te_using_watchdog_timer;
- struct msm_display_dsc_config *dsc;
+ struct drm_dsc_config *dsc;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 184a1b27b13d..20a033cd323d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -37,7 +37,7 @@ static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
}
static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_config *dsc,
+ struct drm_dsc_config *dsc,
u32 mode,
u32 initial_lines)
{
@@ -52,89 +52,89 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
if (is_cmd_mode)
initial_lines += 1;
- slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
+ slice_last_group_size = 3 - (dsc->slice_width % 3);
data = (initial_lines << 20);
data |= ((slice_last_group_size - 1) << 18);
/* bpp is 6.4 format, 4 LSBs bits are for fractional part */
- data |= dsc->drm->bits_per_pixel << 12;
- lsb = dsc->drm->bits_per_pixel % 4;
- bpp = dsc->drm->bits_per_pixel / 4;
+ data |= dsc->bits_per_pixel << 12;
+ lsb = dsc->bits_per_pixel % 4;
+ bpp = dsc->bits_per_pixel / 4;
bpp *= 4;
bpp <<= 4;
bpp |= lsb;
data |= bpp << 8;
- data |= (dsc->drm->block_pred_enable << 7);
- data |= (dsc->drm->line_buf_depth << 3);
- data |= (dsc->drm->simple_422 << 2);
- data |= (dsc->drm->convert_rgb << 1);
- data |= dsc->drm->bits_per_component;
+ data |= (dsc->block_pred_enable << 7);
+ data |= (dsc->line_buf_depth << 3);
+ data |= (dsc->simple_422 << 2);
+ data |= (dsc->convert_rgb << 1);
+ data |= dsc->bits_per_component;
DPU_REG_WRITE(c, DSC_ENC, data);
- data = dsc->drm->pic_width << 16;
- data |= dsc->drm->pic_height;
+ data = dsc->pic_width << 16;
+ data |= dsc->pic_height;
DPU_REG_WRITE(c, DSC_PICTURE, data);
- data = dsc->drm->slice_width << 16;
- data |= dsc->drm->slice_height;
+ data = dsc->slice_width << 16;
+ data |= dsc->slice_height;
DPU_REG_WRITE(c, DSC_SLICE, data);
- data = dsc->drm->slice_chunk_size << 16;
+ data = dsc->slice_chunk_size << 16;
DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
- data = dsc->drm->initial_dec_delay << 16;
- data |= dsc->drm->initial_xmit_delay;
+ data = dsc->initial_dec_delay << 16;
+ data |= dsc->initial_xmit_delay;
DPU_REG_WRITE(c, DSC_DELAY, data);
- data = dsc->drm->initial_scale_value;
+ data = dsc->initial_scale_value;
DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
- data = dsc->drm->scale_decrement_interval;
+ data = dsc->scale_decrement_interval;
DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
- data = dsc->drm->scale_increment_interval;
+ data = dsc->scale_increment_interval;
DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
- data = dsc->drm->first_line_bpg_offset;
+ data = dsc->first_line_bpg_offset;
DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
- data = dsc->drm->nfl_bpg_offset << 16;
- data |= dsc->drm->slice_bpg_offset;
+ data = dsc->nfl_bpg_offset << 16;
+ data |= dsc->slice_bpg_offset;
DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
- data = dsc->drm->initial_offset << 16;
- data |= dsc->drm->final_offset;
+ data = dsc->initial_offset << 16;
+ data |= dsc->final_offset;
DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
- det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
+ det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8);
data = det_thresh_flatness << 10;
- data |= dsc->drm->flatness_max_qp << 5;
- data |= dsc->drm->flatness_min_qp;
+ data |= dsc->flatness_max_qp << 5;
+ data |= dsc->flatness_min_qp;
DPU_REG_WRITE(c, DSC_FLATNESS, data);
- data = dsc->drm->rc_model_size;
+ data = dsc->rc_model_size;
DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
- data = dsc->drm->rc_tgt_offset_low << 18;
- data |= dsc->drm->rc_tgt_offset_high << 14;
- data |= dsc->drm->rc_quant_incr_limit1 << 9;
- data |= dsc->drm->rc_quant_incr_limit0 << 4;
- data |= dsc->drm->rc_edge_factor;
+ data = dsc->rc_tgt_offset_low << 18;
+ data |= dsc->rc_tgt_offset_high << 14;
+ data |= dsc->rc_quant_incr_limit1 << 9;
+ data |= dsc->rc_quant_incr_limit0 << 4;
+ data |= dsc->rc_edge_factor;
DPU_REG_WRITE(c, DSC_RC, data);
}
static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_config *dsc)
+ struct drm_dsc_config *dsc)
{
- struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
+ struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params;
struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
u32 off;
int i;
off = DSC_RC_BUF_THRESH;
for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
- DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
+ DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]);
off += 4;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
index 45e4118f1fa2..c0b77fe1a696 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -31,7 +31,7 @@ struct dpu_hw_dsc_ops {
* @initial_lines: amount of initial lines to be used
*/
void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_config *dsc,
+ struct drm_dsc_config *dsc,
u32 mode,
u32 initial_lines);
@@ -41,7 +41,7 @@ struct dpu_hw_dsc_ops {
* @dsc: panel dsc parameters
*/
void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_config *dsc);
+ struct drm_dsc_config *dsc);
};
struct dpu_hw_dsc {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 75ed2b36e1b3..8016d0a3aade 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -585,7 +585,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.h_tile_instance[info.num_of_h_tiles++] = i;
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
+ info.dsc = msm_dsi_get_dsc_config(priv->dsi[i])->drm;
if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/msm/dsi: use drm_dsc_config instead of msm_display_dsc_config
2022-07-11 10:04 [PATCH 0/2] drm/msm: remove struct msm_display_dsc_config Dmitry Baryshkov
2022-07-11 10:04 ` [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config Dmitry Baryshkov
@ 2022-07-11 10:04 ` Dmitry Baryshkov
2022-07-16 0:28 ` [Freedreno] " Abhinav Kumar
2022-07-16 10:31 ` Marijn Suijten
1 sibling, 2 replies; 7+ messages in thread
From: Dmitry Baryshkov @ 2022-07-11 10:04 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
There is no need to use the struct msm_display_dsc_config wrapper inside
the dsi driver, use the struct drm_dsc_config directly to pass pps data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/dsi/dsi.c | 2 +-
drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 157 +++++++++++-------------
drivers/gpu/drm/msm/msm_drv.h | 9 +-
5 files changed, 79 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8016d0a3aade..75ed2b36e1b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -585,7 +585,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.h_tile_instance[info.num_of_h_tiles++] = i;
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.dsc = msm_dsi_get_dsc_config(priv->dsi[i])->drm;
+ info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 1625328fa430..8f1ed31b048a 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -21,7 +21,7 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
return !(host_flags & MIPI_DSI_MODE_VIDEO);
}
-struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
+struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
{
return msm_dsi_host_get_dsc_config(msm_dsi->host);
}
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 580a1e6358bf..df46cdda1b43 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -154,7 +154,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
-struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
+struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
/* dsi phy */
struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a34078497af1..15e108be1901 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -33,7 +33,7 @@
#define DSI_RESET_TOGGLE_DELAY_MS 20
-static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
+static int dsi_populate_dsc_params(struct drm_dsc_config *dsc);
static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
{
@@ -161,7 +161,7 @@ struct msm_dsi_host {
struct regmap *sfpb;
struct drm_display_mode *mode;
- struct msm_display_dsc_config *dsc;
+ struct drm_dsc_config *dsc;
/* connected device info */
struct device_node *device_node;
@@ -916,7 +916,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
{
- struct msm_display_dsc_config *dsc = msm_host->dsc;
+ struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, intf_width, reg_ctrl, reg_ctrl2;
u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line;
@@ -927,24 +927,24 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
* compress mode registers
*/
intf_width = hdisplay;
- slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
+ slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
/* If slice_per_pkt is greater than slice_per_intf
* then default to 1. This can happen during partial
* update.
*/
- if (slice_per_intf > dsc->drm->slice_count)
- dsc->drm->slice_count = 1;
+ if (slice_per_intf > dsc->slice_count)
+ dsc->slice_count = 1;
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
- bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * dsc->drm->bits_per_pixel, 8);
+ slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8);
- dsc->drm->slice_chunk_size = bytes_in_slice;
+ dsc->slice_chunk_size = bytes_in_slice;
total_bytes_per_intf = bytes_in_slice * slice_per_intf;
eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->drm->slice_count;
+ pkt_per_line = slice_per_intf / dsc->slice_count;
if (is_cmd_mode) /* packet data type */
reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -1009,7 +1009,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
}
if (msm_host->dsc) {
- struct msm_display_dsc_config *dsc = msm_host->dsc;
+ struct drm_dsc_config *dsc = msm_host->dsc;
/* update dsc params with timing params */
if (!dsc || !mode->hdisplay || !mode->vdisplay) {
@@ -1018,9 +1018,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
return;
}
- dsc->drm->pic_width = mode->hdisplay;
- dsc->drm->pic_height = mode->vdisplay;
- DBG("Mode %dx%d\n", dsc->drm->pic_width, dsc->drm->pic_height);
+ dsc->pic_width = mode->hdisplay;
+ dsc->pic_height = mode->vdisplay;
+ DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
/* we do the calculations for dsc parameters here so that
* panel can use these parameters
@@ -1841,7 +1841,7 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = {
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
};
-static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
+static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
{
int mux_words_size;
int groups_per_line, groups_total;
@@ -1854,98 +1854,98 @@ static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
int final_value, final_scale;
int i;
- dsc->drm->rc_model_size = 8192;
- dsc->drm->first_line_bpg_offset = 12;
- dsc->drm->rc_edge_factor = 6;
- dsc->drm->rc_tgt_offset_high = 3;
- dsc->drm->rc_tgt_offset_low = 3;
- dsc->drm->simple_422 = 0;
- dsc->drm->convert_rgb = 1;
- dsc->drm->vbr_enable = 0;
+ dsc->rc_model_size = 8192;
+ dsc->first_line_bpg_offset = 12;
+ dsc->rc_edge_factor = 6;
+ dsc->rc_tgt_offset_high = 3;
+ dsc->rc_tgt_offset_low = 3;
+ dsc->simple_422 = 0;
+ dsc->convert_rgb = 1;
+ dsc->vbr_enable = 0;
/* handle only bpp = bpc = 8 */
for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
- dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
+ dsc->rc_range_params[i].range_min_qp = min_qp[i];
+ dsc->rc_range_params[i].range_max_qp = max_qp[i];
+ dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i];
}
- dsc->drm->initial_offset = 6144; /* Not bpp 12 */
- if (dsc->drm->bits_per_pixel != 8)
- dsc->drm->initial_offset = 2048; /* bpp = 12 */
+ dsc->initial_offset = 6144; /* Not bpp 12 */
+ if (dsc->bits_per_pixel != 8)
+ dsc->initial_offset = 2048; /* bpp = 12 */
mux_words_size = 48; /* bpc == 8/10 */
- if (dsc->drm->bits_per_component == 12)
+ if (dsc->bits_per_component == 12)
mux_words_size = 64;
- dsc->drm->initial_xmit_delay = 512;
- dsc->drm->initial_scale_value = 32;
- dsc->drm->first_line_bpg_offset = 12;
- dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
+ dsc->initial_xmit_delay = 512;
+ dsc->initial_scale_value = 32;
+ dsc->first_line_bpg_offset = 12;
+ dsc->line_buf_depth = dsc->bits_per_component + 1;
/* bpc 8 */
- dsc->drm->flatness_min_qp = 3;
- dsc->drm->flatness_max_qp = 12;
- dsc->drm->rc_quant_incr_limit0 = 11;
- dsc->drm->rc_quant_incr_limit1 = 11;
- dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ dsc->flatness_min_qp = 3;
+ dsc->flatness_max_qp = 12;
+ dsc->rc_quant_incr_limit0 = 11;
+ dsc->rc_quant_incr_limit1 = 11;
+ dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
/* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
* params are calculated
*/
- groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
- dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
- if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
- dsc->drm->slice_chunk_size++;
+ groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
+ dsc->slice_chunk_size = dsc->slice_width * dsc->bits_per_pixel / 8;
+ if ((dsc->slice_width * dsc->bits_per_pixel) % 8)
+ dsc->slice_chunk_size++;
/* rbs-min */
- min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
- dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
- groups_per_line * dsc->drm->first_line_bpg_offset;
+ min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset +
+ dsc->initial_xmit_delay * dsc->bits_per_pixel +
+ groups_per_line * dsc->first_line_bpg_offset;
- hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
+ hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel);
- dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
+ dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
- dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
- (dsc->drm->rc_model_size - dsc->drm->initial_offset);
+ dsc->initial_scale_value = 8 * dsc->rc_model_size /
+ (dsc->rc_model_size - dsc->initial_offset);
- slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
+ slice_bits = 8 * dsc->slice_chunk_size * dsc->slice_height;
- groups_total = groups_per_line * dsc->drm->slice_height;
+ groups_total = groups_per_line * dsc->slice_height;
- data = dsc->drm->first_line_bpg_offset * 2048;
+ data = dsc->first_line_bpg_offset * 2048;
- dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
+ dsc->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->slice_height - 1));
- pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
+ pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->bits_per_component + 4) - 2);
num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
- data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
- dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
+ data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits);
+ dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
/* bpp * 16 + 0.5 */
- data = dsc->drm->bits_per_pixel * 16;
+ data = dsc->bits_per_pixel * 16;
data *= 2;
data++;
data /= 2;
target_bpp_x16 = data;
- data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
- final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
- dsc->drm->final_offset = final_value;
+ data = (dsc->initial_xmit_delay * target_bpp_x16) / 16;
+ final_value = dsc->rc_model_size - data + num_extra_mux_bits;
+ dsc->final_offset = final_value;
- final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
+ final_scale = 8 * dsc->rc_model_size / (dsc->rc_model_size - final_value);
- data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
- dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
+ data = (final_scale - 9) * (dsc->nfl_bpg_offset + dsc->slice_bpg_offset);
+ dsc->scale_increment_interval = (2048 * dsc->final_offset) / data;
- dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
+ dsc->scale_decrement_interval = groups_per_line / (dsc->initial_scale_value - 8);
return 0;
}
@@ -2165,17 +2165,8 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
msm_host->dev = dev;
panel = msm_dsi_host_get_panel(&msm_host->base);
- if (!IS_ERR(panel) && panel->dsc) {
- struct msm_display_dsc_config *dsc = msm_host->dsc;
-
- if (!dsc) {
- dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
- if (!dsc)
- return -ENOMEM;
- dsc->drm = panel->dsc;
- msm_host->dsc = dsc;
- }
- }
+ if (!IS_ERR(panel) && panel->dsc)
+ msm_host->dsc = panel->dsc;
ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
if (ret) {
@@ -2659,22 +2650,22 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
const struct drm_display_mode *mode)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
- struct msm_display_dsc_config *dsc = msm_host->dsc;
+ struct drm_dsc_config *dsc = msm_host->dsc;
int pic_width = mode->hdisplay;
int pic_height = mode->vdisplay;
if (!msm_host->dsc)
return MODE_OK;
- if (pic_width % dsc->drm->slice_width) {
+ if (pic_width % dsc->slice_width) {
pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
- pic_width, dsc->drm->slice_width);
+ pic_width, dsc->slice_width);
return MODE_H_ILLEGAL;
}
- if (pic_height % dsc->drm->slice_height) {
+ if (pic_height % dsc->slice_height) {
pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
- pic_height, dsc->drm->slice_height);
+ pic_height, dsc->slice_height);
return MODE_V_ILLEGAL;
}
@@ -2771,7 +2762,7 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
}
-struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
+struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index ae49e56ac026..8075a0e010a5 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -96,11 +96,6 @@ struct msm_drm_thread {
struct kthread_worker *worker;
};
-/* DSC config */
-struct msm_display_dsc_config {
- struct drm_dsc_config *drm;
-};
-
struct msm_drm_private {
struct drm_device *dev;
@@ -289,7 +284,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
-struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
+struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
#else
static inline void __init msm_dsi_register(void)
{
@@ -319,7 +314,7 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
return false;
}
-static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
+static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
{
return NULL;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config
2022-07-11 10:04 ` [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config Dmitry Baryshkov
@ 2022-07-16 0:22 ` Abhinav Kumar
2022-07-16 10:30 ` Marijn Suijten
1 sibling, 0 replies; 7+ messages in thread
From: Abhinav Kumar @ 2022-07-16 0:22 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 7/11/2022 3:04 AM, Dmitry Baryshkov wrote:
> There is no need to use the struct msm_display_dsc_config wrapper inside
> the dpu driver, use the struct drm_dsc_config directly to pass pps data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This is a nice cleanup!
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 +++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 74 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> 5 files changed, 54 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index c682d4e02d1b..07b22b7df2e9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -162,7 +162,7 @@ enum dpu_enc_rc_states {
> * @vsync_event_work: worker to handle vsync event for autorefresh
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> - * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> + * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -208,7 +208,7 @@ struct dpu_encoder_virt {
> bool wide_bus_en;
>
> /* DSC configuration */
> - struct msm_display_dsc_config *dsc;
> + struct drm_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -1791,12 +1791,12 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> }
>
> static u32
> -dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> +dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
> u32 enc_ip_width)
> {
> int ssm_delay, total_pixels, soft_slice_per_enc;
>
> - soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> + soft_slice_per_enc = enc_ip_width / dsc->slice_width;
>
> /*
> * minimum number of initial line pixels is a sum of:
> @@ -1808,16 +1808,16 @@ dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> * 5. 6 additional pixels as the output of the rate buffer is
> * 48 bits wide
> */
> - ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> - total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
> if (soft_slice_per_enc > 1)
> total_pixels += (ssm_delay * 3);
> - return DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> + return DIV_ROUND_UP(total_pixels, dsc->slice_width);
> }
>
> static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> struct dpu_hw_pingpong *hw_pp,
> - struct msm_display_dsc_config *dsc,
> + struct drm_dsc_config *dsc,
> u32 common_mode,
> u32 initial_lines)
> {
> @@ -1835,7 +1835,7 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> }
>
> static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> - struct msm_display_dsc_config *dsc)
> + struct drm_dsc_config *dsc)
> {
> /* coding only for 2LM, 2enc, 1 dsc config */
> struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> @@ -1858,14 +1858,15 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> }
> }
>
> - pic_width = dsc->drm->pic_width;
> + dsc_common_mode = 0;
> + pic_width = dsc->pic_width;
>
> dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> if (enc_master->intf_mode == INTF_MODE_VIDEO)
> dsc_common_mode |= DSC_MODE_VIDEO;
>
> - this_frame_slices = pic_width / dsc->drm->slice_width;
> - intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> + this_frame_slices = pic_width / dsc->slice_width;
> + intf_ip_w = this_frame_slices * dsc->slice_width;
>
> /*
> * dsc merge case: when using 2 encoders for the same stream,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index d4d1ecd416e3..9e7236ef34e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -36,7 +36,7 @@ struct msm_display_info {
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_cmd_mode;
> bool is_te_using_watchdog_timer;
> - struct msm_display_dsc_config *dsc;
> + struct drm_dsc_config *dsc;
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> index 184a1b27b13d..20a033cd323d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -37,7 +37,7 @@ static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
> }
>
> static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc,
> + struct drm_dsc_config *dsc,
> u32 mode,
> u32 initial_lines)
> {
> @@ -52,89 +52,89 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
> if (is_cmd_mode)
> initial_lines += 1;
>
> - slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + slice_last_group_size = 3 - (dsc->slice_width % 3);
> data = (initial_lines << 20);
> data |= ((slice_last_group_size - 1) << 18);
> /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
> - data |= dsc->drm->bits_per_pixel << 12;
> - lsb = dsc->drm->bits_per_pixel % 4;
> - bpp = dsc->drm->bits_per_pixel / 4;
> + data |= dsc->bits_per_pixel << 12;
> + lsb = dsc->bits_per_pixel % 4;
> + bpp = dsc->bits_per_pixel / 4;
> bpp *= 4;
> bpp <<= 4;
> bpp |= lsb;
>
> data |= bpp << 8;
> - data |= (dsc->drm->block_pred_enable << 7);
> - data |= (dsc->drm->line_buf_depth << 3);
> - data |= (dsc->drm->simple_422 << 2);
> - data |= (dsc->drm->convert_rgb << 1);
> - data |= dsc->drm->bits_per_component;
> + data |= (dsc->block_pred_enable << 7);
> + data |= (dsc->line_buf_depth << 3);
> + data |= (dsc->simple_422 << 2);
> + data |= (dsc->convert_rgb << 1);
> + data |= dsc->bits_per_component;
>
> DPU_REG_WRITE(c, DSC_ENC, data);
>
> - data = dsc->drm->pic_width << 16;
> - data |= dsc->drm->pic_height;
> + data = dsc->pic_width << 16;
> + data |= dsc->pic_height;
> DPU_REG_WRITE(c, DSC_PICTURE, data);
>
> - data = dsc->drm->slice_width << 16;
> - data |= dsc->drm->slice_height;
> + data = dsc->slice_width << 16;
> + data |= dsc->slice_height;
> DPU_REG_WRITE(c, DSC_SLICE, data);
>
> - data = dsc->drm->slice_chunk_size << 16;
> + data = dsc->slice_chunk_size << 16;
> DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
>
> - data = dsc->drm->initial_dec_delay << 16;
> - data |= dsc->drm->initial_xmit_delay;
> + data = dsc->initial_dec_delay << 16;
> + data |= dsc->initial_xmit_delay;
> DPU_REG_WRITE(c, DSC_DELAY, data);
>
> - data = dsc->drm->initial_scale_value;
> + data = dsc->initial_scale_value;
> DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
>
> - data = dsc->drm->scale_decrement_interval;
> + data = dsc->scale_decrement_interval;
> DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
>
> - data = dsc->drm->scale_increment_interval;
> + data = dsc->scale_increment_interval;
> DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
>
> - data = dsc->drm->first_line_bpg_offset;
> + data = dsc->first_line_bpg_offset;
> DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
>
> - data = dsc->drm->nfl_bpg_offset << 16;
> - data |= dsc->drm->slice_bpg_offset;
> + data = dsc->nfl_bpg_offset << 16;
> + data |= dsc->slice_bpg_offset;
> DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
>
> - data = dsc->drm->initial_offset << 16;
> - data |= dsc->drm->final_offset;
> + data = dsc->initial_offset << 16;
> + data |= dsc->final_offset;
> DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
>
> - det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8);
> data = det_thresh_flatness << 10;
> - data |= dsc->drm->flatness_max_qp << 5;
> - data |= dsc->drm->flatness_min_qp;
> + data |= dsc->flatness_max_qp << 5;
> + data |= dsc->flatness_min_qp;
> DPU_REG_WRITE(c, DSC_FLATNESS, data);
>
> - data = dsc->drm->rc_model_size;
> + data = dsc->rc_model_size;
> DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
>
> - data = dsc->drm->rc_tgt_offset_low << 18;
> - data |= dsc->drm->rc_tgt_offset_high << 14;
> - data |= dsc->drm->rc_quant_incr_limit1 << 9;
> - data |= dsc->drm->rc_quant_incr_limit0 << 4;
> - data |= dsc->drm->rc_edge_factor;
> + data = dsc->rc_tgt_offset_low << 18;
> + data |= dsc->rc_tgt_offset_high << 14;
> + data |= dsc->rc_quant_incr_limit1 << 9;
> + data |= dsc->rc_quant_incr_limit0 << 4;
> + data |= dsc->rc_edge_factor;
> DPU_REG_WRITE(c, DSC_RC, data);
> }
>
> static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc)
> + struct drm_dsc_config *dsc)
> {
> - struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
> + struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params;
> struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> u32 off;
> int i;
>
> off = DSC_RC_BUF_THRESH;
> for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
> - DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
> + DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]);
> off += 4;
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> index 45e4118f1fa2..c0b77fe1a696 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> @@ -31,7 +31,7 @@ struct dpu_hw_dsc_ops {
> * @initial_lines: amount of initial lines to be used
> */
> void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc,
> + struct drm_dsc_config *dsc,
> u32 mode,
> u32 initial_lines);
>
> @@ -41,7 +41,7 @@ struct dpu_hw_dsc_ops {
> * @dsc: panel dsc parameters
> */
> void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc);
> + struct drm_dsc_config *dsc);
> };
>
> struct dpu_hw_dsc {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 75ed2b36e1b3..8016d0a3aade 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -585,7 +585,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> info.h_tile_instance[info.num_of_h_tiles++] = i;
> info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
>
> - info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i])->drm;
>
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Freedreno] [PATCH 2/2] drm/msm/dsi: use drm_dsc_config instead of msm_display_dsc_config
2022-07-11 10:04 ` [PATCH 2/2] drm/msm/dsi: " Dmitry Baryshkov
@ 2022-07-16 0:28 ` Abhinav Kumar
2022-07-16 10:31 ` Marijn Suijten
1 sibling, 0 replies; 7+ messages in thread
From: Abhinav Kumar @ 2022-07-16 0:28 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: David Airlie, linux-arm-msm, dri-devel, Bjorn Andersson,
Daniel Vetter, Stephen Boyd, freedreno
On 7/11/2022 3:04 AM, Dmitry Baryshkov wrote:
> There is no need to use the struct msm_display_dsc_config wrapper inside
> the dsi driver, use the struct drm_dsc_config directly to pass pps data.
>
This change is good but needs to be rebased? See below ....
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/dsi/dsi.c | 2 +-
> drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
> drivers/gpu/drm/msm/dsi/dsi_host.c | 157 +++++++++++-------------
> drivers/gpu/drm/msm/msm_drv.h | 9 +-
> 5 files changed, 79 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 8016d0a3aade..75ed2b36e1b3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -585,7 +585,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> info.h_tile_instance[info.num_of_h_tiles++] = i;
> info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
>
> - info.dsc = msm_dsi_get_dsc_config(priv->dsi[i])->drm;
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
>
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 1625328fa430..8f1ed31b048a 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -21,7 +21,7 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> -struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> {
> return msm_dsi_host_get_dsc_config(msm_dsi->host);
> }
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 580a1e6358bf..df46cdda1b43 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -154,7 +154,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> -struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
> +struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index a34078497af1..15e108be1901 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -33,7 +33,7 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> -static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +static int dsi_populate_dsc_params(struct drm_dsc_config *dsc);
>
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> @@ -161,7 +161,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> - struct msm_display_dsc_config *dsc;
> + struct drm_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -916,7 +916,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
>
> static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
> {
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> + struct drm_dsc_config *dsc = msm_host->dsc;
> u32 reg, intf_width, reg_ctrl, reg_ctrl2;
> u32 slice_per_intf, total_bytes_per_intf;
> u32 pkt_per_line;
> @@ -927,24 +927,24 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
> * compress mode registers
> */
> intf_width = hdisplay;
> - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
>
> /* If slice_per_pkt is greater than slice_per_intf
> * then default to 1. This can happen during partial
> * update.
> */
> - if (slice_per_intf > dsc->drm->slice_count)
> - dsc->drm->slice_count = 1;
> + if (slice_per_intf > dsc->slice_count)
> + dsc->slice_count = 1;
>
> - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> - bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * dsc->drm->bits_per_pixel, 8);
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8);
>
> - dsc->drm->slice_chunk_size = bytes_in_slice;
> + dsc->slice_chunk_size = bytes_in_slice;
>
> total_bytes_per_intf = bytes_in_slice * slice_per_intf;
>
> eol_byte_num = total_bytes_per_intf % 3;
> - pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> + pkt_per_line = slice_per_intf / dsc->slice_count;
>
> if (is_cmd_mode) /* packet data type */
> reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
> @@ -1009,7 +1009,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> }
>
> if (msm_host->dsc) {
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> + struct drm_dsc_config *dsc = msm_host->dsc;
>
> /* update dsc params with timing params */
> if (!dsc || !mode->hdisplay || !mode->vdisplay) {
> @@ -1018,9 +1018,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> return;
> }
>
> - dsc->drm->pic_width = mode->hdisplay;
> - dsc->drm->pic_height = mode->vdisplay;
> - DBG("Mode %dx%d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> + dsc->pic_width = mode->hdisplay;
> + dsc->pic_height = mode->vdisplay;
> + DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
>
> /* we do the calculations for dsc parameters here so that
> * panel can use these parameters
> @@ -1841,7 +1841,7 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> };
>
> -static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> {
> int mux_words_size;
> int groups_per_line, groups_total;
> @@ -1854,98 +1854,98 @@ static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> int final_value, final_scale;
> int i;
>
> - dsc->drm->rc_model_size = 8192;
> - dsc->drm->first_line_bpg_offset = 12;
> - dsc->drm->rc_edge_factor = 6;
> - dsc->drm->rc_tgt_offset_high = 3;
> - dsc->drm->rc_tgt_offset_low = 3;
> - dsc->drm->simple_422 = 0;
> - dsc->drm->convert_rgb = 1;
> - dsc->drm->vbr_enable = 0;
> + dsc->rc_model_size = 8192;
> + dsc->first_line_bpg_offset = 12;
> + dsc->rc_edge_factor = 6;
> + dsc->rc_tgt_offset_high = 3;
> + dsc->rc_tgt_offset_low = 3;
> + dsc->simple_422 = 0;
> + dsc->convert_rgb = 1;
> + dsc->vbr_enable = 0;
>
> /* handle only bpp = bpc = 8 */
> for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> - dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> + dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
>
> for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> - dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> - dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> - dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + dsc->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> }
>
> - dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> - if (dsc->drm->bits_per_pixel != 8)
> - dsc->drm->initial_offset = 2048; /* bpp = 12 */
> + dsc->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->bits_per_pixel != 8)
> + dsc->initial_offset = 2048; /* bpp = 12 */
>
> mux_words_size = 48; /* bpc == 8/10 */
> - if (dsc->drm->bits_per_component == 12)
> + if (dsc->bits_per_component == 12)
> mux_words_size = 64;
>
> - dsc->drm->initial_xmit_delay = 512;
> - dsc->drm->initial_scale_value = 32;
> - dsc->drm->first_line_bpg_offset = 12;
> - dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> + dsc->initial_xmit_delay = 512;
> + dsc->initial_scale_value = 32;
> + dsc->first_line_bpg_offset = 12;
> + dsc->line_buf_depth = dsc->bits_per_component + 1;
>
> /* bpc 8 */
> - dsc->drm->flatness_min_qp = 3;
> - dsc->drm->flatness_max_qp = 12;
> - dsc->drm->rc_quant_incr_limit0 = 11;
> - dsc->drm->rc_quant_incr_limit1 = 11;
> - dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> + dsc->flatness_min_qp = 3;
> + dsc->flatness_max_qp = 12;
> + dsc->rc_quant_incr_limit0 = 11;
> + dsc->rc_quant_incr_limit1 = 11;
> + dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
>
> /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> * params are calculated
> */
> - groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> - dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> - if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> - dsc->drm->slice_chunk_size++;
> + groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
> + dsc->slice_chunk_size = dsc->slice_width * dsc->bits_per_pixel / 8;
> + if ((dsc->slice_width * dsc->bits_per_pixel) % 8)
> + dsc->slice_chunk_size++;
>
> /* rbs-min */
> - min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> - dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> - groups_per_line * dsc->drm->first_line_bpg_offset;
> + min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset +
> + dsc->initial_xmit_delay * dsc->bits_per_pixel +
> + groups_per_line * dsc->first_line_bpg_offset;
>
> - hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel);
>
> - dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> + dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
>
> - dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> - (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> + dsc->initial_scale_value = 8 * dsc->rc_model_size /
> + (dsc->rc_model_size - dsc->initial_offset);
>
> - slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> + slice_bits = 8 * dsc->slice_chunk_size * dsc->slice_height;
>
> - groups_total = groups_per_line * dsc->drm->slice_height;
> + groups_total = groups_per_line * dsc->slice_height;
>
> - data = dsc->drm->first_line_bpg_offset * 2048;
> + data = dsc->first_line_bpg_offset * 2048;
>
> - dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> + dsc->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->slice_height - 1));
>
> - pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->bits_per_component + 4) - 2);
>
> num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
>
> - data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> - dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> + data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits);
> + dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
>
> /* bpp * 16 + 0.5 */
> - data = dsc->drm->bits_per_pixel * 16;
> + data = dsc->bits_per_pixel * 16;
> data *= 2;
> data++;
> data /= 2;
> target_bpp_x16 = data;
>
> - data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> - final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> - dsc->drm->final_offset = final_value;
> + data = (dsc->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->rc_model_size - data + num_extra_mux_bits;
> + dsc->final_offset = final_value;
>
> - final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> + final_scale = 8 * dsc->rc_model_size / (dsc->rc_model_size - final_value);
>
> - data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> - dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> + data = (final_scale - 9) * (dsc->nfl_bpg_offset + dsc->slice_bpg_offset);
> + dsc->scale_increment_interval = (2048 * dsc->final_offset) / data;
>
> - dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> + dsc->scale_decrement_interval = groups_per_line / (dsc->initial_scale_value - 8);
>
> return 0;
> }
> @@ -2165,17 +2165,8 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> msm_host->dev = dev;
> panel = msm_dsi_host_get_panel(&msm_host->base);
>
> - if (!IS_ERR(panel) && panel->dsc) {
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> -
> - if (!dsc) {
> - dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> - if (!dsc)
> - return -ENOMEM;
> - dsc->drm = panel->dsc;
With https://patchwork.freedesktop.org/patch/493309/, you need to fetch
the dsc_config from struct mipi_dsi_device.
So i guess, we just need to decide which one goes first ?
> - msm_host->dsc = dsc;
> - }
> - }
> + if (!IS_ERR(panel) && panel->dsc)
> + msm_host->dsc = panel->dsc;
>
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> @@ -2659,22 +2650,22 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
> const struct drm_display_mode *mode)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> + struct drm_dsc_config *dsc = msm_host->dsc;
> int pic_width = mode->hdisplay;
> int pic_height = mode->vdisplay;
>
> if (!msm_host->dsc)
> return MODE_OK;
>
> - if (pic_width % dsc->drm->slice_width) {
> + if (pic_width % dsc->slice_width) {
> pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
> - pic_width, dsc->drm->slice_width);
> + pic_width, dsc->slice_width);
> return MODE_H_ILLEGAL;
> }
>
> - if (pic_height % dsc->drm->slice_height) {
> + if (pic_height % dsc->slice_height) {
> pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
> - pic_height, dsc->drm->slice_height);
> + pic_height, dsc->slice_height);
> return MODE_V_ILLEGAL;
> }
>
> @@ -2771,7 +2762,7 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
>
> -struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index ae49e56ac026..8075a0e010a5 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -96,11 +96,6 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> -/* DSC config */
> -struct msm_display_dsc_config {
> - struct drm_dsc_config *drm;
> -};
> -
> struct msm_drm_private {
>
> struct drm_device *dev;
> @@ -289,7 +284,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> -struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> +struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -319,7 +314,7 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> return false;
> }
>
> -static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> {
> return NULL;
> }
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config
2022-07-11 10:04 ` [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config Dmitry Baryshkov
2022-07-16 0:22 ` Abhinav Kumar
@ 2022-07-16 10:30 ` Marijn Suijten
1 sibling, 0 replies; 7+ messages in thread
From: Marijn Suijten @ 2022-07-16 10:30 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Abhinav Kumar, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On 2022-07-11 13:04:31, Dmitry Baryshkov wrote:
> There is no need to use the struct msm_display_dsc_config wrapper inside
> the dpu driver, use the struct drm_dsc_config directly to pass pps data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 +++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 74 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> 5 files changed, 54 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index c682d4e02d1b..07b22b7df2e9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -162,7 +162,7 @@ enum dpu_enc_rc_states {
> * @vsync_event_work: worker to handle vsync event for autorefresh
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> - * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> + * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -208,7 +208,7 @@ struct dpu_encoder_virt {
> bool wide_bus_en;
>
> /* DSC configuration */
> - struct msm_display_dsc_config *dsc;
> + struct drm_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -1791,12 +1791,12 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> }
>
> static u32
> -dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> +dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
> u32 enc_ip_width)
> {
> int ssm_delay, total_pixels, soft_slice_per_enc;
>
> - soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> + soft_slice_per_enc = enc_ip_width / dsc->slice_width;
>
> /*
> * minimum number of initial line pixels is a sum of:
> @@ -1808,16 +1808,16 @@ dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> * 5. 6 additional pixels as the output of the rate buffer is
> * 48 bits wide
> */
> - ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> - total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
> if (soft_slice_per_enc > 1)
> total_pixels += (ssm_delay * 3);
> - return DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> + return DIV_ROUND_UP(total_pixels, dsc->slice_width);
> }
>
> static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> struct dpu_hw_pingpong *hw_pp,
> - struct msm_display_dsc_config *dsc,
> + struct drm_dsc_config *dsc,
> u32 common_mode,
> u32 initial_lines)
> {
> @@ -1835,7 +1835,7 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> }
>
> static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> - struct msm_display_dsc_config *dsc)
> + struct drm_dsc_config *dsc)
> {
> /* coding only for 2LM, 2enc, 1 dsc config */
> struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> @@ -1858,14 +1858,15 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> }
> }
>
> - pic_width = dsc->drm->pic_width;
> + dsc_common_mode = 0;
> + pic_width = dsc->pic_width;
>
> dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> if (enc_master->intf_mode == INTF_MODE_VIDEO)
> dsc_common_mode |= DSC_MODE_VIDEO;
>
> - this_frame_slices = pic_width / dsc->drm->slice_width;
> - intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> + this_frame_slices = pic_width / dsc->slice_width;
> + intf_ip_w = this_frame_slices * dsc->slice_width;
>
> /*
> * dsc merge case: when using 2 encoders for the same stream,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index d4d1ecd416e3..9e7236ef34e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -36,7 +36,7 @@ struct msm_display_info {
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_cmd_mode;
> bool is_te_using_watchdog_timer;
> - struct msm_display_dsc_config *dsc;
> + struct drm_dsc_config *dsc;
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> index 184a1b27b13d..20a033cd323d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -37,7 +37,7 @@ static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
> }
>
> static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc,
> + struct drm_dsc_config *dsc,
> u32 mode,
> u32 initial_lines)
> {
> @@ -52,89 +52,89 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
> if (is_cmd_mode)
> initial_lines += 1;
>
> - slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + slice_last_group_size = 3 - (dsc->slice_width % 3);
> data = (initial_lines << 20);
> data |= ((slice_last_group_size - 1) << 18);
> /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
> - data |= dsc->drm->bits_per_pixel << 12;
> - lsb = dsc->drm->bits_per_pixel % 4;
> - bpp = dsc->drm->bits_per_pixel / 4;
> + data |= dsc->bits_per_pixel << 12;
> + lsb = dsc->bits_per_pixel % 4;
> + bpp = dsc->bits_per_pixel / 4;
> bpp *= 4;
> bpp <<= 4;
> bpp |= lsb;
>
> data |= bpp << 8;
> - data |= (dsc->drm->block_pred_enable << 7);
> - data |= (dsc->drm->line_buf_depth << 3);
> - data |= (dsc->drm->simple_422 << 2);
> - data |= (dsc->drm->convert_rgb << 1);
> - data |= dsc->drm->bits_per_component;
> + data |= (dsc->block_pred_enable << 7);
> + data |= (dsc->line_buf_depth << 3);
> + data |= (dsc->simple_422 << 2);
> + data |= (dsc->convert_rgb << 1);
> + data |= dsc->bits_per_component;
>
> DPU_REG_WRITE(c, DSC_ENC, data);
>
> - data = dsc->drm->pic_width << 16;
> - data |= dsc->drm->pic_height;
> + data = dsc->pic_width << 16;
> + data |= dsc->pic_height;
> DPU_REG_WRITE(c, DSC_PICTURE, data);
>
> - data = dsc->drm->slice_width << 16;
> - data |= dsc->drm->slice_height;
> + data = dsc->slice_width << 16;
> + data |= dsc->slice_height;
> DPU_REG_WRITE(c, DSC_SLICE, data);
>
> - data = dsc->drm->slice_chunk_size << 16;
> + data = dsc->slice_chunk_size << 16;
> DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
>
> - data = dsc->drm->initial_dec_delay << 16;
> - data |= dsc->drm->initial_xmit_delay;
> + data = dsc->initial_dec_delay << 16;
> + data |= dsc->initial_xmit_delay;
> DPU_REG_WRITE(c, DSC_DELAY, data);
>
> - data = dsc->drm->initial_scale_value;
> + data = dsc->initial_scale_value;
> DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
>
> - data = dsc->drm->scale_decrement_interval;
> + data = dsc->scale_decrement_interval;
> DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
>
> - data = dsc->drm->scale_increment_interval;
> + data = dsc->scale_increment_interval;
> DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
>
> - data = dsc->drm->first_line_bpg_offset;
> + data = dsc->first_line_bpg_offset;
> DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
>
> - data = dsc->drm->nfl_bpg_offset << 16;
> - data |= dsc->drm->slice_bpg_offset;
> + data = dsc->nfl_bpg_offset << 16;
> + data |= dsc->slice_bpg_offset;
> DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
>
> - data = dsc->drm->initial_offset << 16;
> - data |= dsc->drm->final_offset;
> + data = dsc->initial_offset << 16;
> + data |= dsc->final_offset;
> DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
>
> - det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8);
> data = det_thresh_flatness << 10;
> - data |= dsc->drm->flatness_max_qp << 5;
> - data |= dsc->drm->flatness_min_qp;
> + data |= dsc->flatness_max_qp << 5;
> + data |= dsc->flatness_min_qp;
> DPU_REG_WRITE(c, DSC_FLATNESS, data);
>
> - data = dsc->drm->rc_model_size;
> + data = dsc->rc_model_size;
> DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
>
> - data = dsc->drm->rc_tgt_offset_low << 18;
> - data |= dsc->drm->rc_tgt_offset_high << 14;
> - data |= dsc->drm->rc_quant_incr_limit1 << 9;
> - data |= dsc->drm->rc_quant_incr_limit0 << 4;
> - data |= dsc->drm->rc_edge_factor;
> + data = dsc->rc_tgt_offset_low << 18;
> + data |= dsc->rc_tgt_offset_high << 14;
> + data |= dsc->rc_quant_incr_limit1 << 9;
> + data |= dsc->rc_quant_incr_limit0 << 4;
> + data |= dsc->rc_edge_factor;
> DPU_REG_WRITE(c, DSC_RC, data);
> }
>
> static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc)
> + struct drm_dsc_config *dsc)
> {
> - struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
> + struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params;
> struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> u32 off;
> int i;
>
> off = DSC_RC_BUF_THRESH;
> for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
> - DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
> + DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]);
> off += 4;
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> index 45e4118f1fa2..c0b77fe1a696 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> @@ -31,7 +31,7 @@ struct dpu_hw_dsc_ops {
> * @initial_lines: amount of initial lines to be used
> */
> void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc,
> + struct drm_dsc_config *dsc,
> u32 mode,
> u32 initial_lines);
>
> @@ -41,7 +41,7 @@ struct dpu_hw_dsc_ops {
> * @dsc: panel dsc parameters
> */
> void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
> - struct msm_display_dsc_config *dsc);
> + struct drm_dsc_config *dsc);
> };
>
> struct dpu_hw_dsc {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 75ed2b36e1b3..8016d0a3aade 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -585,7 +585,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> info.h_tile_instance[info.num_of_h_tiles++] = i;
> info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
>
> - info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i])->drm;
>
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> --
> 2.35.1
>
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/msm/dsi: use drm_dsc_config instead of msm_display_dsc_config
2022-07-11 10:04 ` [PATCH 2/2] drm/msm/dsi: " Dmitry Baryshkov
2022-07-16 0:28 ` [Freedreno] " Abhinav Kumar
@ 2022-07-16 10:31 ` Marijn Suijten
1 sibling, 0 replies; 7+ messages in thread
From: Marijn Suijten @ 2022-07-16 10:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Abhinav Kumar, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On 2022-07-11 13:04:32, Dmitry Baryshkov wrote:
> There is no need to use the struct msm_display_dsc_config wrapper inside
> the dsi driver, use the struct drm_dsc_config directly to pass pps data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/dsi/dsi.c | 2 +-
> drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
> drivers/gpu/drm/msm/dsi/dsi_host.c | 157 +++++++++++-------------
> drivers/gpu/drm/msm/msm_drv.h | 9 +-
> 5 files changed, 79 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 8016d0a3aade..75ed2b36e1b3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -585,7 +585,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> info.h_tile_instance[info.num_of_h_tiles++] = i;
> info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
>
> - info.dsc = msm_dsi_get_dsc_config(priv->dsi[i])->drm;
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
>
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 1625328fa430..8f1ed31b048a 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -21,7 +21,7 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> -struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> {
> return msm_dsi_host_get_dsc_config(msm_dsi->host);
> }
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 580a1e6358bf..df46cdda1b43 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -154,7 +154,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> -struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
> +struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index a34078497af1..15e108be1901 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -33,7 +33,7 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> -static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +static int dsi_populate_dsc_params(struct drm_dsc_config *dsc);
>
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> @@ -161,7 +161,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> - struct msm_display_dsc_config *dsc;
> + struct drm_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -916,7 +916,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
>
> static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
> {
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> + struct drm_dsc_config *dsc = msm_host->dsc;
> u32 reg, intf_width, reg_ctrl, reg_ctrl2;
> u32 slice_per_intf, total_bytes_per_intf;
> u32 pkt_per_line;
> @@ -927,24 +927,24 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
> * compress mode registers
> */
> intf_width = hdisplay;
> - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
>
> /* If slice_per_pkt is greater than slice_per_intf
> * then default to 1. This can happen during partial
> * update.
> */
> - if (slice_per_intf > dsc->drm->slice_count)
> - dsc->drm->slice_count = 1;
> + if (slice_per_intf > dsc->slice_count)
> + dsc->slice_count = 1;
>
> - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> - bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * dsc->drm->bits_per_pixel, 8);
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8);
>
> - dsc->drm->slice_chunk_size = bytes_in_slice;
> + dsc->slice_chunk_size = bytes_in_slice;
>
> total_bytes_per_intf = bytes_in_slice * slice_per_intf;
>
> eol_byte_num = total_bytes_per_intf % 3;
> - pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> + pkt_per_line = slice_per_intf / dsc->slice_count;
>
> if (is_cmd_mode) /* packet data type */
> reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
> @@ -1009,7 +1009,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> }
>
> if (msm_host->dsc) {
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> + struct drm_dsc_config *dsc = msm_host->dsc;
>
> /* update dsc params with timing params */
> if (!dsc || !mode->hdisplay || !mode->vdisplay) {
> @@ -1018,9 +1018,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> return;
> }
>
> - dsc->drm->pic_width = mode->hdisplay;
> - dsc->drm->pic_height = mode->vdisplay;
> - DBG("Mode %dx%d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> + dsc->pic_width = mode->hdisplay;
> + dsc->pic_height = mode->vdisplay;
> + DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
>
> /* we do the calculations for dsc parameters here so that
> * panel can use these parameters
> @@ -1841,7 +1841,7 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> };
>
> -static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> {
> int mux_words_size;
> int groups_per_line, groups_total;
> @@ -1854,98 +1854,98 @@ static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> int final_value, final_scale;
> int i;
>
> - dsc->drm->rc_model_size = 8192;
> - dsc->drm->first_line_bpg_offset = 12;
> - dsc->drm->rc_edge_factor = 6;
> - dsc->drm->rc_tgt_offset_high = 3;
> - dsc->drm->rc_tgt_offset_low = 3;
> - dsc->drm->simple_422 = 0;
> - dsc->drm->convert_rgb = 1;
> - dsc->drm->vbr_enable = 0;
> + dsc->rc_model_size = 8192;
> + dsc->first_line_bpg_offset = 12;
> + dsc->rc_edge_factor = 6;
> + dsc->rc_tgt_offset_high = 3;
> + dsc->rc_tgt_offset_low = 3;
> + dsc->simple_422 = 0;
> + dsc->convert_rgb = 1;
> + dsc->vbr_enable = 0;
>
> /* handle only bpp = bpc = 8 */
> for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> - dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> + dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
>
> for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> - dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> - dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> - dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + dsc->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> }
>
> - dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> - if (dsc->drm->bits_per_pixel != 8)
> - dsc->drm->initial_offset = 2048; /* bpp = 12 */
> + dsc->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->bits_per_pixel != 8)
> + dsc->initial_offset = 2048; /* bpp = 12 */
>
> mux_words_size = 48; /* bpc == 8/10 */
> - if (dsc->drm->bits_per_component == 12)
> + if (dsc->bits_per_component == 12)
> mux_words_size = 64;
>
> - dsc->drm->initial_xmit_delay = 512;
> - dsc->drm->initial_scale_value = 32;
> - dsc->drm->first_line_bpg_offset = 12;
> - dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> + dsc->initial_xmit_delay = 512;
> + dsc->initial_scale_value = 32;
> + dsc->first_line_bpg_offset = 12;
> + dsc->line_buf_depth = dsc->bits_per_component + 1;
>
> /* bpc 8 */
> - dsc->drm->flatness_min_qp = 3;
> - dsc->drm->flatness_max_qp = 12;
> - dsc->drm->rc_quant_incr_limit0 = 11;
> - dsc->drm->rc_quant_incr_limit1 = 11;
> - dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> + dsc->flatness_min_qp = 3;
> + dsc->flatness_max_qp = 12;
> + dsc->rc_quant_incr_limit0 = 11;
> + dsc->rc_quant_incr_limit1 = 11;
> + dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
>
> /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> * params are calculated
> */
> - groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> - dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> - if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> - dsc->drm->slice_chunk_size++;
> + groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
> + dsc->slice_chunk_size = dsc->slice_width * dsc->bits_per_pixel / 8;
> + if ((dsc->slice_width * dsc->bits_per_pixel) % 8)
> + dsc->slice_chunk_size++;
>
> /* rbs-min */
> - min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> - dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> - groups_per_line * dsc->drm->first_line_bpg_offset;
> + min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset +
> + dsc->initial_xmit_delay * dsc->bits_per_pixel +
> + groups_per_line * dsc->first_line_bpg_offset;
>
> - hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel);
>
> - dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> + dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
>
> - dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> - (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> + dsc->initial_scale_value = 8 * dsc->rc_model_size /
> + (dsc->rc_model_size - dsc->initial_offset);
>
> - slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> + slice_bits = 8 * dsc->slice_chunk_size * dsc->slice_height;
>
> - groups_total = groups_per_line * dsc->drm->slice_height;
> + groups_total = groups_per_line * dsc->slice_height;
>
> - data = dsc->drm->first_line_bpg_offset * 2048;
> + data = dsc->first_line_bpg_offset * 2048;
>
> - dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> + dsc->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->slice_height - 1));
>
> - pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->bits_per_component + 4) - 2);
>
> num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
>
> - data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> - dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> + data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits);
> + dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
>
> /* bpp * 16 + 0.5 */
> - data = dsc->drm->bits_per_pixel * 16;
> + data = dsc->bits_per_pixel * 16;
> data *= 2;
> data++;
> data /= 2;
> target_bpp_x16 = data;
>
> - data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> - final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> - dsc->drm->final_offset = final_value;
> + data = (dsc->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->rc_model_size - data + num_extra_mux_bits;
> + dsc->final_offset = final_value;
>
> - final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> + final_scale = 8 * dsc->rc_model_size / (dsc->rc_model_size - final_value);
>
> - data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> - dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> + data = (final_scale - 9) * (dsc->nfl_bpg_offset + dsc->slice_bpg_offset);
> + dsc->scale_increment_interval = (2048 * dsc->final_offset) / data;
>
> - dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> + dsc->scale_decrement_interval = groups_per_line / (dsc->initial_scale_value - 8);
>
> return 0;
> }
> @@ -2165,17 +2165,8 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> msm_host->dev = dev;
> panel = msm_dsi_host_get_panel(&msm_host->base);
>
> - if (!IS_ERR(panel) && panel->dsc) {
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> -
> - if (!dsc) {
> - dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> - if (!dsc)
> - return -ENOMEM;
> - dsc->drm = panel->dsc;
> - msm_host->dsc = dsc;
> - }
> - }
> + if (!IS_ERR(panel) && panel->dsc)
> + msm_host->dsc = panel->dsc;
>
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> @@ -2659,22 +2650,22 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
> const struct drm_display_mode *mode)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> - struct msm_display_dsc_config *dsc = msm_host->dsc;
> + struct drm_dsc_config *dsc = msm_host->dsc;
> int pic_width = mode->hdisplay;
> int pic_height = mode->vdisplay;
>
> if (!msm_host->dsc)
> return MODE_OK;
>
> - if (pic_width % dsc->drm->slice_width) {
> + if (pic_width % dsc->slice_width) {
> pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
> - pic_width, dsc->drm->slice_width);
> + pic_width, dsc->slice_width);
> return MODE_H_ILLEGAL;
> }
>
> - if (pic_height % dsc->drm->slice_height) {
> + if (pic_height % dsc->slice_height) {
> pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
> - pic_height, dsc->drm->slice_height);
> + pic_height, dsc->slice_height);
> return MODE_V_ILLEGAL;
> }
>
> @@ -2771,7 +2762,7 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
>
> -struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index ae49e56ac026..8075a0e010a5 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -96,11 +96,6 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> -/* DSC config */
> -struct msm_display_dsc_config {
> - struct drm_dsc_config *drm;
> -};
> -
> struct msm_drm_private {
>
> struct drm_device *dev;
> @@ -289,7 +284,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> -struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> +struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -319,7 +314,7 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> return false;
> }
>
> -static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> {
> return NULL;
> }
> --
> 2.35.1
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-07-16 10:31 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-07-11 10:04 [PATCH 0/2] drm/msm: remove struct msm_display_dsc_config Dmitry Baryshkov
2022-07-11 10:04 ` [PATCH 1/2] drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_config Dmitry Baryshkov
2022-07-16 0:22 ` Abhinav Kumar
2022-07-16 10:30 ` Marijn Suijten
2022-07-11 10:04 ` [PATCH 2/2] drm/msm/dsi: " Dmitry Baryshkov
2022-07-16 0:28 ` [Freedreno] " Abhinav Kumar
2022-07-16 10:31 ` Marijn Suijten
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