[PATCH RFC 0/4] Support for Adreno X1-85 Speedbin along with new OPP levels

[PATCH RFC 0/4] Support for Adreno X1-85 Speedbin along with new OPP levels

[Akhil P Oommen]

This series adds gpu speedbin support for Adreno X1-85 GPU along with
additional OPP levels. Because the higher OPPs require GPU ACD feature,
this series has dependency on the GPU ACD support series [1]. Also,
there is dependency on dimtry's series which fixes dword alignment in
nvmem driver [2]. We need a small fix up on top of that and that is
being discussed there. Hence, the RFC tag.

An interesting bit here is the non-contigous "hi" bit for speedbin fuse.
Otherwise, it is business as usual.

The device tree change has a dependency on the driver changes. So the
driver changes should be picked up first.

[1] https://lore.kernel.org/lkml/20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com/
[2] https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/

-Akhil

---
Akhil P Oommen (4):
      drm/msm/adreno: Add speedbin support for X1-85
      dt-bindings: power: qcom,rpmpd: add Turbo L5 corner
      dt-bindings: nvmem: qfprom: Add X1E80100 compatible
      arm64: dts: qcom: x1e80100: Update GPU OPP table

 .../devicetree/bindings/nvmem/qcom,qfprom.yaml     |  1 +
 arch/arm64/boot/dts/qcom/x1e80100.dtsi             | 47 ++++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c          |  5 +++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c            | 15 ++++++-
 include/dt-bindings/power/qcom-rpmpd.h             |  1 +
 5 files changed, 68 insertions(+), 1 deletion(-)
---
base-commit: 5fcdd8fcd55d1da6fdf8deb78355a5c23ce94d39
change-id: 20240807-x1e-speedbin-b4-a0c304d13983
prerequisite-message-id: 20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com
prerequisite-patch-id: 2ac56343518c3c16229262051f52e448564f2286
prerequisite-patch-id: 1c363fb7cd864279bd97ed50a02f05f72ca00a5d
prerequisite-patch-id: 059608aac5a0a1fa11ea93a8871820f054771301
prerequisite-patch-id: de12f1b879070aca3f42973b75ed04d4d835b244
prerequisite-patch-id: 421ea499b3e901030f66f697dc0a0b718d9db20e
prerequisite-patch-id: ca6d3a3c65bd17bbcd7785e4584941a438aafcb9
prerequisite-patch-id: 017b7ba9e9bfd70719b77bf741bf0afa7f20cee0
prerequisite-message-id: 20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org
prerequisite-patch-id: c1310808de89982d41261bab69c77be2e83a6339
prerequisite-patch-id: 34a5a771be148f71d66acd4417493cc752e6d3a6
prerequisite-patch-id: 30ac1f33b3dc8979f28fdfd6303595fcfce56b84
prerequisite-patch-id: 2238546441608d9f5755b4ebc1d5ea6090c6c3bb
prerequisite-patch-id: 7a260ae7850d966e8fecd3ebc5114ac157d23c87

Best regards,
-- 
Akhil P Oommen <quic_akhilpo@quicinc.com>

[PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85

[Akhil P Oommen]

Adreno X1-85 has an additional bit which is at a non-contiguous
location in qfprom. Add support for this new "hi" bit along with
the speedbin mappings.
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  5 +++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 15 ++++++++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
 			.gmu_cgc_mode = 0x00020202,
 		},
 		.address_space_size = SZ_256G,
+		.speedbins = ADRENO_SPEEDBINS(
+			{ 0,   0 },
+			{ 263, 1 },
+			{ 315, 0 },
+		),
 		.preempt_record_size = 4192 * SZ_1K,
 	}, {
 		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
 
 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
 {
-	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+	u32 hi_bits = 0;
+	int ret;
+
+	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+	if (ret)
+		return ret;
+
+	/* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
+	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
+	if (ret != -ENOENT)
+		return ret;
+
+	*speedbin |= (hi_bits << 8);
+	return 0;
 }
 
 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,

-- 
2.45.2

[PATCH RFC 2/4] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner

[Akhil P Oommen]

Update the RPMH level definitions to include TURBO_L5 corner.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
 include/dt-bindings/power/qcom-rpmpd.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index df599bf462207267a412eac8e01634189a696a59..5bc4735fb3e6e06ec62a352e2d40503b01084fd8 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -240,6 +240,7 @@
 #define RPMH_REGULATOR_LEVEL_TURBO_L2		432
 #define RPMH_REGULATOR_LEVEL_TURBO_L3		448
 #define RPMH_REGULATOR_LEVEL_TURBO_L4		452
+#define RPMH_REGULATOR_LEVEL_TURBO_L5		456
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO 	464
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
 

-- 
2.45.2

[PATCH RFC 3/4] dt-bindings: nvmem: qfprom: Add X1E80100 compatible

[Akhil P Oommen]

Document compatible string for the QFPROM on X1E80100 platform.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 9755b31946bf9d4c1055a993145d06c274b61a37..25f07f93345af83015b2c2917993e460cfd6799e 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -47,6 +47,7 @@ properties:
           - qcom,sm8450-qfprom
           - qcom,sm8550-qfprom
           - qcom,sm8650-qfprom
+          - qcom,x1e80100-qfprom
       - const: qcom,qfprom
 
   reg:

-- 
2.45.2

[PATCH RFC 4/4] arm64: dts: qcom: x1e80100: Update GPU OPP table

[Akhil P Oommen]

Update GPU OPP table with new levels along with the speedbin
configurations.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 47 ++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 444723ab4f11d15cb7c0f9829ec8123b76e4ebeb..0a4f179ef2eb2de11485580d797457f823f3c528 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3325,6 +3325,9 @@ gpu: gpu@3d00000 {
 			qcom,gmu = <&gmu>;
 			#cooling-cells = <2>;
 
+			nvmem-cells = <&gpu_speed_bin>, <&gpu_speed_bin_hi>;
+			nvmem-cell-names = "speed_bin", "speed_bin_hi";
+
 			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
 			interconnect-names = "gfx-mem";
 
@@ -3337,11 +3340,28 @@ zap-shader {
 			gpu_opp_table: opp-table {
 				compatible = "operating-points-v2-adreno", "operating-points-v2";
 
+				opp-1500000000 {
+					opp-hz = /bits/ 64 <1500000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+					opp-peak-kBps = <16500000>;
+					qcom,opp-acd-level = <0xa82a5ffd>;
+					opp-supported-hw = <0x01>;
+				};
+
+				opp-1375000000 {
+					opp-hz = /bits/ 64 <1375000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+					opp-peak-kBps = <16500000>;
+					qcom,opp-acd-level = <0xa82a5ffd>;
+					opp-supported-hw = <0x01>;
+				};
+
 				opp-1250000000 {
 					opp-hz = /bits/ 64 <1250000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
 					opp-peak-kBps = <16500000>;
 					qcom,opp-acd-level = <0xa82a5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-1175000000 {
@@ -3349,6 +3369,7 @@ opp-1175000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
 					opp-peak-kBps = <14398438>;
 					qcom,opp-acd-level = <0xa82a5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-1100000000 {
@@ -3356,6 +3377,7 @@ opp-1100000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 					opp-peak-kBps = <14398438>;
 					qcom,opp-acd-level = <0xa82a5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-1000000000 {
@@ -3363,6 +3385,7 @@ opp-1000000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 					opp-peak-kBps = <14398438>;
 					qcom,opp-acd-level = <0xa82b5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-925000000 {
@@ -3370,6 +3393,7 @@ opp-925000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 					opp-peak-kBps = <14398438>;
 					qcom,opp-acd-level = <0xa82b5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-800000000 {
@@ -3377,6 +3401,7 @@ opp-800000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 					opp-peak-kBps = <12449219>;
 					qcom,opp-acd-level = <0xa82c5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-744000000 {
@@ -3384,6 +3409,7 @@ opp-744000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 					opp-peak-kBps = <10687500>;
 					qcom,opp-acd-level = <0x882e5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-687000000 {
@@ -3391,6 +3417,7 @@ opp-687000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 					opp-peak-kBps = <8171875>;
 					qcom,opp-acd-level = <0x882e5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-550000000 {
@@ -3398,6 +3425,7 @@ opp-550000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 					opp-peak-kBps = <6074219>;
 					qcom,opp-acd-level = <0xc0285ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-390000000 {
@@ -3405,6 +3433,7 @@ opp-390000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 					opp-peak-kBps = <3000000>;
 					qcom,opp-acd-level = <0xc0285ffd>;
+					opp-supported-hw = <0x03>;
 				};
 
 				opp-300000000 {
@@ -3412,6 +3441,7 @@ opp-300000000 {
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 					opp-peak-kBps = <2136719>;
 					qcom,opp-acd-level = <0xc02b5ffd>;
+					opp-supported-hw = <0x03>;
 				};
 			};
 		};
@@ -5992,6 +6022,23 @@ frame@1780d000 {
 			};
 		};
 
+		efuse@221c8000 {
+			compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
+			reg = <0 0x221c8000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpu_speed_bin: gpu_speed_bin@119 {
+				reg = <0x119 0x2>;
+				bits = <7 8>;
+			};
+
+			gpu_speed_bin_hi: gpu_speed_bin_hi@11b {
+				reg = <0x11b 0x1>;
+				bits = <7 1>;
+			};
+		};
+
 		pmu@24091000 {
 			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0 0x24091000 0 0x1000>;

-- 
2.45.2

Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85

[Konrad Dybcio]

On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
> Adreno X1-85 has an additional bit which is at a non-contiguous
> location in qfprom. Add support for this new "hi" bit along with
> the speedbin mappings.
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  5 +++++
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 15 ++++++++++++++-
>  2 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
>  			.gmu_cgc_mode = 0x00020202,
>  		},
>  		.address_space_size = SZ_256G,
> +		.speedbins = ADRENO_SPEEDBINS(
> +			{ 0,   0 },
> +			{ 263, 1 },
> +			{ 315, 0 },
> +		),
>  		.preempt_record_size = 4192 * SZ_1K,
>  	}, {
>  		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
>  
>  int adreno_read_speedbin(struct device *dev, u32 *speedbin)
>  {
> -	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
> +	u32 hi_bits = 0;
> +	int ret;
> +
> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
> +	if (ret)
> +		return ret;
> +
> +	/* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
> +	if (ret != -ENOENT)
> +		return ret;
> +
> +	*speedbin |= (hi_bits << 8);

Now that we're overwriting speedbin, we should probably have some checks in
order to make sure somebody passing a too-wide cell to one of these won't
result in cripplingly-untraceable value corruption

I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it
a day?

Konrad

Re: [PATCH RFC 3/4] dt-bindings: nvmem: qfprom: Add X1E80100 compatible

[Krzysztof Kozlowski]

On Thu, Jan 09, 2025 at 04:12:40AM +0530, Akhil P Oommen wrote:
> Document compatible string for the QFPROM on X1E80100 platform.
> 
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---

This shouldn't be really RFC...

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH RFC 2/4] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner

[Krzysztof Kozlowski]

On Thu, Jan 09, 2025 at 04:12:39AM +0530, Akhil P Oommen wrote:
> Update the RPMH level definitions to include TURBO_L5 corner.
> 
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
>  include/dt-bindings/power/qcom-rpmpd.h | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85

[Akhil P Oommen]

On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
> On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
>> Adreno X1-85 has an additional bit which is at a non-contiguous
>> location in qfprom. Add support for this new "hi" bit along with
>> the speedbin mappings.
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  5 +++++
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 15 ++++++++++++++-
>>  2 files changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
>>  			.gmu_cgc_mode = 0x00020202,
>>  		},
>>  		.address_space_size = SZ_256G,
>> +		.speedbins = ADRENO_SPEEDBINS(
>> +			{ 0,   0 },
>> +			{ 263, 1 },
>> +			{ 315, 0 },
>> +		),
>>  		.preempt_record_size = 4192 * SZ_1K,
>>  	}, {
>>  		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
>>  
>>  int adreno_read_speedbin(struct device *dev, u32 *speedbin)
>>  {
>> -	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
>> +	u32 hi_bits = 0;
>> +	int ret;
>> +
>> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
>> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
>> +	if (ret != -ENOENT)
>> +		return ret;
>> +
>> +	*speedbin |= (hi_bits << 8);
> 
> Now that we're overwriting speedbin, we should probably have some checks in
> order to make sure somebody passing a too-wide cell to one of these won't
> result in cripplingly-untraceable value corruption
> 
> I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it
> a day?

X1E is an outlier here, because this was fixed from the next chipset
onward. For newer chipsets, we can use just the "speed_bin" node, which
represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) >
8)" here?

-Akhil.

> 
> Konrad

Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85

[Dmitry Baryshkov]

On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote:
> On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
> > On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
> >> Adreno X1-85 has an additional bit which is at a non-contiguous
> >> location in qfprom. Add support for this new "hi" bit along with
> >> the speedbin mappings.
> >> ---
> >>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  5 +++++
> >>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 15 ++++++++++++++-
> >>  2 files changed, 19 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
> >>  			.gmu_cgc_mode = 0x00020202,
> >>  		},
> >>  		.address_space_size = SZ_256G,
> >> +		.speedbins = ADRENO_SPEEDBINS(
> >> +			{ 0,   0 },
> >> +			{ 263, 1 },
> >> +			{ 315, 0 },
> >> +		),
> >>  		.preempt_record_size = 4192 * SZ_1K,
> >>  	}, {
> >>  		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> >> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
> >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> >> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
> >>  
> >>  int adreno_read_speedbin(struct device *dev, u32 *speedbin)
> >>  {
> >> -	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
> >> +	u32 hi_bits = 0;
> >> +	int ret;
> >> +
> >> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
> >> +	if (ret)
> >> +		return ret;
> >> +
> >> +	/* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
> >> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
> >> +	if (ret != -ENOENT)
> >> +		return ret;
> >> +
> >> +	*speedbin |= (hi_bits << 8);
> > 
> > Now that we're overwriting speedbin, we should probably have some checks in
> > order to make sure somebody passing a too-wide cell to one of these won't
> > result in cripplingly-untraceable value corruption
> > 
> > I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it
> > a day?
> 
> X1E is an outlier here, because this was fixed from the next chipset
> onward. For newer chipsets, we can use just the "speed_bin" node, which
> represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) >
> 8)" here?

Or extend nvmem core to support non-contiguous fields.

> 
> -Akhil.
> 
> > 
> > Konrad
> 

-- 
With best wishes
Dmitry

Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85

[Konrad Dybcio]

On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote:
> On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote:
>> On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
>>> On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
>>>> Adreno X1-85 has an additional bit which is at a non-contiguous
>>>> location in qfprom. Add support for this new "hi" bit along with
>>>> the speedbin mappings.
>>>> ---
>>>>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  5 +++++
>>>>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 15 ++++++++++++++-
>>>>  2 files changed, 19 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
>>>>  			.gmu_cgc_mode = 0x00020202,
>>>>  		},
>>>>  		.address_space_size = SZ_256G,
>>>> +		.speedbins = ADRENO_SPEEDBINS(
>>>> +			{ 0,   0 },
>>>> +			{ 263, 1 },
>>>> +			{ 315, 0 },
>>>> +		),
>>>>  		.preempt_record_size = 4192 * SZ_1K,
>>>>  	}, {
>>>>  		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
>>>>  
>>>>  int adreno_read_speedbin(struct device *dev, u32 *speedbin)
>>>>  {
>>>> -	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
>>>> +	u32 hi_bits = 0;
>>>> +	int ret;
>>>> +
>>>> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
>>>> +	if (ret)
>>>> +		return ret;
>>>> +
>>>> +	/* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
>>>> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
>>>> +	if (ret != -ENOENT)
>>>> +		return ret;
>>>> +
>>>> +	*speedbin |= (hi_bits << 8);
>>>
>>> Now that we're overwriting speedbin, we should probably have some checks in
>>> order to make sure somebody passing a too-wide cell to one of these won't
>>> result in cripplingly-untraceable value corruption
>>>
>>> I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it
>>> a day?
>>
>> X1E is an outlier here, because this was fixed from the next chipset
>> onward. For newer chipsets, we can use just the "speed_bin" node, which
>> represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) >
>> 8)" here?
> 
> Or extend nvmem core to support non-contiguous fields.

This sounds more desirable, as we surely aren't the only ones with
such a "feature"..

Konrad

Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85

[Akhil P Oommen]

On 1/17/2025 2:46 AM, Konrad Dybcio wrote:
> On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote:
>> On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote:
>>> On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
>>>> On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
>>>>> Adreno X1-85 has an additional bit which is at a non-contiguous
>>>>> location in qfprom. Add support for this new "hi" bit along with
>>>>> the speedbin mappings.
>>>>> ---
>>>>>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  5 +++++
>>>>>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 15 ++++++++++++++-
>>>>>  2 files changed, 19 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>>> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
>>>>>  			.gmu_cgc_mode = 0x00020202,
>>>>>  		},
>>>>>  		.address_space_size = SZ_256G,
>>>>> +		.speedbins = ADRENO_SPEEDBINS(
>>>>> +			{ 0,   0 },
>>>>> +			{ 263, 1 },
>>>>> +			{ 315, 0 },
>>>>> +		),
>>>>>  		.preempt_record_size = 4192 * SZ_1K,
>>>>>  	}, {
>>>>>  		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>>> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>>> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
>>>>>  
>>>>>  int adreno_read_speedbin(struct device *dev, u32 *speedbin)
>>>>>  {
>>>>> -	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
>>>>> +	u32 hi_bits = 0;
>>>>> +	int ret;
>>>>> +
>>>>> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
>>>>> +	if (ret)
>>>>> +		return ret;
>>>>> +
>>>>> +	/* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
>>>>> +	ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
>>>>> +	if (ret != -ENOENT)
>>>>> +		return ret;
>>>>> +
>>>>> +	*speedbin |= (hi_bits << 8);
>>>>
>>>> Now that we're overwriting speedbin, we should probably have some checks in
>>>> order to make sure somebody passing a too-wide cell to one of these won't
>>>> result in cripplingly-untraceable value corruption
>>>>
>>>> I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it
>>>> a day?
>>>
>>> X1E is an outlier here, because this was fixed from the next chipset
>>> onward. For newer chipsets, we can use just the "speed_bin" node, which
>>> represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) >
>>> 8)" here?
>>
>> Or extend nvmem core to support non-contiguous fields.
> 
> This sounds more desirable, as we surely aren't the only ones with
> such a "feature"..

Sounds good. I can explore that when I am back from vacation early next
month.

-Akhil.

> 
> Konrad

Re: (subset) [PATCH RFC 0/4] Support for Adreno X1-85 Speedbin along with new OPP levels

[Srinivas Kandagatla]

On Thu, 09 Jan 2025 04:12:37 +0530, Akhil P Oommen wrote:
> This series adds gpu speedbin support for Adreno X1-85 GPU along with
> additional OPP levels. Because the higher OPPs require GPU ACD feature,
> this series has dependency on the GPU ACD support series [1]. Also,
> there is dependency on dimtry's series which fixes dword alignment in
> nvmem driver [2]. We need a small fix up on top of that and that is
> being discussed there. Hence, the RFC tag.
> 
> [...]

Applied, thanks!

[3/4] dt-bindings: nvmem: qfprom: Add X1E80100 compatible
      commit: 3419bdfd88e314bc5f80b02fa4651c81a0a85b57

Best regards,
-- 
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>