* [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver
@ 2025-02-17 9:30 Jie Gan
2025-02-17 9:30 ` [PATCH v12 1/7] Coresight: Add support for new APB clock name Jie Gan
` (7 more replies)
0 siblings, 8 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
From: Jie Gan <jie.gan@oss.qualcomm.com>
The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration
registers to control various features related to TMC ETR device.
The CTCU device works as a helper device physically connected to the TMC ETR device.
---------------------------------------------------------
|ETR0| |ETR1|
. \ / .
. \ / .
. \ / .
. \ / .
---------------------------------------------------
ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3
---------------------------------------------------
Each ETR has four ATID registers with 128 bits long in total.
e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device.
Based on the trace id which is programed in CTCU ATID register of
specific ETR, trace data with that trace id can get into ETR's buffer
while other trace data gets ignored. The number of CTCU ATID registers
depends on the number of defined TMC ETR devices. For example, two TMC
ETR devices need eight ATID registers. ETR0 with ETR0ATID0-ETR0ATID3
and ETR1 with ETR1ATID0-ETRATID3.
The significant challenge in enabling the data filter function is how
to collect the trace ID of the source device. The introduction of
trace_id callback function addresses this challenge. The callback function
collects trace ID of the device and return it back. The trace ID will be
stored in the structure called coresight_path and transmitted to helper
and sink devices.
The coresight_path structure is created to address how to transmit
parameters needs by coresight_enable_path/coresight_disbale_path
functions.
Here is the definition of the struct coresight_path:
/**
* struct coresight_path - data needed by enable/disable path
* @path: path from source to sink.
* @trace_id: trace_id of the whole path.
*/
struct coresight_path {
struct list_head *path;
u8 trace_id;
};
The atid_offset mentioned before is the offset to ATID register in CTCU
device.
Enabling the source device will configure one bit in the ATID register based
on its trace ID.
Disabling the source devices will reset the bit in the AITD register
based on its trace ID.
Useage:
Enable:
STM device with trace ID 5 and ETR0 is activated.
Bitmap before the enablement:
ETR0ATID0:
31..................543210
==========================
0000000000000000000000...0
==========================
Bitmap after the enablement:
31..................543210
==========================
0000000000000...0000100000
==========================
The bit 5 of the ETR0ATID0 register is configured to 1 when enabling the
STM device.
Disable:
STM device with trace ID 5 and ETR0 is activated.
Bitmap before the disablement:
ETR0ATID0:
31................6543210
=========================
000000000010111...0100000
=========================
Bitmap after the disablement
ETR0ATID0:
31................6543210
=========================
000000000010111...0000000
=========================
The bit 5 of the ETR0ATID0 register is reset to 0 when disabling the STM
device.
Sincere thanks to James Clark for providing an excellent idea to handle
the trace_id of the path.
Changes in V12:
1. Update the method for allocating trace_id for perf mode.
Link to V11 - https://lore.kernel.org/linux-arm-msm/20250214024021.249655-1-quic_jiegan@quicinc.com/
Changes in V11:
1. Add reviewed-by tag to patch(2/7), (4/7), (6/7). Patch(3/7) is
contributed by James, so didnot add reviewed-by tag of James.
2. Fix warning reported by kernel bot and verified with build(W=1).
3. Restore to the original logic that responsible for allocate trace_id
of ETM device in perf mode according to James' comment.
Link to V10 - https://lore.kernel.org/linux-arm-msm/20250207064213.2314482-1-quic_jiegan@quicinc.com/
Changes in V10:
1. Introduce a new API to allocate and read trace_id after path is built.
2. Introduce a new API to allocate and read trace_id of ETM device.
3. Add a new patch: [PATCH v10 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show()
4. Remove perf handle from coresight_path.
5. Use u8 instead of atomic_t for traceid_refcnt.
6. Optimize the part of code in CTCU drvier that is responsible for program atid register.
Link to V9 - https://lore.kernel.org/all/20250124072537.1801030-1-quic_jiegan@quicinc.com/
Changes in V9:
1. Rebased on tag next-20250113.
2. Separate the previous trace_id patch (patch 2/5 Coresight: Add trace_id function to
retrieving the trace ID) into two patches.
3. Introduce a new struct coresight_path instead of cs_sink_data which was
created in previous version. The coresight_path will be initialized
and constructed in coresight_build_path function and released by
coresight_release_path function.
Detail of the struct coresight_path is shown below:
/**
* struct coresight_path - data needed by enable/disable path
* @path: path from source to sink.
* @trace_id: trace_id of the whole path.
*/
struct coresight_path {
struct list_head *path;
u8 trace_id;
};
4. Introduce an array of atomic in CTCU driver to represent the refcnt or each
enabled trace_id for each sink. The reason is there is a scenario that more
than one TPDM device physically connected to the same TPDA device has
been enabled. The CTCU driver must verify the refcnt before resetting the
bit of the atid register according to the trace_id of the TPDA device.
5. Remove redundant codes in CTCU driver.
6. Add reviewed-by tag to the commit message for APB clock path(patch
1/5).
Link to V8 - https://lore.kernel.org/all/20241226011022.1477160-1-quic_jiegan@quicinc.com/
Changes in V8:
1. Rebased on tag next-20241220.
2. Use raw_spinlock_t instead of spinlock_t.
3. Remove redundant codes in CTCU driver:
- Eliminate unnecessary parameter validations.
- Correct log level when an error occurs.
- Optimize codes.
4. Correct the subject prefix for DT patch.
5. Collected reviewed-by tag from Konrad Dybcib for DT patch.
Link to V7 - https://lore.kernel.org/all/20241210031545.3468561-1-quic_jiegan@quicinc.com/
Changes in V7:
1. Rebased on tag next-20241204.
2. Fix format issue for dts patch.
- Padding the address part to 8 digits
Link to V6 - https://lore.kernel.org/linux-arm-msm/20241009112503.1851585-1-quic_jiegan@quicinc.com/
Changes in V6:
1. Collected reviewed-by tag from Rob for dt-binding patch.
2. Rebased on tag next-20241008.
3. Dropped all depends-on tags.
Link to V5 - https://lore.kernel.org/linux-arm-msm/20240909033458.3118238-1-quic_jiegan@quicinc.com/
Changes in V5:
1. Fix the format issue for description paragrah in dt binding file.
2. Previous discussion for why use "in-ports" property instead of "ports".
Link to V4 - https://lore.kernel.org/linux-arm-msm/20240828012706.543605-1-quic_jiegan@quicinc.com/
Changes in V4:
1. Add TMC description in binding file.
2. Restrict the number of ports for the CTCU device to a range of 0 to 1 in the binding file,
because the maximum number of CTCU devices is 2 for existing projects.
Link to V3 - https://lore.kernel.org/linux-arm-kernel/20240812024141.2867655-1-quic_jiegan@quicinc.com/
Changes in V3:
1. Rename the device to Coresight TMC Control Unit(CTCU).
2. Introduce a new way to define the platform related configs. The new
structure, qcom_ctcu_config, is used to store configurations specific
to a platform. Each platform should have its own qcom_ctcu_config structure.
3. In perf mode, the ETM devices allocate their trace IDs using the
perf_sink_id_map. In sysfs mode, the ETM devices allocate their trace
IDs using the id_map_default.
4. Considering the scenario where both ETR devices might be enabled simultaneously
with multiple sources, retrieving and using trace IDs instead of id_map is more effective
for the CTCU device in sysfs mode. For example, We can configure one ETR as sink for high
throughput trace data like ETM and another ETR for low throughput trace data like STM.
In this case, STM data won’t be flushed out by ETM data quickly. However, if we use id_map to
manage the trace IDs, we need to create a separate id_map for each ETR device. Addtionally, We
would need to iterate through the entire id_map for each configuration.
5. Add support for apb's clock name "apb". If the function fails to obtain the clock with
the name "apb_pclk", it will attempt to acquire the clock with the name "apb".
Link to V2 - https://lore.kernel.org/linux-arm-msm/20240705090049.1656986-1-quic_jiegan@quicinc.com/T/#t
Changes in V2:
1. Rename the device to Coresight Control Unit.
2. Introduce the trace_id function pointer to address the challeng how to
properly collect the trace ID of the device.
3. Introduce a new way to define the qcom,ccu-atid-offset property in
device tree.
4. Disabling the filter function blocked on acquiring the ATID-offset,
which will be addressed in a separate patch once it’s ready.
Link to V1 - https://lore.kernel.org/lkml/20240618072726.3767974-1-quic_jiegan@quicinc.com/T/#t
James Clark (1):
Coresight: Use coresight_etm_get_trace_id() in traceid_show()
Jie Gan (6):
Coresight: Add support for new APB clock name
Coresight: Add trace_id function to retrieving the trace ID
Coresight: Introduce a new struct coresight_path
dt-bindings: arm: Add Coresight TMC Control Unit hardware
Coresight: Add Coresight TMC Control Unit driver
arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
.../bindings/arm/qcom,coresight-ctcu.yaml | 84 ++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++
drivers/hwtracing/coresight/Kconfig | 12 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-core.c | 133 +++++++--
drivers/hwtracing/coresight/coresight-ctcu.c | 268 ++++++++++++++++++
drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
drivers/hwtracing/coresight/coresight-dummy.c | 16 +-
.../hwtracing/coresight/coresight-etm-perf.c | 24 +-
.../hwtracing/coresight/coresight-etm-perf.h | 2 +-
drivers/hwtracing/coresight/coresight-etm.h | 1 -
.../coresight/coresight-etm3x-core.c | 55 +---
.../coresight/coresight-etm3x-sysfs.c | 3 +-
.../coresight/coresight-etm4x-core.c | 55 +---
.../coresight/coresight-etm4x-sysfs.c | 4 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 1 -
drivers/hwtracing/coresight/coresight-priv.h | 12 +-
drivers/hwtracing/coresight/coresight-stm.c | 14 +-
drivers/hwtracing/coresight/coresight-sysfs.c | 17 +-
drivers/hwtracing/coresight/coresight-tpda.c | 11 +
drivers/hwtracing/coresight/coresight-tpdm.c | 3 +-
include/linux/coresight.h | 30 +-
22 files changed, 762 insertions(+), 161 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
--
2.34.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v12 1/7] Coresight: Add support for new APB clock name
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-17 9:30 ` [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
` (6 subsequent siblings)
7 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
Add support for new APB clock-name. If the function fails
to obtain the clock with the name "apb_pclk", it will
attempt to acquire the clock with the name "apb".
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
include/linux/coresight.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 17276965ff1d..157c4bd009a1 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -459,8 +459,11 @@ static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev)
int ret;
pclk = clk_get(dev, "apb_pclk");
- if (IS_ERR(pclk))
- return NULL;
+ if (IS_ERR(pclk)) {
+ pclk = clk_get(dev, "apb");
+ if (IS_ERR(pclk))
+ return NULL;
+ }
ret = clk_prepare_enable(pclk);
if (ret) {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2025-02-17 9:30 ` [PATCH v12 1/7] Coresight: Add support for new APB clock name Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-20 17:34 ` Suzuki K Poulose
2025-02-17 9:30 ` [PATCH v12 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show() Jie Gan
` (5 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
Add 'trace_id' function pointer in ops. It's responsible for
retrieving the device's trace ID.
Co-developed-by: James Clark <james.clark@linaro.org>
Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-dummy.c | 11 ++++++++
.../coresight/coresight-etm3x-core.c | 1 +
.../coresight/coresight-etm4x-core.c | 1 +
drivers/hwtracing/coresight/coresight-stm.c | 11 ++++++++
drivers/hwtracing/coresight/coresight-tpda.c | 11 ++++++++
include/linux/coresight.h | 8 ++++++
7 files changed, 70 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 0a9380350fb5..6cad777757f3 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -23,6 +23,7 @@
#include "coresight-etm-perf.h"
#include "coresight-priv.h"
#include "coresight-syscfg.h"
+#include "coresight-trace-id.h"
/*
* Mutex used to lock all sysfs enable and disable actions and loading and
@@ -1515,6 +1516,32 @@ void coresight_remove_driver(struct amba_driver *amba_drv,
}
EXPORT_SYMBOL_GPL(coresight_remove_driver);
+int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
+ struct coresight_device *sink)
+{
+ int trace_id;
+ int cpu = source_ops(csdev)->cpu_id(csdev);
+
+ switch (mode) {
+ case CS_MODE_SYSFS:
+ trace_id = coresight_trace_id_get_cpu_id(cpu);
+ break;
+ case CS_MODE_PERF:
+ trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map);
+ break;
+ default:
+ trace_id = -EINVAL;
+ break;
+ }
+
+ if (!IS_VALID_CS_TRACE_ID(trace_id))
+ dev_err(&csdev->dev,
+ "Failed to allocate trace ID on CPU%d\n", cpu);
+
+ return trace_id;
+}
+EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id);
+
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c
index 9be53be8964b..c47f0382b943 100644
--- a/drivers/hwtracing/coresight/coresight-dummy.c
+++ b/drivers/hwtracing/coresight/coresight-dummy.c
@@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev,
dev_dbg(csdev->dev.parent, "Dummy source disabled\n");
}
+static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
+ __maybe_unused struct coresight_device *sink)
+{
+ struct dummy_drvdata *drvdata;
+
+ drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ return drvdata->traceid;
+}
+
static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode,
void *data)
{
@@ -59,6 +69,7 @@ static int dummy_sink_disable(struct coresight_device *csdev)
static const struct coresight_ops_source dummy_source_ops = {
.enable = dummy_source_enable,
.disable = dummy_source_disable,
+ .trace_id = dummy_source_trace_id,
};
static const struct coresight_ops dummy_source_cs_ops = {
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index c103f4c70f5d..a38e72ef8e79 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -701,6 +701,7 @@ static const struct coresight_ops_source etm_source_ops = {
.cpu_id = etm_cpu_id,
.enable = etm_enable,
.disable = etm_disable,
+ .trace_id = coresight_etm_get_trace_id,
};
static const struct coresight_ops etm_cs_ops = {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 2c1a60577728..1a993d5380e7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1064,6 +1064,7 @@ static const struct coresight_ops_source etm4_source_ops = {
.cpu_id = etm4_cpu_id,
.enable = etm4_enable,
.disable = etm4_disable,
+ .trace_id = coresight_etm_get_trace_id,
};
static const struct coresight_ops etm4_cs_ops = {
diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index b581a30a1cd9..64fcfa916562 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -281,9 +281,20 @@ static void stm_disable(struct coresight_device *csdev,
}
}
+static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
+ __maybe_unused struct coresight_device *sink)
+{
+ struct stm_drvdata *drvdata;
+
+ drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ return drvdata->traceid;
+}
+
static const struct coresight_ops_source stm_source_ops = {
.enable = stm_enable,
.disable = stm_disable,
+ .trace_id = stm_trace_id,
};
static const struct coresight_ops stm_cs_ops = {
diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
index 189a4abc2561..d80b6427e5a6 100644
--- a/drivers/hwtracing/coresight/coresight-tpda.c
+++ b/drivers/hwtracing/coresight/coresight-tpda.c
@@ -241,9 +241,20 @@ static void tpda_disable(struct coresight_device *csdev,
dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port);
}
+static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
+ __maybe_unused struct coresight_device *sink)
+{
+ struct tpda_drvdata *drvdata;
+
+ drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ return drvdata->atid;
+}
+
static const struct coresight_ops_link tpda_link_ops = {
.enable = tpda_enable,
.disable = tpda_disable,
+ .trace_id = tpda_trace_id,
};
static const struct coresight_ops tpda_cs_ops = {
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 157c4bd009a1..70407d61262e 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -368,6 +368,7 @@ struct coresight_ops_sink {
* Operations available for links.
* @enable: enables flow between iport and oport.
* @disable: disables flow between iport and oport.
+ * @trace_id: alloc or read the traceid.
*/
struct coresight_ops_link {
int (*enable)(struct coresight_device *csdev,
@@ -376,6 +377,8 @@ struct coresight_ops_link {
void (*disable)(struct coresight_device *csdev,
struct coresight_connection *in,
struct coresight_connection *out);
+ int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
+ struct coresight_device *sink);
};
/**
@@ -385,6 +388,7 @@ struct coresight_ops_link {
* is associated to.
* @enable: enables tracing for a source.
* @disable: disables tracing for a source.
+ * @trace_id: alloc or read the traceid.
*/
struct coresight_ops_source {
int (*cpu_id)(struct coresight_device *csdev);
@@ -392,6 +396,8 @@ struct coresight_ops_source {
enum cs_mode mode, struct coresight_trace_id_map *id_map);
void (*disable)(struct coresight_device *csdev,
struct perf_event *event);
+ int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
+ struct coresight_device *sink);
};
/**
@@ -697,4 +703,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv,
void coresight_remove_driver(struct amba_driver *amba_drv,
struct platform_driver *pdev_drv);
+int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
+ struct coresight_device *sink);
#endif /* _LINUX_COREISGHT_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v12 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show()
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2025-02-17 9:30 ` [PATCH v12 1/7] Coresight: Add support for new APB clock name Jie Gan
2025-02-17 9:30 ` [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-18 10:03 ` James Clark
2025-02-17 9:30 ` [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path Jie Gan
` (4 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
From: James Clark <james.clark@linaro.org>
Use the new API, coresight_etm_get_trace_id, to read the traceid of the ETM
device when call traceid_show via sysfs node.
Signed-off-by: James Clark <james.clark@linaro.org>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 3 +--
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index 68c644be9813..b9006451f515 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -1190,10 +1190,9 @@ static DEVICE_ATTR_RO(cpu);
static ssize_t traceid_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
- int trace_id;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ int trace_id = coresight_etm_get_trace_id(drvdata->csdev, CS_MODE_SYSFS, NULL);
- trace_id = etm_read_alloc_trace_id(drvdata);
if (trace_id < 0)
return trace_id;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index c767f8ae4cf1..e5216c0f60da 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -4,6 +4,7 @@
* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
*/
+#include <linux/coresight.h>
#include <linux/pid_namespace.h>
#include <linux/pm_runtime.h>
#include <linux/sysfs.h>
@@ -2402,10 +2403,9 @@ static ssize_t trctraceid_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- int trace_id;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ int trace_id = coresight_etm_get_trace_id(drvdata->csdev, CS_MODE_SYSFS, NULL);
- trace_id = etm4_read_alloc_trace_id(drvdata);
if (trace_id < 0)
return trace_id;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
` (2 preceding siblings ...)
2025-02-17 9:30 ` [PATCH v12 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show() Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-21 10:30 ` Suzuki K Poulose
2025-02-17 9:30 ` [PATCH v12 5/7] dt-bindings: arm: Add Coresight TMC Control Unit hardware Jie Gan
` (3 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
Add 'struct coresight_path' to store the data that is needed by
coresight_enable_path/coresight_disable_path. The structure will be
transmitted to any required devices to enable related funcationalities.
The trace_id will be allocated after the path is built. Consequently,
The ETM3x and ETM4x devices will directly read the trace_id from path
which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id
being deleted.
Co-developed-by: James Clark <james.clark@linaro.org>
Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
drivers/hwtracing/coresight/coresight-core.c | 106 +++++++++++++-----
drivers/hwtracing/coresight/coresight-dummy.c | 5 +-
.../hwtracing/coresight/coresight-etm-perf.c | 24 ++--
.../hwtracing/coresight/coresight-etm-perf.h | 2 +-
drivers/hwtracing/coresight/coresight-etm.h | 1 -
.../coresight/coresight-etm3x-core.c | 54 ++-------
.../coresight/coresight-etm4x-core.c | 54 ++-------
drivers/hwtracing/coresight/coresight-etm4x.h | 1 -
drivers/hwtracing/coresight/coresight-priv.h | 12 +-
drivers/hwtracing/coresight/coresight-stm.c | 3 +-
drivers/hwtracing/coresight/coresight-sysfs.c | 17 ++-
drivers/hwtracing/coresight/coresight-tpdm.c | 3 +-
include/linux/coresight.h | 12 +-
13 files changed, 140 insertions(+), 154 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 6cad777757f3..182bfa2420cc 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -76,14 +76,14 @@ struct coresight_device *coresight_get_percpu_sink(int cpu)
}
EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);
-static struct coresight_device *coresight_get_source(struct list_head *path)
+static struct coresight_device *coresight_get_source(struct coresight_path *path)
{
struct coresight_device *csdev;
if (!path)
return NULL;
- csdev = list_first_entry(path, struct coresight_node, link)->csdev;
+ csdev = list_first_entry(path->path_list, struct coresight_node, link)->csdev;
if (!coresight_is_device_source(csdev))
return NULL;
@@ -332,12 +332,12 @@ static int coresight_enable_helper(struct coresight_device *csdev,
return helper_ops(csdev)->enable(csdev, mode, data);
}
-static void coresight_disable_helper(struct coresight_device *csdev)
+static void coresight_disable_helper(struct coresight_device *csdev, void *data)
{
- helper_ops(csdev)->disable(csdev, NULL);
+ helper_ops(csdev)->disable(csdev, data);
}
-static void coresight_disable_helpers(struct coresight_device *csdev)
+static void coresight_disable_helpers(struct coresight_device *csdev, void *data)
{
int i;
struct coresight_device *helper;
@@ -345,7 +345,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev)
for (i = 0; i < csdev->pdata->nr_outconns; ++i) {
helper = csdev->pdata->out_conns[i]->dest_dev;
if (helper && coresight_is_helper(helper))
- coresight_disable_helper(helper);
+ coresight_disable_helper(helper, data);
}
}
@@ -362,7 +362,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev)
void coresight_disable_source(struct coresight_device *csdev, void *data)
{
source_ops(csdev)->disable(csdev, data);
- coresight_disable_helpers(csdev);
+ coresight_disable_helpers(csdev, NULL);
}
EXPORT_SYMBOL_GPL(coresight_disable_source);
@@ -371,16 +371,16 @@ EXPORT_SYMBOL_GPL(coresight_disable_source);
* @nd in the list. If @nd is NULL, all the components, except the SOURCE are
* disabled.
*/
-static void coresight_disable_path_from(struct list_head *path,
+static void coresight_disable_path_from(struct coresight_path *path,
struct coresight_node *nd)
{
u32 type;
struct coresight_device *csdev, *parent, *child;
if (!nd)
- nd = list_first_entry(path, struct coresight_node, link);
+ nd = list_first_entry(path->path_list, struct coresight_node, link);
- list_for_each_entry_continue(nd, path, link) {
+ list_for_each_entry_continue(nd, path->path_list, link) {
csdev = nd->csdev;
type = csdev->type;
@@ -418,11 +418,11 @@ static void coresight_disable_path_from(struct list_head *path,
}
/* Disable all helpers adjacent along the path last */
- coresight_disable_helpers(csdev);
+ coresight_disable_helpers(csdev, path);
}
}
-void coresight_disable_path(struct list_head *path)
+void coresight_disable_path(struct coresight_path *path)
{
coresight_disable_path_from(path, NULL);
}
@@ -447,7 +447,7 @@ static int coresight_enable_helpers(struct coresight_device *csdev,
return 0;
}
-int coresight_enable_path(struct list_head *path, enum cs_mode mode,
+int coresight_enable_path(struct coresight_path *path, enum cs_mode mode,
void *sink_data)
{
int ret = 0;
@@ -457,12 +457,12 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode,
struct coresight_device *source;
source = coresight_get_source(path);
- list_for_each_entry_reverse(nd, path, link) {
+ list_for_each_entry_reverse(nd, path->path_list, link) {
csdev = nd->csdev;
type = csdev->type;
/* Enable all helpers adjacent to the path first */
- ret = coresight_enable_helpers(csdev, mode, sink_data);
+ ret = coresight_enable_helpers(csdev, mode, path);
if (ret)
goto err;
/*
@@ -510,20 +510,21 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode,
goto out;
}
-struct coresight_device *coresight_get_sink(struct list_head *path)
+struct coresight_device *coresight_get_sink(struct coresight_path *path)
{
struct coresight_device *csdev;
if (!path)
return NULL;
- csdev = list_last_entry(path, struct coresight_node, link)->csdev;
+ csdev = list_last_entry(path->path_list, struct coresight_node, link)->csdev;
if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
return NULL;
return csdev;
}
+EXPORT_SYMBOL_GPL(coresight_get_sink);
u32 coresight_get_sink_id(struct coresight_device *csdev)
{
@@ -654,6 +655,51 @@ static void coresight_drop_device(struct coresight_device *csdev)
}
}
+/*
+ * Links or sources will read their existing or alloc a trace ID, if their ID
+ * callback is set.
+ */
+static int coresight_get_trace_id(struct coresight_device *csdev,
+ enum cs_mode mode,
+ struct coresight_device *sink)
+{
+ if (csdev->type == CORESIGHT_DEV_TYPE_LINK && link_ops(csdev)->trace_id)
+ return link_ops(csdev)->trace_id(csdev, mode, sink);
+
+ if (csdev->type == CORESIGHT_DEV_TYPE_SOURCE && source_ops(csdev)->trace_id)
+ return source_ops(csdev)->trace_id(csdev, mode, sink);
+
+ return 0;
+}
+
+/*
+ * Call this after creating the path and before enabling it. This leaves
+ * the trace ID set on the path and returns the ID, or an error if it
+ * couldn't be assigned.
+ */
+int coresight_path_assign_trace_id(struct coresight_path *path,
+ enum cs_mode mode)
+{
+ struct coresight_device *sink = coresight_get_sink(path);
+ struct coresight_node *nd;
+ int ret;
+
+ list_for_each_entry(nd, path->path_list, link) {
+ /* Assign a trace ID to the path for the first device that wants to do it */
+ ret = coresight_get_trace_id(nd->csdev, mode, sink);
+
+ /*
+ * 0 in this context is that it didn't want to assign so keep searching.
+ * Non 0 is either success or fail, return it either way.
+ */
+ if (ret != 0) {
+ path->trace_id = ret;
+ return ret;
+ }
+ }
+ return 0;
+}
+
/**
* _coresight_build_path - recursively build a path from a @csdev to a sink.
* @csdev: The device to start from.
@@ -669,7 +715,7 @@ static void coresight_drop_device(struct coresight_device *csdev)
static int _coresight_build_path(struct coresight_device *csdev,
struct coresight_device *source,
struct coresight_device *sink,
- struct list_head *path)
+ struct coresight_path *path)
{
int i, ret;
bool found = false;
@@ -722,28 +768,37 @@ static int _coresight_build_path(struct coresight_device *csdev,
return -ENOMEM;
node->csdev = csdev;
- list_add(&node->link, path);
+ list_add(&node->link, path->path_list);
return 0;
}
-struct list_head *coresight_build_path(struct coresight_device *source,
+struct coresight_path *coresight_build_path(struct coresight_device *source,
struct coresight_device *sink)
{
- struct list_head *path;
+ struct coresight_path *path;
+ struct list_head *path_list;
int rc;
if (!sink)
return ERR_PTR(-EINVAL);
- path = kzalloc(sizeof(struct list_head), GFP_KERNEL);
+ path = kzalloc(sizeof(struct coresight_path), GFP_KERNEL);
if (!path)
return ERR_PTR(-ENOMEM);
- INIT_LIST_HEAD(path);
+ path_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
+ if (!path_list) {
+ kfree(path);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ INIT_LIST_HEAD(path_list);
+ path->path_list = path_list;
rc = _coresight_build_path(source, source, sink, path);
if (rc) {
+ kfree(path_list);
kfree(path);
return ERR_PTR(rc);
}
@@ -758,12 +813,12 @@ struct list_head *coresight_build_path(struct coresight_device *source,
* Go through all the elements of a path and 1) removed it from the list and
* 2) free the memory allocated for each node.
*/
-void coresight_release_path(struct list_head *path)
+void coresight_release_path(struct coresight_path *path)
{
struct coresight_device *csdev;
struct coresight_node *nd, *next;
- list_for_each_entry_safe(nd, next, path, link) {
+ list_for_each_entry_safe(nd, next, path->path_list, link) {
csdev = nd->csdev;
coresight_drop_device(csdev);
@@ -771,6 +826,7 @@ void coresight_release_path(struct list_head *path)
kfree(nd);
}
+ kfree(path->path_list);
kfree(path);
}
diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c
index c47f0382b943..d9a811d44885 100644
--- a/drivers/hwtracing/coresight/coresight-dummy.c
+++ b/drivers/hwtracing/coresight/coresight-dummy.c
@@ -22,9 +22,8 @@ struct dummy_drvdata {
DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source");
DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink");
-static int dummy_source_enable(struct coresight_device *csdev,
- struct perf_event *event, enum cs_mode mode,
- __maybe_unused struct coresight_trace_id_map *id_map)
+static int dummy_source_enable(struct coresight_device *csdev, struct perf_event *event,
+ enum cs_mode mode, struct coresight_path *path)
{
if (!coresight_take_mode(csdev, mode))
return -EBUSY;
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index ad6a8f4b70b6..ebdcf56b7463 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -136,13 +136,13 @@ static const struct attribute_group *etm_pmu_attr_groups[] = {
NULL,
};
-static inline struct list_head **
+static inline struct coresight_path **
etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu)
{
return per_cpu_ptr(data->path, cpu);
}
-static inline struct list_head *
+static inline struct coresight_path *
etm_event_cpu_path(struct etm_event_data *data, int cpu)
{
return *etm_event_cpu_path_ptr(data, cpu);
@@ -226,7 +226,7 @@ static void free_event_data(struct work_struct *work)
cscfg_deactivate_config(event_data->cfg_hash);
for_each_cpu(cpu, mask) {
- struct list_head **ppath;
+ struct coresight_path **ppath;
ppath = etm_event_cpu_path_ptr(event_data, cpu);
if (!(IS_ERR_OR_NULL(*ppath))) {
@@ -276,7 +276,7 @@ static void *alloc_event_data(int cpu)
* unused memory when dealing with single CPU trace scenarios is small
* compared to the cost of searching through an optimized array.
*/
- event_data->path = alloc_percpu(struct list_head *);
+ event_data->path = alloc_percpu(struct coresight_path *);
if (!event_data->path) {
kfree(event_data);
@@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
* CPUs, we can handle it and fail the session.
*/
for_each_cpu(cpu, mask) {
- struct list_head *path;
+ struct coresight_path *path;
struct coresight_device *csdev;
csdev = per_cpu(csdev_src, cpu);
@@ -407,7 +407,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
}
/* ensure we can allocate a trace ID for this CPU */
- trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map);
+ trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF);
if (!IS_VALID_CS_TRACE_ID(trace_id)) {
cpumask_clear_cpu(cpu, mask);
coresight_release_path(path);
@@ -458,9 +458,8 @@ static void etm_event_start(struct perf_event *event, int flags)
struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
struct perf_output_handle *handle = &ctxt->handle;
struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
- struct list_head *path;
+ struct coresight_path *path;
u64 hw_id;
- u8 trace_id;
if (!csdev)
goto fail;
@@ -503,8 +502,7 @@ static void etm_event_start(struct perf_event *event, int flags)
goto fail_end_stop;
/* Finally enable the tracer */
- if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF,
- &sink->perf_sink_id_map))
+ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, path))
goto fail_disable_path;
/*
@@ -514,13 +512,11 @@ static void etm_event_start(struct perf_event *event, int flags)
if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) {
cpumask_set_cpu(cpu, &event_data->aux_hwid_done);
- trace_id = coresight_trace_id_read_cpu_id_map(cpu, &sink->perf_sink_id_map);
-
hw_id = FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK,
CS_AUX_HW_ID_MAJOR_VERSION);
hw_id |= FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK,
CS_AUX_HW_ID_MINOR_VERSION);
- hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, trace_id);
+ hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, path->trace_id);
hw_id |= FIELD_PREP(CS_AUX_HW_ID_SINK_ID_MASK, coresight_get_sink_id(sink));
perf_report_aux_output_id(event, hw_id);
@@ -558,7 +554,7 @@ static void etm_event_stop(struct perf_event *event, int mode)
struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
struct perf_output_handle *handle = &ctxt->handle;
struct etm_event_data *event_data;
- struct list_head *path;
+ struct coresight_path *path;
/*
* If we still have access to the event_data via handle,
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h
index 744531158d6b..5febbcdb8696 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -59,7 +59,7 @@ struct etm_event_data {
cpumask_t aux_hwid_done;
void *snk_config;
u32 cfg_hash;
- struct list_head * __percpu *path;
+ struct coresight_path * __percpu *path;
};
int etm_perf_symlink(struct coresight_device *csdev, bool link);
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index e02c3ea972c9..171f1384f7c0 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -284,6 +284,5 @@ extern const struct attribute_group *coresight_etm_groups[];
void etm_set_default(struct etm_config *config);
void etm_config_trace_mode(struct etm_config *config);
struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
-int etm_read_alloc_trace_id(struct etm_drvdata *drvdata);
void etm_release_trace_id(struct etm_drvdata *drvdata);
#endif
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index a38e72ef8e79..cb8a30a3b48e 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -455,26 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev)
return drvdata->cpu;
}
-int etm_read_alloc_trace_id(struct etm_drvdata *drvdata)
-{
- int trace_id;
-
- /*
- * This will allocate a trace ID to the cpu,
- * or return the one currently allocated.
- *
- * trace id function has its own lock
- */
- trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
- if (IS_VALID_CS_TRACE_ID(trace_id))
- drvdata->traceid = (u8)trace_id;
- else
- dev_err(&drvdata->csdev->dev,
- "Failed to allocate trace ID for %s on CPU%d\n",
- dev_name(&drvdata->csdev->dev), drvdata->cpu);
- return trace_id;
-}
-
void etm_release_trace_id(struct etm_drvdata *drvdata)
{
coresight_trace_id_put_cpu_id(drvdata->cpu);
@@ -482,38 +462,22 @@ void etm_release_trace_id(struct etm_drvdata *drvdata)
static int etm_enable_perf(struct coresight_device *csdev,
struct perf_event *event,
- struct coresight_trace_id_map *id_map)
+ struct coresight_path *path)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- int trace_id;
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
return -EINVAL;
/* Configure the tracer based on the session's specifics */
etm_parse_event_config(drvdata, event);
-
- /*
- * perf allocates cpu ids as part of _setup_aux() - device needs to use
- * the allocated ID. This reads the current version without allocation.
- *
- * This does not use the trace id lock to prevent lock_dep issues
- * with perf locks - we know the ID cannot change until perf shuts down
- * the session
- */
- trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
- if (!IS_VALID_CS_TRACE_ID(trace_id)) {
- dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
- dev_name(&drvdata->csdev->dev), drvdata->cpu);
- return -EINVAL;
- }
- drvdata->traceid = (u8)trace_id;
+ drvdata->traceid = path->trace_id;
/* And enable it */
return etm_enable_hw(drvdata);
}
-static int etm_enable_sysfs(struct coresight_device *csdev)
+static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etm_enable_arg arg = { };
@@ -521,10 +485,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
spin_lock(&drvdata->spinlock);
- /* sysfs needs to allocate and set a trace ID */
- ret = etm_read_alloc_trace_id(drvdata);
- if (ret < 0)
- goto unlock_enable_sysfs;
+ drvdata->traceid = path->trace_id;
/*
* Configure the ETM only if the CPU is online. If it isn't online
@@ -545,7 +506,6 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
if (ret)
etm_release_trace_id(drvdata);
-unlock_enable_sysfs:
spin_unlock(&drvdata->spinlock);
if (!ret)
@@ -554,7 +514,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
}
static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
- enum cs_mode mode, struct coresight_trace_id_map *id_map)
+ enum cs_mode mode, struct coresight_path *path)
{
int ret;
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -566,10 +526,10 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
switch (mode) {
case CS_MODE_SYSFS:
- ret = etm_enable_sysfs(csdev);
+ ret = etm_enable_sysfs(csdev, path);
break;
case CS_MODE_PERF:
- ret = etm_enable_perf(csdev, event, id_map);
+ ret = etm_enable_perf(csdev, event, path);
break;
default:
ret = -EINVAL;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 1a993d5380e7..3d0fc25085ea 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -233,25 +233,6 @@ static int etm4_cpu_id(struct coresight_device *csdev)
return drvdata->cpu;
}
-int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
-{
- int trace_id;
-
- /*
- * This will allocate a trace ID to the cpu,
- * or return the one currently allocated.
- * The trace id function has its own lock
- */
- trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
- if (IS_VALID_CS_TRACE_ID(trace_id))
- drvdata->trcid = (u8)trace_id;
- else
- dev_err(&drvdata->csdev->dev,
- "Failed to allocate trace ID for %s on CPU%d\n",
- dev_name(&drvdata->csdev->dev), drvdata->cpu);
- return trace_id;
-}
-
void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
{
coresight_trace_id_put_cpu_id(drvdata->cpu);
@@ -788,9 +769,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
static int etm4_enable_perf(struct coresight_device *csdev,
struct perf_event *event,
- struct coresight_trace_id_map *id_map)
+ struct coresight_path *path)
{
- int ret = 0, trace_id;
+ int ret = 0;
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
@@ -803,22 +784,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
if (ret)
goto out;
- /*
- * perf allocates cpu ids as part of _setup_aux() - device needs to use
- * the allocated ID. This reads the current version without allocation.
- *
- * This does not use the trace id lock to prevent lock_dep issues
- * with perf locks - we know the ID cannot change until perf shuts down
- * the session
- */
- trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
- if (!IS_VALID_CS_TRACE_ID(trace_id)) {
- dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
- dev_name(&drvdata->csdev->dev), drvdata->cpu);
- ret = -EINVAL;
- goto out;
- }
- drvdata->trcid = (u8)trace_id;
+ drvdata->trcid = path->trace_id;
/* And enable it */
ret = etm4_enable_hw(drvdata);
@@ -827,7 +793,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
return ret;
}
-static int etm4_enable_sysfs(struct coresight_device *csdev)
+static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etm4_enable_arg arg = { };
@@ -844,10 +810,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
spin_lock(&drvdata->spinlock);
- /* sysfs needs to read and allocate a trace ID */
- ret = etm4_read_alloc_trace_id(drvdata);
- if (ret < 0)
- goto unlock_sysfs_enable;
+ drvdata->trcid = path->trace_id;
/*
* Executing etm4_enable_hw on the cpu whose ETM is being enabled
@@ -864,7 +827,6 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
if (ret)
etm4_release_trace_id(drvdata);
-unlock_sysfs_enable:
spin_unlock(&drvdata->spinlock);
if (!ret)
@@ -873,7 +835,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
}
static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
- enum cs_mode mode, struct coresight_trace_id_map *id_map)
+ enum cs_mode mode, struct coresight_path *path)
{
int ret;
@@ -884,10 +846,10 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
switch (mode) {
case CS_MODE_SYSFS:
- ret = etm4_enable_sysfs(csdev);
+ ret = etm4_enable_sysfs(csdev, path);
break;
case CS_MODE_PERF:
- ret = etm4_enable_perf(csdev, event, id_map);
+ ret = etm4_enable_perf(csdev, event, path);
break;
default:
ret = -EINVAL;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 1119762b5cec..2b92de17b5a2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -1066,6 +1066,5 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
return drvdata->arch >= ETM_ARCH_ETE;
}
-int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata);
void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
#endif
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 76403530f33e..c10dd3643854 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -132,16 +132,16 @@ static inline void CS_UNLOCK(void __iomem *addr)
} while (0);
}
-void coresight_disable_path(struct list_head *path);
-int coresight_enable_path(struct list_head *path, enum cs_mode mode,
+void coresight_disable_path(struct coresight_path *path);
+int coresight_enable_path(struct coresight_path *path, enum cs_mode mode,
void *sink_data);
-struct coresight_device *coresight_get_sink(struct list_head *path);
+struct coresight_device *coresight_get_sink(struct coresight_path *path);
struct coresight_device *coresight_get_sink_by_id(u32 id);
struct coresight_device *
coresight_find_default_sink(struct coresight_device *csdev);
-struct list_head *coresight_build_path(struct coresight_device *csdev,
+struct coresight_path *coresight_build_path(struct coresight_device *csdev,
struct coresight_device *sink);
-void coresight_release_path(struct list_head *path);
+void coresight_release_path(struct coresight_path *path);
int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
@@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig,
void coresight_remove_links(struct coresight_device *orig,
struct coresight_connection *conn);
u32 coresight_get_sink_id(struct coresight_device *csdev);
+int coresight_path_assign_trace_id(struct coresight_path *path,
+ enum cs_mode mode);
#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
extern int etm_readl_cp14(u32 off, unsigned int *val);
diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index 64fcfa916562..0d4a9d325df4 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -194,8 +194,7 @@ static void stm_enable_hw(struct stm_drvdata *drvdata)
}
static int stm_enable(struct coresight_device *csdev, struct perf_event *event,
- enum cs_mode mode,
- __maybe_unused struct coresight_trace_id_map *trace_id)
+ enum cs_mode mode, struct coresight_path *path)
{
struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c
index a01c9e54e2ed..c2b0a1f59d1a 100644
--- a/drivers/hwtracing/coresight/coresight-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-sysfs.c
@@ -22,7 +22,7 @@ static DEFINE_IDR(path_idr);
* When operating Coresight drivers from the sysFS interface, only a single
* path can exist from a tracer (associated to a CPU) to a sink.
*/
-static DEFINE_PER_CPU(struct list_head *, tracer_path);
+static DEFINE_PER_CPU(struct coresight_path *, tracer_path);
ssize_t coresight_simple_show_pair(struct device *_dev,
struct device_attribute *attr, char *buf)
@@ -53,7 +53,8 @@ ssize_t coresight_simple_show32(struct device *_dev,
EXPORT_SYMBOL_GPL(coresight_simple_show32);
static int coresight_enable_source_sysfs(struct coresight_device *csdev,
- enum cs_mode mode, void *data)
+ enum cs_mode mode,
+ struct coresight_path *path)
{
int ret;
@@ -64,7 +65,7 @@ static int coresight_enable_source_sysfs(struct coresight_device *csdev,
*/
lockdep_assert_held(&coresight_mutex);
if (coresight_get_mode(csdev) != CS_MODE_SYSFS) {
- ret = source_ops(csdev)->enable(csdev, data, mode, NULL);
+ ret = source_ops(csdev)->enable(csdev, NULL, mode, path);
if (ret)
return ret;
}
@@ -167,7 +168,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev)
{
int cpu, ret = 0;
struct coresight_device *sink;
- struct list_head *path;
+ struct coresight_path *path;
enum coresight_dev_subtype_source subtype;
u32 hash;
@@ -209,11 +210,15 @@ int coresight_enable_sysfs(struct coresight_device *csdev)
goto out;
}
+ ret = coresight_path_assign_trace_id(path, CS_MODE_SYSFS);
+ if (ret < 0)
+ goto err_path;
+
ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL);
if (ret)
goto err_path;
- ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, NULL);
+ ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, path);
if (ret)
goto err_source;
@@ -262,7 +267,7 @@ EXPORT_SYMBOL_GPL(coresight_enable_sysfs);
void coresight_disable_sysfs(struct coresight_device *csdev)
{
int cpu, ret;
- struct list_head *path = NULL;
+ struct coresight_path *path = NULL;
u32 hash;
mutex_lock(&coresight_mutex);
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index c38f9701665e..f0880a62028f 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -439,8 +439,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata)
}
static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event,
- enum cs_mode mode,
- __maybe_unused struct coresight_trace_id_map *id_map)
+ enum cs_mode mode, struct coresight_path *path)
{
struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 70407d61262e..03d833a15726 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -329,6 +329,16 @@ static struct coresight_dev_list (var) = { \
#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
+/**
+ * struct coresight_path - data needed by enable/disable path
+ * @path: path from source to sink.
+ * @trace_id: trace_id of the whole path.
+ */
+struct coresight_path {
+ struct list_head *path_list;
+ u8 trace_id;
+};
+
enum cs_mode {
CS_MODE_DISABLED,
CS_MODE_SYSFS,
@@ -393,7 +403,7 @@ struct coresight_ops_link {
struct coresight_ops_source {
int (*cpu_id)(struct coresight_device *csdev);
int (*enable)(struct coresight_device *csdev, struct perf_event *event,
- enum cs_mode mode, struct coresight_trace_id_map *id_map);
+ enum cs_mode mode, struct coresight_path *path);
void (*disable)(struct coresight_device *csdev,
struct perf_event *event);
int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v12 5/7] dt-bindings: arm: Add Coresight TMC Control Unit hardware
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
` (3 preceding siblings ...)
2025-02-17 9:30 ` [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-17 9:30 ` [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
` (2 subsequent siblings)
7 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
Add binding file to specify how to define a Coresight TMC
Control Unit device in device tree.
It is responsible for controlling the data filter function
based on the source device's Trace ID for TMC ETR device.
The trace data with that Trace id can get into ETR's buffer
while other trace data gets ignored.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
.../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
new file mode 100644
index 000000000000..843b52eaf872
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CoreSight TMC Control Unit
+
+maintainers:
+ - Yuanfang Zhang <quic_yuanfang@quicinc.com>
+ - Mao Jinlong <quic_jinlmao@quicinc.com>
+ - Jie Gan <quic_jiegan@quicinc.com>
+
+description: |
+ The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
+ Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations.
+ The configuration mode (ETB, ETF, ETR) is discovered at boot time when
+ the device is probed.
+
+ The Coresight TMC Control unit controls various Coresight behaviors.
+ It works as a helper device when connected to TMC ETR device.
+ It is responsible for controlling the data filter function based on
+ the source device's Trace ID for TMC ETR device. The trace data with
+ that Trace id can get into ETR's buffer while other trace data gets
+ ignored.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-ctcu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: apb
+
+ in-ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ patternProperties:
+ '^port(@[0-1])?$':
+ description: Input connections from CoreSight Trace bus
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - in-ports
+
+additionalProperties: false
+
+examples:
+ - |
+ ctcu@1001000 {
+ compatible = "qcom,sa8775p-ctcu";
+ reg = <0x1001000 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ctcu_in_port0: endpoint {
+ remote-endpoint = <&etr0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ctcu_in_port1: endpoint {
+ remote-endpoint = <&etr1_out_port>;
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
` (4 preceding siblings ...)
2025-02-17 9:30 ` [PATCH v12 5/7] dt-bindings: arm: Add Coresight TMC Control Unit hardware Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-21 11:39 ` Suzuki K Poulose
2025-02-17 9:30 ` [PATCH v12 7/7] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
2025-02-18 10:05 ` [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver James Clark
7 siblings, 1 reply; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
The Coresight TMC Control Unit hosts miscellaneous configuration registers
which control various features related to TMC ETR sink.
Based on the trace ID, which is programmed in the related CTCU ATID
register of a specific ETR, trace data with that trace ID gets into
the ETR buffer, while other trace data gets dropped.
Enabling source device sets one bit of the ATID register based on
source device's trace ID.
Disabling source device resets the bit according to the source
device's trace ID.
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 12 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
include/linux/coresight.h | 3 +-
5 files changed, 307 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 06f0a7594169..ecd7086a5b83 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -133,6 +133,18 @@ config CORESIGHT_STM
To compile this driver as a module, choose M here: the
module will be called coresight-stm.
+config CORESIGHT_CTCU
+ tristate "CoreSight TMC Control Unit driver"
+ depends on CORESIGHT_LINK_AND_SINK_TMC
+ help
+ This driver provides support for CoreSight TMC Control Unit
+ that hosts miscellaneous configuration registers. This is
+ primarily used for controlling the behaviors of the TMC
+ ETR device.
+
+ To compile this driver as a module, choose M here: the
+ module will be called coresight-ctcu.
+
config CORESIGHT_CPU_DEBUG
tristate "CoreSight CPU Debug driver"
depends on ARM || ARM64
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index 4ba478211b31..1b7869910a12 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
coresight-cti-sysfs.o
obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
+obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/hwtracing/coresight/coresight-ctcu.c
new file mode 100644
index 000000000000..e1460a627c4d
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-ctcu.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "coresight-ctcu.h"
+#include "coresight-priv.h"
+
+DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
+
+#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
+#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
+
+/*
+ * The TMC Coresight Control Unit uses four ATID registers to control the data
+ * filter function based on the trace ID for each TMC ETR sink. The length of
+ * each ATID register is 32 bits. Therefore, the ETR has a related field in
+ * CTCU that is 128 bits long. Each trace ID is represented by one bit in that
+ * filed.
+ * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
+ * bit5
+ * ------------------------------------------------------
+ * | |28| |24| |20| |16| |12| |8| 1|4| |0|
+ * ------------------------------------------------------
+ *
+ * e.g. ETR0:
+ * 127 0 from ATID_offset for ETR0ATID0
+ * -------------------------
+ * |ATID3|ATID2|ATID1|ATID0|
+ */
+#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
+ ((traceid / 32) * 4 + atid_offset)
+
+#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
+#define CTCU_ATID_REG_SIZE 0x10
+
+struct ctcu_atid_config {
+ const u32 atid_offset;
+ const u32 port_num;
+};
+
+struct ctcu_config {
+ const struct ctcu_atid_config *atid_config;
+ int num_atid_config;
+};
+
+static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
+ {0xf8, 0},
+ {0x108, 1},
+};
+
+static const struct ctcu_config sa8775p_cfgs = {
+ .atid_config = sa8775p_atid_cfgs,
+ .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
+};
+
+static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset,
+ u8 bit, bool enable)
+{
+ u32 val;
+
+ CS_UNLOCK(drvdata->base);
+ val = ctcu_readl(drvdata, reg_offset);
+ val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
+ ctcu_writel(drvdata, val, reg_offset);
+ CS_LOCK(drvdata->base);
+}
+
+/*
+ * __ctcu_set_etr_traceid: Set bit in the ATID register based on trace ID when enable is true.
+ * Reset the bit of the ATID register based on trace ID when enable is false.
+ *
+ * @csdev: coresight_device struct related to the device
+ * @traceid: trace ID of the source tracer.
+ * @port_num: port number from TMC ETR sink.
+ * @enable: True for set bit and false for reset bit.
+ *
+ * Returns 0 indicates success. Non-zero result means failure.
+ */
+static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, int port_num,
+ bool enable)
+{
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ u32 atid_offset, reg_offset;
+ u8 refcnt, bit;
+
+ atid_offset = drvdata->atid_offset[port_num];
+ if (atid_offset == 0)
+ return -EINVAL;
+
+ bit = CTCU_ATID_REG_BIT(traceid);
+ reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
+ if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
+ return -EINVAL;
+
+ guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
+ refcnt = drvdata->traceid_refcnt[port_num][traceid];
+ /* Only program the atid register when the refcnt value is 0 or 1 */
+ if (enable && (++refcnt == 1))
+ ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
+ else if (!enable && (--refcnt == 0))
+ ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
+
+ drvdata->traceid_refcnt[port_num][traceid] = refcnt;
+
+ return 0;
+}
+
+static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper)
+{
+ int i;
+
+ for (i = 0; i < sink->pdata->nr_outconns; ++i) {
+ if (sink->pdata->out_conns[i]->dest_dev)
+ return sink->pdata->out_conns[i]->dest_port;
+ }
+
+ return -EINVAL;
+}
+
+static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *path,
+ bool enable)
+{
+ struct coresight_device *sink = coresight_get_sink(path);
+ u8 traceid = path->trace_id;
+ int port_num;
+
+ if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(traceid)) {
+ dev_err(&csdev->dev, "Invalid parameters\n");
+ return -EINVAL;
+ }
+
+ port_num = ctcu_get_active_port(sink, csdev);
+ if (port_num < 0)
+ return -EINVAL;
+
+ dev_dbg(&csdev->dev, "traceid is %d\n", traceid);
+
+ return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable);
+}
+
+static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode,
+ void *data)
+{
+ struct coresight_path *path = (struct coresight_path *)data;
+
+ return ctcu_set_etr_traceid(csdev, path, true);
+}
+
+static int ctcu_disable(struct coresight_device *csdev, void *data)
+{
+ struct coresight_path *path = (struct coresight_path *)data;
+
+ return ctcu_set_etr_traceid(csdev, path, false);
+}
+
+static const struct coresight_ops_helper ctcu_helper_ops = {
+ .enable = ctcu_enable,
+ .disable = ctcu_disable,
+};
+
+static const struct coresight_ops ctcu_ops = {
+ .helper_ops = &ctcu_helper_ops,
+};
+
+static int ctcu_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *base;
+ struct device *dev = &pdev->dev;
+ struct coresight_platform_data *pdata;
+ struct ctcu_drvdata *drvdata;
+ struct coresight_desc desc = { 0 };
+ const struct ctcu_config *cfgs;
+ const struct ctcu_atid_config *atid_cfg;
+
+ desc.name = coresight_alloc_device_name(&ctcu_devs, dev);
+ if (!desc.name)
+ return -ENOMEM;
+
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ pdata = coresight_get_platform_data(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ dev->platform_data = pdata;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ if (!base)
+ return -ENOMEM;
+
+ drvdata->apb_clk = coresight_get_enable_apb_pclk(dev);
+ if (IS_ERR(drvdata->apb_clk))
+ return -ENODEV;
+
+ cfgs = of_device_get_match_data(dev);
+ if (cfgs) {
+ if (cfgs->num_atid_config <= ATID_MAX_NUM) {
+ for (i = 0; i < cfgs->num_atid_config; i++) {
+ atid_cfg = &cfgs->atid_config[i];
+ drvdata->atid_offset[i] = atid_cfg->atid_offset;
+ }
+ }
+ }
+
+ drvdata->base = base;
+ drvdata->dev = dev;
+ platform_set_drvdata(pdev, drvdata);
+
+ desc.type = CORESIGHT_DEV_TYPE_HELPER;
+ desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU;
+ desc.pdata = pdata;
+ desc.dev = dev;
+ desc.ops = &ctcu_ops;
+
+ drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev)) {
+ if (!IS_ERR_OR_NULL(drvdata->apb_clk))
+ clk_put(drvdata->apb_clk);
+
+ return PTR_ERR(drvdata->csdev);
+ }
+
+ return 0;
+}
+
+static void ctcu_remove(struct platform_device *pdev)
+{
+ struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev);
+
+ coresight_unregister(drvdata->csdev);
+ if (!IS_ERR_OR_NULL(drvdata->apb_clk))
+ clk_put(drvdata->apb_clk);
+}
+
+static const struct of_device_id ctcu_match[] = {
+ {.compatible = "qcom,sa8775p-ctcu", .data = &sa8775p_cfgs},
+ {}
+};
+
+static struct platform_driver ctcu_driver = {
+ .probe = ctcu_probe,
+ .remove = ctcu_remove,
+ .driver = {
+ .name = "coresight-ctcu",
+ .of_match_table = ctcu_match,
+ .suppress_bind_attrs = true,
+ },
+};
+module_platform_driver(ctcu_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CoreSight TMC Control Unit driver");
diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h
new file mode 100644
index 000000000000..9890c3da5ec8
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-ctcu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CORESIGHT_CTCU_H
+#define _CORESIGHT_CTCU_H
+#include "coresight-trace-id.h"
+
+/* Maximum number of supported sink devices for a single CTCU in current projects. */
+#define ATID_MAX_NUM 2
+
+struct ctcu_drvdata {
+ void __iomem *base;
+ struct clk *apb_clk;
+ phys_addr_t pbase;
+ struct device *dev;
+ struct coresight_device *csdev;
+ raw_spinlock_t spin_lock;
+ u32 atid_offset[ATID_MAX_NUM];
+ /* refcnt for each traceid of each sink */
+ u8 traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
+};
+#endif
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 03d833a15726..55bb825d509e 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -71,7 +71,8 @@ enum coresight_dev_subtype_source {
enum coresight_dev_subtype_helper {
CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
- CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI
+ CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI,
+ CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,
};
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v12 7/7] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
` (5 preceding siblings ...)
2025-02-17 9:30 ` [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
@ 2025-02-17 9:30 ` Jie Gan
2025-02-18 10:05 ` [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver James Clark
7 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-17 9:30 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32,
Konrad Dybcio
Add CTCU and ETR nodes in DT to enable related functionalities.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 3394ae2d1300..31aa94d2a043 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2429,6 +2429,35 @@ crypto: crypto@1dfa000 {
interconnect-names = "memory";
};
+ ctcu@4001000 {
+ compatible = "qcom,sa8775p-ctcu";
+ reg = <0x0 0x04001000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ctcu_in0: endpoint {
+ remote-endpoint = <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ctcu_in1: endpoint {
+ remote-endpoint = <&etr1_out>;
+ };
+ };
+ };
+ };
+
stm: stm@4002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x4002000 0x0 0x1000>,
@@ -2633,6 +2662,122 @@ qdss_funnel_in1: endpoint {
};
};
+ replicator@4046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x04046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint = <&swao_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_rep_out0: endpoint {
+ remote-endpoint = <&etr_rep_in>;
+ };
+ };
+ };
+ };
+
+ tmc_etr: tmc@4048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x04048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04c0 0x00>;
+
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint = <&etr_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint = <&ctcu_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@404e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x0404e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint = <&qdss_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ etr_rep_out0: endpoint {
+ remote-endpoint = <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ etr_rep_out1: endpoint {
+ remote-endpoint = <&etr1_in>;
+ };
+ };
+ };
+ };
+
+ tmc_etr1: tmc@404f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x0404f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04a0 0x40>;
+
+ arm,scatter-gather;
+ arm,buffer-size = <0x400000>;
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint = <&etr_rep_out1>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint = <&ctcu_in1>;
+ };
+ };
+ };
+ };
+
funnel@4b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x4b04000 0x0 0x1000>;
@@ -2708,6 +2853,14 @@ out-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ swao_rep_out0: endpoint {
+ remote-endpoint = <&qdss_rep_in>;
+ };
+ };
+
port@1 {
reg = <1>;
swao_rep_out1: endpoint {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v12 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show()
2025-02-17 9:30 ` [PATCH v12 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show() Jie Gan
@ 2025-02-18 10:03 ` James Clark
0 siblings, 0 replies; 22+ messages in thread
From: James Clark @ 2025-02-18 10:03 UTC (permalink / raw)
To: Jie Gan
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32,
Suzuki K Poulose, Mike Leach, Alexander Shishkin, Maxime Coquelin,
Alexandre Torgue, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
On 17/02/2025 9:30 am, Jie Gan wrote:
> From: James Clark <james.clark@linaro.org>
>
> Use the new API, coresight_etm_get_trace_id, to read the traceid of the ETM
> device when call traceid_show via sysfs node.
>
> Signed-off-by: James Clark <james.clark@linaro.org>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 3 +--
> drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 4 ++--
> 2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> index 68c644be9813..b9006451f515 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> @@ -1190,10 +1190,9 @@ static DEVICE_ATTR_RO(cpu);
> static ssize_t traceid_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> - int trace_id;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + int trace_id = coresight_etm_get_trace_id(drvdata->csdev, CS_MODE_SYSFS, NULL);
>
> - trace_id = etm_read_alloc_trace_id(drvdata);
> if (trace_id < 0)
> return trace_id;
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index c767f8ae4cf1..e5216c0f60da 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -4,6 +4,7 @@
> * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
> */
>
> +#include <linux/coresight.h>
> #include <linux/pid_namespace.h>
> #include <linux/pm_runtime.h>
> #include <linux/sysfs.h>
> @@ -2402,10 +2403,9 @@ static ssize_t trctraceid_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> {
> - int trace_id;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + int trace_id = coresight_etm_get_trace_id(drvdata->csdev, CS_MODE_SYSFS, NULL);
>
> - trace_id = etm4_read_alloc_trace_id(drvdata);
> if (trace_id < 0)
> return trace_id;
>
Reviewed-by: James Clark <james.clark@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
` (6 preceding siblings ...)
2025-02-17 9:30 ` [PATCH v12 7/7] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
@ 2025-02-18 10:05 ` James Clark
2025-02-19 0:59 ` Jie Gan
7 siblings, 1 reply; 22+ messages in thread
From: James Clark @ 2025-02-18 10:05 UTC (permalink / raw)
To: Jie Gan, Suzuki K Poulose
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32, Mike Leach,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
On 17/02/2025 9:30 am, Jie Gan wrote:
> From: Jie Gan <jie.gan@oss.qualcomm.com>
>
> The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration
> registers to control various features related to TMC ETR device.
>
> The CTCU device works as a helper device physically connected to the TMC ETR device.
> ---------------------------------------------------------
> |ETR0| |ETR1|
> . \ / .
> . \ / .
> . \ / .
> . \ / .
> ---------------------------------------------------
> ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3
> ---------------------------------------------------
> Each ETR has four ATID registers with 128 bits long in total.
> e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device.
>
> Based on the trace id which is programed in CTCU ATID register of
> specific ETR, trace data with that trace id can get into ETR's buffer
> while other trace data gets ignored. The number of CTCU ATID registers
> depends on the number of defined TMC ETR devices. For example, two TMC
> ETR devices need eight ATID registers. ETR0 with ETR0ATID0-ETR0ATID3
> and ETR1 with ETR1ATID0-ETRATID3.
>
> The significant challenge in enabling the data filter function is how
> to collect the trace ID of the source device. The introduction of
> trace_id callback function addresses this challenge. The callback function
> collects trace ID of the device and return it back. The trace ID will be
> stored in the structure called coresight_path and transmitted to helper
> and sink devices.
>
> The coresight_path structure is created to address how to transmit
> parameters needs by coresight_enable_path/coresight_disbale_path
> functions.
>
> Here is the definition of the struct coresight_path:
> /**
> * struct coresight_path - data needed by enable/disable path
> * @path: path from source to sink.
> * @trace_id: trace_id of the whole path.
> */
> struct coresight_path {
> struct list_head *path;
> u8 trace_id;
> };
>
> The atid_offset mentioned before is the offset to ATID register in CTCU
> device.
>
> Enabling the source device will configure one bit in the ATID register based
> on its trace ID.
> Disabling the source devices will reset the bit in the AITD register
> based on its trace ID.
>
> Useage:
> Enable:
> STM device with trace ID 5 and ETR0 is activated.
> Bitmap before the enablement:
> ETR0ATID0:
> 31..................543210
> ==========================
> 0000000000000000000000...0
> ==========================
>
> Bitmap after the enablement:
> 31..................543210
> ==========================
> 0000000000000...0000100000
> ==========================
>
> The bit 5 of the ETR0ATID0 register is configured to 1 when enabling the
> STM device.
>
> Disable:
> STM device with trace ID 5 and ETR0 is activated.
> Bitmap before the disablement:
> ETR0ATID0:
> 31................6543210
> =========================
> 000000000010111...0100000
> =========================
>
> Bitmap after the disablement
> ETR0ATID0:
> 31................6543210
> =========================
> 000000000010111...0000000
> =========================
>
> The bit 5 of the ETR0ATID0 register is reset to 0 when disabling the STM
> device.
>
> Sincere thanks to James Clark for providing an excellent idea to handle
> the trace_id of the path.
>
> Changes in V12:
> 1. Update the method for allocating trace_id for perf mode.
> Link to V11 - https://lore.kernel.org/linux-arm-msm/20250214024021.249655-1-quic_jiegan@quicinc.com/
>
I tested the latest change, looks good to me.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-18 10:05 ` [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver James Clark
@ 2025-02-19 0:59 ` Jie Gan
0 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-19 0:59 UTC (permalink / raw)
To: James Clark, Suzuki K Poulose
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32, Mike Leach,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
On 2/18/2025 6:05 PM, James Clark wrote:
>
>
> On 17/02/2025 9:30 am, Jie Gan wrote:
>> From: Jie Gan <jie.gan@oss.qualcomm.com>
>>
>> The Coresight TMC Control Unit(CTCU) device hosts miscellaneous
>> configuration
>> registers to control various features related to TMC ETR device.
>>
>> The CTCU device works as a helper device physically connected to the
>> TMC ETR device.
>> ---------------------------------------------------------
>> |ETR0| |ETR1|
>> . \ / .
>> . \ / .
>> . \ / .
>> . \ / .
>> ---------------------------------------------------
>> ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3
>> ---------------------------------------------------
>> Each ETR has four ATID registers with 128 bits long in total.
>> e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device.
>>
>> Based on the trace id which is programed in CTCU ATID register of
>> specific ETR, trace data with that trace id can get into ETR's buffer
>> while other trace data gets ignored. The number of CTCU ATID registers
>> depends on the number of defined TMC ETR devices. For example, two TMC
>> ETR devices need eight ATID registers. ETR0 with ETR0ATID0-ETR0ATID3
>> and ETR1 with ETR1ATID0-ETRATID3.
>>
>> The significant challenge in enabling the data filter function is how
>> to collect the trace ID of the source device. The introduction of
>> trace_id callback function addresses this challenge. The callback
>> function
>> collects trace ID of the device and return it back. The trace ID will be
>> stored in the structure called coresight_path and transmitted to helper
>> and sink devices.
>>
>> The coresight_path structure is created to address how to transmit
>> parameters needs by coresight_enable_path/coresight_disbale_path
>> functions.
>>
>> Here is the definition of the struct coresight_path:
>> /**
>> * struct coresight_path - data needed by enable/disable path
>> * @path: path from source to sink.
>> * @trace_id: trace_id of the whole path.
>> */
>> struct coresight_path {
>> struct list_head *path;
>> u8 trace_id;
>> };
>>
>> The atid_offset mentioned before is the offset to ATID register in CTCU
>> device.
>>
>> Enabling the source device will configure one bit in the ATID register
>> based
>> on its trace ID.
>> Disabling the source devices will reset the bit in the AITD register
>> based on its trace ID.
>>
>> Useage:
>> Enable:
>> STM device with trace ID 5 and ETR0 is activated.
>> Bitmap before the enablement:
>> ETR0ATID0:
>> 31..................543210
>> ==========================
>> 0000000000000000000000...0
>> ==========================
>>
>> Bitmap after the enablement:
>> 31..................543210
>> ==========================
>> 0000000000000...0000100000
>> ==========================
>>
>> The bit 5 of the ETR0ATID0 register is configured to 1 when enabling the
>> STM device.
>>
>> Disable:
>> STM device with trace ID 5 and ETR0 is activated.
>> Bitmap before the disablement:
>> ETR0ATID0:
>> 31................6543210
>> =========================
>> 000000000010111...0100000
>> =========================
>>
>> Bitmap after the disablement
>> ETR0ATID0:
>> 31................6543210
>> =========================
>> 000000000010111...0000000
>> =========================
>>
>> The bit 5 of the ETR0ATID0 register is reset to 0 when disabling the STM
>> device.
>>
>> Sincere thanks to James Clark for providing an excellent idea to handle
>> the trace_id of the path.
>>
>> Changes in V12:
>> 1. Update the method for allocating trace_id for perf mode.
>> Link to V11 - https://lore.kernel.org/linux-arm-
>> msm/20250214024021.249655-1-quic_jiegan@quicinc.com/
>>
>
> I tested the latest change, looks good to me.
>
Hi James,
Thanks for testing.
Jie
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID
2025-02-17 9:30 ` [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
@ 2025-02-20 17:34 ` Suzuki K Poulose
2025-02-21 1:23 ` Jie Gan
0 siblings, 1 reply; 22+ messages in thread
From: Suzuki K Poulose @ 2025-02-20 17:34 UTC (permalink / raw)
To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 17/02/2025 09:30, Jie Gan wrote:
> Add 'trace_id' function pointer in ops. It's responsible for
> retrieving the device's trace ID.
>
> Co-developed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: James Clark <james.clark@linaro.org>
> Reviewed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
minor nit: Given this is an optional callback, we could as well make
this a generic ops and avoid checking if it is a link/source etc. We
anyway check if the op is available before calling it.
i.e.:
struct coresight_ops {
+ int (*trace_id)(struct coresight *csdev,...);
...
};
Suzuki
> ---
> drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-dummy.c | 11 ++++++++
> .../coresight/coresight-etm3x-core.c | 1 +
> .../coresight/coresight-etm4x-core.c | 1 +
> drivers/hwtracing/coresight/coresight-stm.c | 11 ++++++++
> drivers/hwtracing/coresight/coresight-tpda.c | 11 ++++++++
> include/linux/coresight.h | 8 ++++++
> 7 files changed, 70 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 0a9380350fb5..6cad777757f3 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -23,6 +23,7 @@
> #include "coresight-etm-perf.h"
> #include "coresight-priv.h"
> #include "coresight-syscfg.h"
> +#include "coresight-trace-id.h"
>
> /*
> * Mutex used to lock all sysfs enable and disable actions and loading and
> @@ -1515,6 +1516,32 @@ void coresight_remove_driver(struct amba_driver *amba_drv,
> }
> EXPORT_SYMBOL_GPL(coresight_remove_driver);
>
> +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
> + struct coresight_device *sink)
> +{
> + int trace_id;
> + int cpu = source_ops(csdev)->cpu_id(csdev);
> +
> + switch (mode) {
> + case CS_MODE_SYSFS:
> + trace_id = coresight_trace_id_get_cpu_id(cpu);
> + break;
> + case CS_MODE_PERF:
> + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map);
> + break;
> + default:
> + trace_id = -EINVAL;
> + break;
> + }
> +
> + if (!IS_VALID_CS_TRACE_ID(trace_id))
> + dev_err(&csdev->dev,
> + "Failed to allocate trace ID on CPU%d\n", cpu);
> +
> + return trace_id;
> +}
> +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id);
> +
> MODULE_LICENSE("GPL v2");
> MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
> MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c
> index 9be53be8964b..c47f0382b943 100644
> --- a/drivers/hwtracing/coresight/coresight-dummy.c
> +++ b/drivers/hwtracing/coresight/coresight-dummy.c
> @@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev,
> dev_dbg(csdev->dev.parent, "Dummy source disabled\n");
> }
>
> +static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
> + __maybe_unused struct coresight_device *sink)
> +{
> + struct dummy_drvdata *drvdata;
> +
> + drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + return drvdata->traceid;
> +}
> +
> static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode,
> void *data)
> {
> @@ -59,6 +69,7 @@ static int dummy_sink_disable(struct coresight_device *csdev)
> static const struct coresight_ops_source dummy_source_ops = {
> .enable = dummy_source_enable,
> .disable = dummy_source_disable,
> + .trace_id = dummy_source_trace_id,
> };
>
> static const struct coresight_ops dummy_source_cs_ops = {
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> index c103f4c70f5d..a38e72ef8e79 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> @@ -701,6 +701,7 @@ static const struct coresight_ops_source etm_source_ops = {
> .cpu_id = etm_cpu_id,
> .enable = etm_enable,
> .disable = etm_disable,
> + .trace_id = coresight_etm_get_trace_id,
> };
>
> static const struct coresight_ops etm_cs_ops = {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 2c1a60577728..1a993d5380e7 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1064,6 +1064,7 @@ static const struct coresight_ops_source etm4_source_ops = {
> .cpu_id = etm4_cpu_id,
> .enable = etm4_enable,
> .disable = etm4_disable,
> + .trace_id = coresight_etm_get_trace_id,
> };
>
> static const struct coresight_ops etm4_cs_ops = {
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index b581a30a1cd9..64fcfa916562 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -281,9 +281,20 @@ static void stm_disable(struct coresight_device *csdev,
> }
> }
>
> +static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
> + __maybe_unused struct coresight_device *sink)
> +{
> + struct stm_drvdata *drvdata;
> +
> + drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + return drvdata->traceid;
> +}
> +
> static const struct coresight_ops_source stm_source_ops = {
> .enable = stm_enable,
> .disable = stm_disable,
> + .trace_id = stm_trace_id,
> };
>
> static const struct coresight_ops stm_cs_ops = {
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
> index 189a4abc2561..d80b6427e5a6 100644
> --- a/drivers/hwtracing/coresight/coresight-tpda.c
> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
> @@ -241,9 +241,20 @@ static void tpda_disable(struct coresight_device *csdev,
> dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port);
> }
>
> +static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
> + __maybe_unused struct coresight_device *sink)
> +{
> + struct tpda_drvdata *drvdata;
> +
> + drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + return drvdata->atid;
> +}
> +
> static const struct coresight_ops_link tpda_link_ops = {
> .enable = tpda_enable,
> .disable = tpda_disable,
> + .trace_id = tpda_trace_id,
> };
>
> static const struct coresight_ops tpda_cs_ops = {
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 157c4bd009a1..70407d61262e 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -368,6 +368,7 @@ struct coresight_ops_sink {
> * Operations available for links.
> * @enable: enables flow between iport and oport.
> * @disable: disables flow between iport and oport.
> + * @trace_id: alloc or read the traceid.
> */
> struct coresight_ops_link {
> int (*enable)(struct coresight_device *csdev,
> @@ -376,6 +377,8 @@ struct coresight_ops_link {
> void (*disable)(struct coresight_device *csdev,
> struct coresight_connection *in,
> struct coresight_connection *out);
> + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
> + struct coresight_device *sink);
> };
>
> /**
> @@ -385,6 +388,7 @@ struct coresight_ops_link {
> * is associated to.
> * @enable: enables tracing for a source.
> * @disable: disables tracing for a source.
> + * @trace_id: alloc or read the traceid.
> */
> struct coresight_ops_source {
> int (*cpu_id)(struct coresight_device *csdev);
> @@ -392,6 +396,8 @@ struct coresight_ops_source {
> enum cs_mode mode, struct coresight_trace_id_map *id_map);
> void (*disable)(struct coresight_device *csdev,
> struct perf_event *event);
> + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
> + struct coresight_device *sink);
> };
>
> /**
> @@ -697,4 +703,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv,
>
> void coresight_remove_driver(struct amba_driver *amba_drv,
> struct platform_driver *pdev_drv);
> +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
> + struct coresight_device *sink);
> #endif /* _LINUX_COREISGHT_H */
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID
2025-02-20 17:34 ` Suzuki K Poulose
@ 2025-02-21 1:23 ` Jie Gan
0 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-21 1:23 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 2/21/2025 1:34 AM, Suzuki K Poulose wrote:
> On 17/02/2025 09:30, Jie Gan wrote:
>> Add 'trace_id' function pointer in ops. It's responsible for
>> retrieving the device's trace ID.
>>
>> Co-developed-by: James Clark <james.clark@linaro.org>
>> Signed-off-by: James Clark <james.clark@linaro.org>
>> Reviewed-by: James Clark <james.clark@linaro.org>
>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>
>
> minor nit: Given this is an optional callback, we could as well make
> this a generic ops and avoid checking if it is a link/source etc. We
> anyway check if the op is available before calling it.
>
> i.e.:
>
> struct coresight_ops {
> + int (*trace_id)(struct coresight *csdev,...);
>
> ...
> };
>
Hi Suzuki,
Thanks for comment. Looks a good idea because the trace_id is a generic
function for the coresight_deivce, which can simplify our codes.
Will update a new version to acheive the idea.
Thanks,
Jie
>
>
>
>> ---
>> drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-dummy.c | 11 ++++++++
>> .../coresight/coresight-etm3x-core.c | 1 +
>> .../coresight/coresight-etm4x-core.c | 1 +
>> drivers/hwtracing/coresight/coresight-stm.c | 11 ++++++++
>> drivers/hwtracing/coresight/coresight-tpda.c | 11 ++++++++
>> include/linux/coresight.h | 8 ++++++
>> 7 files changed, 70 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/
>> hwtracing/coresight/coresight-core.c
>> index 0a9380350fb5..6cad777757f3 100644
>> --- a/drivers/hwtracing/coresight/coresight-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-core.c
>> @@ -23,6 +23,7 @@
>> #include "coresight-etm-perf.h"
>> #include "coresight-priv.h"
>> #include "coresight-syscfg.h"
>> +#include "coresight-trace-id.h"
>> /*
>> * Mutex used to lock all sysfs enable and disable actions and
>> loading and
>> @@ -1515,6 +1516,32 @@ void coresight_remove_driver(struct amba_driver
>> *amba_drv,
>> }
>> EXPORT_SYMBOL_GPL(coresight_remove_driver);
>> +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum
>> cs_mode mode,
>> + struct coresight_device *sink)
>> +{
>> + int trace_id;
>> + int cpu = source_ops(csdev)->cpu_id(csdev);
>> +
>> + switch (mode) {
>> + case CS_MODE_SYSFS:
>> + trace_id = coresight_trace_id_get_cpu_id(cpu);
>> + break;
>> + case CS_MODE_PERF:
>> + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink-
>> >perf_sink_id_map);
>> + break;
>> + default:
>> + trace_id = -EINVAL;
>> + break;
>> + }
>> +
>> + if (!IS_VALID_CS_TRACE_ID(trace_id))
>> + dev_err(&csdev->dev,
>> + "Failed to allocate trace ID on CPU%d\n", cpu);
>> +
>> + return trace_id;
>> +}
>> +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id);
>> +
>> MODULE_LICENSE("GPL v2");
>> MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
>> MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
>> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/
>> hwtracing/coresight/coresight-dummy.c
>> index 9be53be8964b..c47f0382b943 100644
>> --- a/drivers/hwtracing/coresight/coresight-dummy.c
>> +++ b/drivers/hwtracing/coresight/coresight-dummy.c
>> @@ -41,6 +41,16 @@ static void dummy_source_disable(struct
>> coresight_device *csdev,
>> dev_dbg(csdev->dev.parent, "Dummy source disabled\n");
>> }
>> +static int dummy_source_trace_id(struct coresight_device *csdev,
>> __maybe_unused enum cs_mode mode,
>> + __maybe_unused struct coresight_device *sink)
>> +{
>> + struct dummy_drvdata *drvdata;
>> +
>> + drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> + return drvdata->traceid;
>> +}
>> +
>> static int dummy_sink_enable(struct coresight_device *csdev, enum
>> cs_mode mode,
>> void *data)
>> {
>> @@ -59,6 +69,7 @@ static int dummy_sink_disable(struct
>> coresight_device *csdev)
>> static const struct coresight_ops_source dummy_source_ops = {
>> .enable = dummy_source_enable,
>> .disable = dummy_source_disable,
>> + .trace_id = dummy_source_trace_id,
>> };
>> static const struct coresight_ops dummy_source_cs_ops = {
>> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/
>> drivers/hwtracing/coresight/coresight-etm3x-core.c
>> index c103f4c70f5d..a38e72ef8e79 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
>> @@ -701,6 +701,7 @@ static const struct coresight_ops_source
>> etm_source_ops = {
>> .cpu_id = etm_cpu_id,
>> .enable = etm_enable,
>> .disable = etm_disable,
>> + .trace_id = coresight_etm_get_trace_id,
>> };
>> static const struct coresight_ops etm_cs_ops = {
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/
>> drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index 2c1a60577728..1a993d5380e7 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -1064,6 +1064,7 @@ static const struct coresight_ops_source
>> etm4_source_ops = {
>> .cpu_id = etm4_cpu_id,
>> .enable = etm4_enable,
>> .disable = etm4_disable,
>> + .trace_id = coresight_etm_get_trace_id,
>> };
>> static const struct coresight_ops etm4_cs_ops = {
>> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/
>> hwtracing/coresight/coresight-stm.c
>> index b581a30a1cd9..64fcfa916562 100644
>> --- a/drivers/hwtracing/coresight/coresight-stm.c
>> +++ b/drivers/hwtracing/coresight/coresight-stm.c
>> @@ -281,9 +281,20 @@ static void stm_disable(struct coresight_device
>> *csdev,
>> }
>> }
>> +static int stm_trace_id(struct coresight_device *csdev,
>> __maybe_unused enum cs_mode mode,
>> + __maybe_unused struct coresight_device *sink)
>> +{
>> + struct stm_drvdata *drvdata;
>> +
>> + drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> + return drvdata->traceid;
>> +}
>> +
>> static const struct coresight_ops_source stm_source_ops = {
>> .enable = stm_enable,
>> .disable = stm_disable,
>> + .trace_id = stm_trace_id,
>> };
>> static const struct coresight_ops stm_cs_ops = {
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/
>> hwtracing/coresight/coresight-tpda.c
>> index 189a4abc2561..d80b6427e5a6 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>> @@ -241,9 +241,20 @@ static void tpda_disable(struct coresight_device
>> *csdev,
>> dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port);
>> }
>> +static int tpda_trace_id(struct coresight_device *csdev,
>> __maybe_unused enum cs_mode mode,
>> + __maybe_unused struct coresight_device *sink)
>> +{
>> + struct tpda_drvdata *drvdata;
>> +
>> + drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> + return drvdata->atid;
>> +}
>> +
>> static const struct coresight_ops_link tpda_link_ops = {
>> .enable = tpda_enable,
>> .disable = tpda_disable,
>> + .trace_id = tpda_trace_id,
>> };
>> static const struct coresight_ops tpda_cs_ops = {
>> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
>> index 157c4bd009a1..70407d61262e 100644
>> --- a/include/linux/coresight.h
>> +++ b/include/linux/coresight.h
>> @@ -368,6 +368,7 @@ struct coresight_ops_sink {
>> * Operations available for links.
>> * @enable: enables flow between iport and oport.
>> * @disable: disables flow between iport and oport.
>> + * @trace_id: alloc or read the traceid.
>> */
>> struct coresight_ops_link {
>> int (*enable)(struct coresight_device *csdev,
>> @@ -376,6 +377,8 @@ struct coresight_ops_link {
>> void (*disable)(struct coresight_device *csdev,
>> struct coresight_connection *in,
>> struct coresight_connection *out);
>> + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
>> + struct coresight_device *sink);
>> };
>> /**
>> @@ -385,6 +388,7 @@ struct coresight_ops_link {
>> * is associated to.
>> * @enable: enables tracing for a source.
>> * @disable: disables tracing for a source.
>> + * @trace_id: alloc or read the traceid.
>> */
>> struct coresight_ops_source {
>> int (*cpu_id)(struct coresight_device *csdev);
>> @@ -392,6 +396,8 @@ struct coresight_ops_source {
>> enum cs_mode mode, struct coresight_trace_id_map
>> *id_map);
>> void (*disable)(struct coresight_device *csdev,
>> struct perf_event *event);
>> + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
>> + struct coresight_device *sink);
>> };
>> /**
>> @@ -697,4 +703,6 @@ int coresight_init_driver(const char *drv, struct
>> amba_driver *amba_drv,
>> void coresight_remove_driver(struct amba_driver *amba_drv,
>> struct platform_driver *pdev_drv);
>> +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum
>> cs_mode mode,
>> + struct coresight_device *sink);
>> #endif /* _LINUX_COREISGHT_H */
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path
2025-02-17 9:30 ` [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path Jie Gan
@ 2025-02-21 10:30 ` Suzuki K Poulose
2025-02-24 2:35 ` Jie Gan
0 siblings, 1 reply; 22+ messages in thread
From: Suzuki K Poulose @ 2025-02-21 10:30 UTC (permalink / raw)
To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 17/02/2025 09:30, Jie Gan wrote:
> Add 'struct coresight_path' to store the data that is needed by
> coresight_enable_path/coresight_disable_path. The structure will be
> transmitted to any required devices to enable related funcationalities.
>
> The trace_id will be allocated after the path is built. Consequently,
> The ETM3x and ETM4x devices will directly read the trace_id from path
> which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id
> being deleted.
>
> Co-developed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: James Clark <james.clark@linaro.org>
> Reviewed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
> ---
Personally, I find this patch doing 3 things in one shot, which is
complicated TBH for the patch review.
1. Introduce coresight_path
2. Move trace-id to coresight_path and allocate it after building the path.
3. Change enable/disable to accept the "coresight_path"
Please do not repeat this in the future, split them accordingly. At the
least we could split this patch into 1 and 2+3
> drivers/hwtracing/coresight/coresight-core.c | 106 +++++++++++++-----
> drivers/hwtracing/coresight/coresight-dummy.c | 5 +-
> .../hwtracing/coresight/coresight-etm-perf.c | 24 ++--
> .../hwtracing/coresight/coresight-etm-perf.h | 2 +-
> drivers/hwtracing/coresight/coresight-etm.h | 1 -
> .../coresight/coresight-etm3x-core.c | 54 ++-------
> .../coresight/coresight-etm4x-core.c | 54 ++-------
> drivers/hwtracing/coresight/coresight-etm4x.h | 1 -
> drivers/hwtracing/coresight/coresight-priv.h | 12 +-
> drivers/hwtracing/coresight/coresight-stm.c | 3 +-
> drivers/hwtracing/coresight/coresight-sysfs.c | 17 ++-
> drivers/hwtracing/coresight/coresight-tpdm.c | 3 +-
> include/linux/coresight.h | 12 +-
> 13 files changed, 140 insertions(+), 154 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 6cad777757f3..182bfa2420cc 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -76,14 +76,14 @@ struct coresight_device *coresight_get_percpu_sink(int cpu)
> }
> EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);
>
> -static struct coresight_device *coresight_get_source(struct list_head *path)
> +static struct coresight_device *coresight_get_source(struct coresight_path *path)
> {
> struct coresight_device *csdev;
>
> if (!path)
> return NULL;
>
> - csdev = list_first_entry(path, struct coresight_node, link)->csdev;
> + csdev = list_first_entry(path->path_list, struct coresight_node, link)->csdev;
> if (!coresight_is_device_source(csdev))
> return NULL;
>
> @@ -332,12 +332,12 @@ static int coresight_enable_helper(struct coresight_device *csdev,
> return helper_ops(csdev)->enable(csdev, mode, data);
> }
>
> -static void coresight_disable_helper(struct coresight_device *csdev)
> +static void coresight_disable_helper(struct coresight_device *csdev, void *data)
> {
> - helper_ops(csdev)->disable(csdev, NULL);
> + helper_ops(csdev)->disable(csdev, data);
> }
>
> -static void coresight_disable_helpers(struct coresight_device *csdev)
> +static void coresight_disable_helpers(struct coresight_device *csdev, void *data)
> {
> int i;
> struct coresight_device *helper;
> @@ -345,7 +345,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev)
> for (i = 0; i < csdev->pdata->nr_outconns; ++i) {
> helper = csdev->pdata->out_conns[i]->dest_dev;
> if (helper && coresight_is_helper(helper))
> - coresight_disable_helper(helper);
> + coresight_disable_helper(helper, data);
> }
> }
>
> @@ -362,7 +362,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev)
> void coresight_disable_source(struct coresight_device *csdev, void *data)
> {
> source_ops(csdev)->disable(csdev, data);
> - coresight_disable_helpers(csdev);
> + coresight_disable_helpers(csdev, NULL);
> }
> EXPORT_SYMBOL_GPL(coresight_disable_source);
>
> @@ -371,16 +371,16 @@ EXPORT_SYMBOL_GPL(coresight_disable_source);
> * @nd in the list. If @nd is NULL, all the components, except the SOURCE are
> * disabled.
> */
> -static void coresight_disable_path_from(struct list_head *path,
> +static void coresight_disable_path_from(struct coresight_path *path,
> struct coresight_node *nd)
> {
> u32 type;
> struct coresight_device *csdev, *parent, *child;
>
> if (!nd)
> - nd = list_first_entry(path, struct coresight_node, link);
> + nd = list_first_entry(path->path_list, struct coresight_node, link);
>
> - list_for_each_entry_continue(nd, path, link) {
> + list_for_each_entry_continue(nd, path->path_list, link) {
> csdev = nd->csdev;
> type = csdev->type;
>
> @@ -418,11 +418,11 @@ static void coresight_disable_path_from(struct list_head *path,
> }
>
> /* Disable all helpers adjacent along the path last */
> - coresight_disable_helpers(csdev);
> + coresight_disable_helpers(csdev, path);
> }
> }
>
> -void coresight_disable_path(struct list_head *path)
> +void coresight_disable_path(struct coresight_path *path)
> {
> coresight_disable_path_from(path, NULL);
> }
> @@ -447,7 +447,7 @@ static int coresight_enable_helpers(struct coresight_device *csdev,
> return 0;
> }
>
> -int coresight_enable_path(struct list_head *path, enum cs_mode mode,
> +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode,
> void *sink_data)
> {
> int ret = 0;
> @@ -457,12 +457,12 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode,
> struct coresight_device *source;
>
> source = coresight_get_source(path);
> - list_for_each_entry_reverse(nd, path, link) {
> + list_for_each_entry_reverse(nd, path->path_list, link) {
> csdev = nd->csdev;
> type = csdev->type;
>
> /* Enable all helpers adjacent to the path first */
> - ret = coresight_enable_helpers(csdev, mode, sink_data);
> + ret = coresight_enable_helpers(csdev, mode, path);
> if (ret)
> goto err;
> /*
> @@ -510,20 +510,21 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode,
> goto out;
> }
>
> -struct coresight_device *coresight_get_sink(struct list_head *path)
> +struct coresight_device *coresight_get_sink(struct coresight_path *path)
> {
> struct coresight_device *csdev;
>
> if (!path)
> return NULL;
>
> - csdev = list_last_entry(path, struct coresight_node, link)->csdev;
> + csdev = list_last_entry(path->path_list, struct coresight_node, link)->csdev;
> if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
> csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
> return NULL;
>
> return csdev;
> }
> +EXPORT_SYMBOL_GPL(coresight_get_sink);
>
> u32 coresight_get_sink_id(struct coresight_device *csdev)
> {
> @@ -654,6 +655,51 @@ static void coresight_drop_device(struct coresight_device *csdev)
> }
> }
>
> +/*
> + * Links or sources will read their existing or alloc a trace ID, if their ID
> + * callback is set.
> + */
Please could we document the return value conditions here ?
> +static int coresight_get_trace_id(struct coresight_device *csdev,
> + enum cs_mode mode,
> + struct coresight_device *sink)
> +{
> + if (csdev->type == CORESIGHT_DEV_TYPE_LINK && link_ops(csdev)->trace_id)
> + return link_ops(csdev)->trace_id(csdev, mode, sink);
> +
> + if (csdev->type == CORESIGHT_DEV_TYPE_SOURCE && source_ops(csdev)->trace_id)
> + return source_ops(csdev)->trace_id(csdev, mode, sink);
> +
> + return 0;
> +}
> +
> +/*
> + * Call this after creating the path and before enabling it. This leaves
> + * the trace ID set on the path and returns the ID, or an error if it
> + * couldn't be assigned.
> + */
> +int coresight_path_assign_trace_id(struct coresight_path *path,
> + enum cs_mode mode)
> +{
> + struct coresight_device *sink = coresight_get_sink(path);
> + struct coresight_node *nd;
> + int ret;
Might be better to rename this as "trace_id" ? As we return the trace id
not a status of whether it was allocated or not. Or drop it completely
and return path->trace_id, below when we succeed. Or it could even
be a void, as the caller can check IS_VALID(path->trace_id)
> +
> + list_for_each_entry(nd, path->path_list, link) {
> + /* Assign a trace ID to the path for the first device that wants to do it */
> + ret = coresight_get_trace_id(nd->csdev, mode, sink);
> +
> + /*
> + * 0 in this context is that it didn't want to assign so keep searching.
> + * Non 0 is either success or fail, return it either way.
> + */
> + if (ret != 0) {
> + path->trace_id = ret;
> + return ret;
> + }
> + }
> + return 0;
> +}
> +
> /**
> * _coresight_build_path - recursively build a path from a @csdev to a sink.
> * @csdev: The device to start from.
> @@ -669,7 +715,7 @@ static void coresight_drop_device(struct coresight_device *csdev)
> static int _coresight_build_path(struct coresight_device *csdev,
> struct coresight_device *source,
> struct coresight_device *sink,
> - struct list_head *path)
> + struct coresight_path *path)
> {
> int i, ret;
> bool found = false;
> @@ -722,28 +768,37 @@ static int _coresight_build_path(struct coresight_device *csdev,
> return -ENOMEM;
>
> node->csdev = csdev;
> - list_add(&node->link, path);
> + list_add(&node->link, path->path_list);
>
> return 0;
> }
>
> -struct list_head *coresight_build_path(struct coresight_device *source,
> +struct coresight_path *coresight_build_path(struct coresight_device *source,
> struct coresight_device *sink)
> {
> - struct list_head *path;
> + struct coresight_path *path;
> + struct list_head *path_list;
> int rc;
>
> if (!sink)
> return ERR_PTR(-EINVAL);
>
> - path = kzalloc(sizeof(struct list_head), GFP_KERNEL);
> + path = kzalloc(sizeof(struct coresight_path), GFP_KERNEL);
> if (!path)
> return ERR_PTR(-ENOMEM);
>
> - INIT_LIST_HEAD(path);
> + path_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
> + if (!path_list) {
> + kfree(path);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + INIT_LIST_HEAD(path_list);
> + path->path_list = path_list;
>
> rc = _coresight_build_path(source, source, sink, path);
> if (rc) {
> + kfree(path_list);
> kfree(path);
> return ERR_PTR(rc);
> }
> @@ -758,12 +813,12 @@ struct list_head *coresight_build_path(struct coresight_device *source,
> * Go through all the elements of a path and 1) removed it from the list and
> * 2) free the memory allocated for each node.
> */
> -void coresight_release_path(struct list_head *path)
> +void coresight_release_path(struct coresight_path *path)
> {
> struct coresight_device *csdev;
> struct coresight_node *nd, *next;
>
> - list_for_each_entry_safe(nd, next, path, link) {
> + list_for_each_entry_safe(nd, next, path->path_list, link) {
> csdev = nd->csdev;
>
> coresight_drop_device(csdev);
> @@ -771,6 +826,7 @@ void coresight_release_path(struct list_head *path)
> kfree(nd);
> }
>
> + kfree(path->path_list);
> kfree(path);
> }
>
> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c
> index c47f0382b943..d9a811d44885 100644
> --- a/drivers/hwtracing/coresight/coresight-dummy.c
> +++ b/drivers/hwtracing/coresight/coresight-dummy.c
> @@ -22,9 +22,8 @@ struct dummy_drvdata {
> DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source");
> DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink");
>
> -static int dummy_source_enable(struct coresight_device *csdev,
> - struct perf_event *event, enum cs_mode mode,
> - __maybe_unused struct coresight_trace_id_map *id_map)
> +static int dummy_source_enable(struct coresight_device *csdev, struct perf_event *event,
> + enum cs_mode mode, struct coresight_path *path)
> {
> if (!coresight_take_mode(csdev, mode))
> return -EBUSY;
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index ad6a8f4b70b6..ebdcf56b7463 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -136,13 +136,13 @@ static const struct attribute_group *etm_pmu_attr_groups[] = {
> NULL,
> };
>
> -static inline struct list_head **
> +static inline struct coresight_path **
> etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu)
> {
> return per_cpu_ptr(data->path, cpu);
> }
>
> -static inline struct list_head *
> +static inline struct coresight_path *
> etm_event_cpu_path(struct etm_event_data *data, int cpu)
> {
> return *etm_event_cpu_path_ptr(data, cpu);
> @@ -226,7 +226,7 @@ static void free_event_data(struct work_struct *work)
> cscfg_deactivate_config(event_data->cfg_hash);
>
> for_each_cpu(cpu, mask) {
> - struct list_head **ppath;
> + struct coresight_path **ppath;
>
> ppath = etm_event_cpu_path_ptr(event_data, cpu);
> if (!(IS_ERR_OR_NULL(*ppath))) {
> @@ -276,7 +276,7 @@ static void *alloc_event_data(int cpu)
> * unused memory when dealing with single CPU trace scenarios is small
> * compared to the cost of searching through an optimized array.
> */
> - event_data->path = alloc_percpu(struct list_head *);
> + event_data->path = alloc_percpu(struct coresight_path *);
>
> if (!event_data->path) {
> kfree(event_data);
> @@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> * CPUs, we can handle it and fail the session.
> */
> for_each_cpu(cpu, mask) {
> - struct list_head *path;
> + struct coresight_path *path;
> struct coresight_device *csdev;
>
> csdev = per_cpu(csdev_src, cpu);
> @@ -407,7 +407,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> }
>
> /* ensure we can allocate a trace ID for this CPU */
> - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map);
> + trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF);
> if (!IS_VALID_CS_TRACE_ID(trace_id)) {
> cpumask_clear_cpu(cpu, mask);
> coresight_release_path(path);
> @@ -458,9 +458,8 @@ static void etm_event_start(struct perf_event *event, int flags)
> struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> struct perf_output_handle *handle = &ctxt->handle;
> struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
> - struct list_head *path;
> + struct coresight_path *path;
> u64 hw_id;
> - u8 trace_id;
>
> if (!csdev)
> goto fail;
> @@ -503,8 +502,7 @@ static void etm_event_start(struct perf_event *event, int flags)
> goto fail_end_stop;
>
> /* Finally enable the tracer */
> - if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF,
> - &sink->perf_sink_id_map))
> + if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, path))
> goto fail_disable_path;
>
> /*
> @@ -514,13 +512,11 @@ static void etm_event_start(struct perf_event *event, int flags)
> if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) {
> cpumask_set_cpu(cpu, &event_data->aux_hwid_done);
>
> - trace_id = coresight_trace_id_read_cpu_id_map(cpu, &sink->perf_sink_id_map);
> -
> hw_id = FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK,
> CS_AUX_HW_ID_MAJOR_VERSION);
> hw_id |= FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK,
> CS_AUX_HW_ID_MINOR_VERSION);
> - hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, trace_id);
> + hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, path->trace_id);
> hw_id |= FIELD_PREP(CS_AUX_HW_ID_SINK_ID_MASK, coresight_get_sink_id(sink));
>
> perf_report_aux_output_id(event, hw_id);
> @@ -558,7 +554,7 @@ static void etm_event_stop(struct perf_event *event, int mode)
> struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> struct perf_output_handle *handle = &ctxt->handle;
> struct etm_event_data *event_data;
> - struct list_head *path;
> + struct coresight_path *path;
>
> /*
> * If we still have access to the event_data via handle,
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h
> index 744531158d6b..5febbcdb8696 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.h
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
> @@ -59,7 +59,7 @@ struct etm_event_data {
> cpumask_t aux_hwid_done;
> void *snk_config;
> u32 cfg_hash;
> - struct list_head * __percpu *path;
> + struct coresight_path * __percpu *path;
> };
>
> int etm_perf_symlink(struct coresight_device *csdev, bool link);
> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
> index e02c3ea972c9..171f1384f7c0 100644
> --- a/drivers/hwtracing/coresight/coresight-etm.h
> +++ b/drivers/hwtracing/coresight/coresight-etm.h
> @@ -284,6 +284,5 @@ extern const struct attribute_group *coresight_etm_groups[];
> void etm_set_default(struct etm_config *config);
> void etm_config_trace_mode(struct etm_config *config);
> struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
> -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata);
> void etm_release_trace_id(struct etm_drvdata *drvdata);
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> index a38e72ef8e79..cb8a30a3b48e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> @@ -455,26 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev)
> return drvdata->cpu;
> }
>
> -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata)
> -{
> - int trace_id;
> -
> - /*
> - * This will allocate a trace ID to the cpu,
> - * or return the one currently allocated.
> - *
> - * trace id function has its own lock
> - */
> - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
> - if (IS_VALID_CS_TRACE_ID(trace_id))
> - drvdata->traceid = (u8)trace_id;
> - else
> - dev_err(&drvdata->csdev->dev,
> - "Failed to allocate trace ID for %s on CPU%d\n",
> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
> - return trace_id;
> -}
> -
> void etm_release_trace_id(struct etm_drvdata *drvdata)
> {
> coresight_trace_id_put_cpu_id(drvdata->cpu);
> @@ -482,38 +462,22 @@ void etm_release_trace_id(struct etm_drvdata *drvdata)
>
> static int etm_enable_perf(struct coresight_device *csdev,
> struct perf_event *event,
> - struct coresight_trace_id_map *id_map)
> + struct coresight_path *path)
> {
> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> - int trace_id;
>
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> return -EINVAL;
>
> /* Configure the tracer based on the session's specifics */
> etm_parse_event_config(drvdata, event);
> -
> - /*
> - * perf allocates cpu ids as part of _setup_aux() - device needs to use
> - * the allocated ID. This reads the current version without allocation.
> - *
> - * This does not use the trace id lock to prevent lock_dep issues
> - * with perf locks - we know the ID cannot change until perf shuts down
> - * the session
> - */
> - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
> - if (!IS_VALID_CS_TRACE_ID(trace_id)) {
> - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
> - return -EINVAL;
> - }
> - drvdata->traceid = (u8)trace_id;
> + drvdata->traceid = path->trace_id;
>
> /* And enable it */
> return etm_enable_hw(drvdata);
> }
>
> -static int etm_enable_sysfs(struct coresight_device *csdev)
> +static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
> {
> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> struct etm_enable_arg arg = { };
> @@ -521,10 +485,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
>
> spin_lock(&drvdata->spinlock);
>
> - /* sysfs needs to allocate and set a trace ID */
> - ret = etm_read_alloc_trace_id(drvdata);
> - if (ret < 0)
> - goto unlock_enable_sysfs;
> + drvdata->traceid = path->trace_id;
>
> /*
> * Configure the ETM only if the CPU is online. If it isn't online
> @@ -545,7 +506,6 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
> if (ret)
> etm_release_trace_id(drvdata);
>
> -unlock_enable_sysfs:
> spin_unlock(&drvdata->spinlock);
>
> if (!ret)
> @@ -554,7 +514,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
> }
>
> static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
> - enum cs_mode mode, struct coresight_trace_id_map *id_map)
> + enum cs_mode mode, struct coresight_path *path)
> {
> int ret;
> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> @@ -566,10 +526,10 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
>
> switch (mode) {
> case CS_MODE_SYSFS:
> - ret = etm_enable_sysfs(csdev);
> + ret = etm_enable_sysfs(csdev, path);
> break;
> case CS_MODE_PERF:
> - ret = etm_enable_perf(csdev, event, id_map);
> + ret = etm_enable_perf(csdev, event, path);
> break;
> default:
> ret = -EINVAL;
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 1a993d5380e7..3d0fc25085ea 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -233,25 +233,6 @@ static int etm4_cpu_id(struct coresight_device *csdev)
> return drvdata->cpu;
> }
>
> -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
> -{
> - int trace_id;
> -
> - /*
> - * This will allocate a trace ID to the cpu,
> - * or return the one currently allocated.
> - * The trace id function has its own lock
> - */
> - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
> - if (IS_VALID_CS_TRACE_ID(trace_id))
> - drvdata->trcid = (u8)trace_id;
> - else
> - dev_err(&drvdata->csdev->dev,
> - "Failed to allocate trace ID for %s on CPU%d\n",
> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
> - return trace_id;
> -}
> -
> void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
> {
> coresight_trace_id_put_cpu_id(drvdata->cpu);
> @@ -788,9 +769,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>
> static int etm4_enable_perf(struct coresight_device *csdev,
> struct perf_event *event,
> - struct coresight_trace_id_map *id_map)
> + struct coresight_path *path)
> {
> - int ret = 0, trace_id;
> + int ret = 0;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
> @@ -803,22 +784,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> if (ret)
> goto out;
>
> - /*
> - * perf allocates cpu ids as part of _setup_aux() - device needs to use
> - * the allocated ID. This reads the current version without allocation.
> - *
> - * This does not use the trace id lock to prevent lock_dep issues
> - * with perf locks - we know the ID cannot change until perf shuts down
> - * the session
> - */
> - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
> - if (!IS_VALID_CS_TRACE_ID(trace_id)) {
> - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
> - ret = -EINVAL;
> - goto out;
> - }
> - drvdata->trcid = (u8)trace_id;
> + drvdata->trcid = path->trace_id;
>
> /* And enable it */
> ret = etm4_enable_hw(drvdata);
> @@ -827,7 +793,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> return ret;
> }
>
> -static int etm4_enable_sysfs(struct coresight_device *csdev)
> +static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
> {
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> struct etm4_enable_arg arg = { };
> @@ -844,10 +810,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
>
> spin_lock(&drvdata->spinlock);
>
> - /* sysfs needs to read and allocate a trace ID */
> - ret = etm4_read_alloc_trace_id(drvdata);
> - if (ret < 0)
> - goto unlock_sysfs_enable;
> + drvdata->trcid = path->trace_id;
>
> /*
> * Executing etm4_enable_hw on the cpu whose ETM is being enabled
> @@ -864,7 +827,6 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
> if (ret)
> etm4_release_trace_id(drvdata);
>
> -unlock_sysfs_enable:
> spin_unlock(&drvdata->spinlock);
>
> if (!ret)
> @@ -873,7 +835,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
> }
>
> static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
> - enum cs_mode mode, struct coresight_trace_id_map *id_map)
> + enum cs_mode mode, struct coresight_path *path)
> {
> int ret;
>
> @@ -884,10 +846,10 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
>
> switch (mode) {
> case CS_MODE_SYSFS:
> - ret = etm4_enable_sysfs(csdev);
> + ret = etm4_enable_sysfs(csdev, path);
> break;
> case CS_MODE_PERF:
> - ret = etm4_enable_perf(csdev, event, id_map);
> + ret = etm4_enable_perf(csdev, event, path);
> break;
> default:
> ret = -EINVAL;
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 1119762b5cec..2b92de17b5a2 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -1066,6 +1066,5 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
> return drvdata->arch >= ETM_ARCH_ETE;
> }
>
> -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata);
> void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index 76403530f33e..c10dd3643854 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -132,16 +132,16 @@ static inline void CS_UNLOCK(void __iomem *addr)
> } while (0);
> }
>
> -void coresight_disable_path(struct list_head *path);
> -int coresight_enable_path(struct list_head *path, enum cs_mode mode,
> +void coresight_disable_path(struct coresight_path *path);
> +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode,
> void *sink_data);
> -struct coresight_device *coresight_get_sink(struct list_head *path);
> +struct coresight_device *coresight_get_sink(struct coresight_path *path);
> struct coresight_device *coresight_get_sink_by_id(u32 id);
> struct coresight_device *
> coresight_find_default_sink(struct coresight_device *csdev);
> -struct list_head *coresight_build_path(struct coresight_device *csdev,
> +struct coresight_path *coresight_build_path(struct coresight_device *csdev,
> struct coresight_device *sink);
> -void coresight_release_path(struct list_head *path);
> +void coresight_release_path(struct coresight_path *path);
> int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
> void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
> int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
> @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig,
> void coresight_remove_links(struct coresight_device *orig,
> struct coresight_connection *conn);
> u32 coresight_get_sink_id(struct coresight_device *csdev);
> +int coresight_path_assign_trace_id(struct coresight_path *path,
> + enum cs_mode mode);
>
> #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
> extern int etm_readl_cp14(u32 off, unsigned int *val);
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index 64fcfa916562..0d4a9d325df4 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -194,8 +194,7 @@ static void stm_enable_hw(struct stm_drvdata *drvdata)
> }
>
> static int stm_enable(struct coresight_device *csdev, struct perf_event *event,
> - enum cs_mode mode,
> - __maybe_unused struct coresight_trace_id_map *trace_id)
> + enum cs_mode mode, struct coresight_path *path)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>
> diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c
> index a01c9e54e2ed..c2b0a1f59d1a 100644
> --- a/drivers/hwtracing/coresight/coresight-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-sysfs.c
> @@ -22,7 +22,7 @@ static DEFINE_IDR(path_idr);
> * When operating Coresight drivers from the sysFS interface, only a single
> * path can exist from a tracer (associated to a CPU) to a sink.
> */
> -static DEFINE_PER_CPU(struct list_head *, tracer_path);
> +static DEFINE_PER_CPU(struct coresight_path *, tracer_path);
>
> ssize_t coresight_simple_show_pair(struct device *_dev,
> struct device_attribute *attr, char *buf)
> @@ -53,7 +53,8 @@ ssize_t coresight_simple_show32(struct device *_dev,
> EXPORT_SYMBOL_GPL(coresight_simple_show32);
>
> static int coresight_enable_source_sysfs(struct coresight_device *csdev,
> - enum cs_mode mode, void *data)
> + enum cs_mode mode,
> + struct coresight_path *path)
> {
> int ret;
>
> @@ -64,7 +65,7 @@ static int coresight_enable_source_sysfs(struct coresight_device *csdev,
> */
> lockdep_assert_held(&coresight_mutex);
> if (coresight_get_mode(csdev) != CS_MODE_SYSFS) {
> - ret = source_ops(csdev)->enable(csdev, data, mode, NULL);
> + ret = source_ops(csdev)->enable(csdev, NULL, mode, path);
> if (ret)
> return ret;
> }
> @@ -167,7 +168,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev)
> {
> int cpu, ret = 0;
> struct coresight_device *sink;
> - struct list_head *path;
> + struct coresight_path *path;
> enum coresight_dev_subtype_source subtype;
> u32 hash;
>
> @@ -209,11 +210,15 @@ int coresight_enable_sysfs(struct coresight_device *csdev)
> goto out;
> }
>
> + ret = coresight_path_assign_trace_id(path, CS_MODE_SYSFS);
> + if (ret < 0)
> + goto err_path;
> +
> ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL);
> if (ret)
> goto err_path;
>
> - ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, NULL);
> + ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, path);
> if (ret)
> goto err_source;
>
> @@ -262,7 +267,7 @@ EXPORT_SYMBOL_GPL(coresight_enable_sysfs);
> void coresight_disable_sysfs(struct coresight_device *csdev)
> {
> int cpu, ret;
> - struct list_head *path = NULL;
> + struct coresight_path *path = NULL;
> u32 hash;
>
> mutex_lock(&coresight_mutex);
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index c38f9701665e..f0880a62028f 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -439,8 +439,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata)
> }
>
> static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event,
> - enum cs_mode mode,
> - __maybe_unused struct coresight_trace_id_map *id_map)
> + enum cs_mode mode, struct coresight_path *path)
> {
> struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 70407d61262e..03d833a15726 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -329,6 +329,16 @@ static struct coresight_dev_list (var) = { \
>
> #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
>
> +/**
> + * struct coresight_path - data needed by enable/disable path
> + * @path: path from source to sink.
> + * @trace_id: trace_id of the whole path.
> + */
> +struct coresight_path {
> + struct list_head *path_list;
Minor nit: We could do
struct list_head path_list;
to avoid allocating/freeing the head node without multiple
kzalloc/kfree
Suzuki
> + u8 trace_id;
> +};
> +
> enum cs_mode {
> CS_MODE_DISABLED,
> CS_MODE_SYSFS,
> @@ -393,7 +403,7 @@ struct coresight_ops_link {
> struct coresight_ops_source {
> int (*cpu_id)(struct coresight_device *csdev);
> int (*enable)(struct coresight_device *csdev, struct perf_event *event,
> - enum cs_mode mode, struct coresight_trace_id_map *id_map);
> + enum cs_mode mode, struct coresight_path *path);
> void (*disable)(struct coresight_device *csdev,
> struct perf_event *event);
> int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-17 9:30 ` [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
@ 2025-02-21 11:39 ` Suzuki K Poulose
2025-02-24 3:32 ` Jie Gan
0 siblings, 1 reply; 22+ messages in thread
From: Suzuki K Poulose @ 2025-02-21 11:39 UTC (permalink / raw)
To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 17/02/2025 09:30, Jie Gan wrote:
> The Coresight TMC Control Unit hosts miscellaneous configuration registers
> which control various features related to TMC ETR sink.
>
> Based on the trace ID, which is programmed in the related CTCU ATID
> register of a specific ETR, trace data with that trace ID gets into
> the ETR buffer, while other trace data gets dropped.
>
> Enabling source device sets one bit of the ATID register based on
> source device's trace ID.
> Disabling source device resets the bit according to the source
> device's trace ID.
>
> Reviewed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 12 +
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
> include/linux/coresight.h | 3 +-
> 5 files changed, 307 insertions(+), 1 deletion(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 06f0a7594169..ecd7086a5b83 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -133,6 +133,18 @@ config CORESIGHT_STM
> To compile this driver as a module, choose M here: the
> module will be called coresight-stm.
>
> +config CORESIGHT_CTCU
> + tristate "CoreSight TMC Control Unit driver"
> + depends on CORESIGHT_LINK_AND_SINK_TMC
> + help
> + This driver provides support for CoreSight TMC Control Unit
> + that hosts miscellaneous configuration registers. This is
> + primarily used for controlling the behaviors of the TMC
> + ETR device.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called coresight-ctcu.
> +
> config CORESIGHT_CPU_DEBUG
> tristate "CoreSight CPU Debug driver"
> depends on ARM || ARM64
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 4ba478211b31..1b7869910a12 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
> coresight-cti-sysfs.o
> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/hwtracing/coresight/coresight-ctcu.c
> new file mode 100644
> index 000000000000..e1460a627c4d
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
> @@ -0,0 +1,268 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "coresight-ctcu.h"
> +#include "coresight-priv.h"
> +
> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
> +
> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
> +
> +/*
> + * The TMC Coresight Control Unit uses four ATID registers to control the data
> + * filter function based on the trace ID for each TMC ETR sink. The length of
> + * each ATID register is 32 bits. Therefore, the ETR has a related field in
> + * CTCU that is 128 bits long. Each trace ID is represented by one bit in that
> + * filed.
> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
> + * bit5
> + * ------------------------------------------------------
> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
> + * ------------------------------------------------------
> + *
> + * e.g. ETR0:
> + * 127 0 from ATID_offset for ETR0ATID0
> + * -------------------------
> + * |ATID3|ATID2|ATID1|ATID0|
> + */
> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
> + ((traceid / 32) * 4 + atid_offset)
> +
> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
> +#define CTCU_ATID_REG_SIZE 0x10
> +
> +struct ctcu_atid_config {
> + const u32 atid_offset;
> + const u32 port_num;
> +};
> +
> +struct ctcu_config {
> + const struct ctcu_atid_config *atid_config;
> + int num_atid_config;
> +};
> +
> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
> + {0xf8, 0},
> + {0x108, 1},
> +};
> +
> +static const struct ctcu_config sa8775p_cfgs = {
> + .atid_config = sa8775p_atid_cfgs,
> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
> +};
> +
> +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset,
> + u8 bit, bool enable)
> +{
> + u32 val;
> +
> + CS_UNLOCK(drvdata->base);
> + val = ctcu_readl(drvdata, reg_offset);
> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
minor nit: If possible do not use the ternary operator like this. It is
much better readable as:
if (enable)
val |= BIT(bit);
else
val &= ~BIT(bit);
> + ctcu_writel(drvdata, val, reg_offset);
> + CS_LOCK(drvdata->base);
> +}
> +
> +/*
> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on trace ID when enable is true.
> + * Reset the bit of the ATID register based on trace ID when enable is false.
> + *
> + * @csdev: coresight_device struct related to the device
> + * @traceid: trace ID of the source tracer.
> + * @port_num: port number from TMC ETR sink.
> + * @enable: True for set bit and false for reset bit.
> + *
> + * Returns 0 indicates success. Non-zero result means failure.
> + */
> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, int port_num,
> + bool enable)
> +{
> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + u32 atid_offset, reg_offset;
> + u8 refcnt, bit;
> +
> + atid_offset = drvdata->atid_offset[port_num];
> + if (atid_offset == 0)
> + return -EINVAL;
> +
> + bit = CTCU_ATID_REG_BIT(traceid);
> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
> + return -EINVAL;
> +
> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
> + /* Only program the atid register when the refcnt value is 0 or 1 */
A normal trace source won't be enabled more than once (e.g., ETM). The
only odd one out is the STM, which may be driven by multiple agents.
So this refcounting looks necessary.
> + if (enable && (++refcnt == 1))
> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
> + else if (!enable && (--refcnt == 0))
> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
minor nit:
if ((enable && !refcount++) ||
(!enable && --refcount))
ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
Also, see my comment the bottom for "refcount" being u8 .
> +
> + drvdata->traceid_refcnt[port_num][traceid] = refcnt;
> +
> + return 0;
> +}
> +
> +static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper)
> +{
> + int i;
> +
> + for (i = 0; i < sink->pdata->nr_outconns; ++i) {
> + if (sink->pdata->out_conns[i]->dest_dev)
> + return sink->pdata->out_conns[i]->dest_port;
Don't we need to make sure it matches the helper ? What if there are
multiple helpers ? e.g, a CATU connected to the ETR and CTCU ?
Or even try the opposite ? i.e. search the helper and find the port
matching the sink ?
struct coresight_platform_data *pdata = helper->pdata;
for (i = 0; i < pdata->nr_inconns; ++i)
if (pdata->in_conns[i]->dest_dev == sink)
return pdata->in_conns[i]->src_port;
Not sure if that works with the helper device connection, James ?
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *path,
> + bool enable)
> +{
> + struct coresight_device *sink = coresight_get_sink(path);
> + u8 traceid = path->trace_id;
> + int port_num;
> +
> + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(traceid)) {
> + dev_err(&csdev->dev, "Invalid parameters\n");
> + return -EINVAL;
> + }
> +
> + port_num = ctcu_get_active_port(sink, csdev);
> + if (port_num < 0)
> + return -EINVAL;
> +
> + dev_dbg(&csdev->dev, "traceid is %d\n", traceid);
> +
> + return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable);
> +}
> +
> +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode,
> + void *data)
> +{
> + struct coresight_path *path = (struct coresight_path *)data;
> +
> + return ctcu_set_etr_traceid(csdev, path, true);
> +}
> +
> +static int ctcu_disable(struct coresight_device *csdev, void *data)
> +{
> + struct coresight_path *path = (struct coresight_path *)data;
> +
> + return ctcu_set_etr_traceid(csdev, path, false);
> +}
> +
> +static const struct coresight_ops_helper ctcu_helper_ops = {
> + .enable = ctcu_enable,
> + .disable = ctcu_disable,
> +};
> +
> +static const struct coresight_ops ctcu_ops = {
> + .helper_ops = &ctcu_helper_ops,
> +};
> +
> +static int ctcu_probe(struct platform_device *pdev)
> +{
> + int i;
> + void __iomem *base;
> + struct device *dev = &pdev->dev;
> + struct coresight_platform_data *pdata;
> + struct ctcu_drvdata *drvdata;
> + struct coresight_desc desc = { 0 };
> + const struct ctcu_config *cfgs;
> + const struct ctcu_atid_config *atid_cfg;
> +
> + desc.name = coresight_alloc_device_name(&ctcu_devs, dev);
> + if (!desc.name)
> + return -ENOMEM;
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> +
> + pdata = coresight_get_platform_data(dev);
> + if (IS_ERR(pdata))
> + return PTR_ERR(pdata);
> + dev->platform_data = pdata;
> +
> + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
> + if (!base)
> + return -ENOMEM;
> +
> + drvdata->apb_clk = coresight_get_enable_apb_pclk(dev);
> + if (IS_ERR(drvdata->apb_clk))
> + return -ENODEV;
> +
> + cfgs = of_device_get_match_data(dev);
> + if (cfgs) {
> + if (cfgs->num_atid_config <= ATID_MAX_NUM) {
> + for (i = 0; i < cfgs->num_atid_config; i++) {
> + atid_cfg = &cfgs->atid_config[i];
> + drvdata->atid_offset[i] = atid_cfg->atid_offset;
> + }
> + }
> + }
> +
> + drvdata->base = base;
> + drvdata->dev = dev;
> + platform_set_drvdata(pdev, drvdata);
> +
> + desc.type = CORESIGHT_DEV_TYPE_HELPER;
> + desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU;
> + desc.pdata = pdata;
> + desc.dev = dev;
> + desc.ops = &ctcu_ops;
Please set the desc.access
desc.access = CSDEV_ACCESS_IOMEM(drvdata->base);
> +
> + drvdata->csdev = coresight_register(&desc);
> + if (IS_ERR(drvdata->csdev)) {
> + if (!IS_ERR_OR_NULL(drvdata->apb_clk))
> + clk_put(drvdata->apb_clk);
> +
> + return PTR_ERR(drvdata->csdev);
> + }
> +
> + return 0;
> +}
> +
> +static void ctcu_remove(struct platform_device *pdev)
> +{
> + struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev);
> +
> + coresight_unregister(drvdata->csdev);
> + if (!IS_ERR_OR_NULL(drvdata->apb_clk))
> + clk_put(drvdata->apb_clk);
Why isn't the clock get/put at runtime via pm_runtime calls ?
See coresight-replicator driver for e.g.
> +}
> +
> +static const struct of_device_id ctcu_match[] = {
> + {.compatible = "qcom,sa8775p-ctcu", .data = &sa8775p_cfgs},
> + {}
> +};
> +
> +static struct platform_driver ctcu_driver = {
> + .probe = ctcu_probe,
> + .remove = ctcu_remove,
> + .driver = {
> + .name = "coresight-ctcu",
> + .of_match_table = ctcu_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +module_platform_driver(ctcu_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("CoreSight TMC Control Unit driver");
> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h
> new file mode 100644
> index 000000000000..9890c3da5ec8
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-ctcu.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _CORESIGHT_CTCU_H
> +#define _CORESIGHT_CTCU_H
> +#include "coresight-trace-id.h"
> +
> +/* Maximum number of supported sink devices for a single CTCU in current projects. */
> +#define ATID_MAX_NUM 2
> +
> +struct ctcu_drvdata {
> + void __iomem *base;
> + struct clk *apb_clk;
> + phys_addr_t pbase;
Where is this used ?
> + struct device *dev;
> + struct coresight_device *csdev;
> + raw_spinlock_t spin_lock;
> + u32 atid_offset[ATID_MAX_NUM];
> + /* refcnt for each traceid of each sink */
> + u8 traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
Hopefully u8 is sufficient, but is it ? Why don't we check this in
"enable" path to see if we are going to overflow ?
> +};
> +#endif
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 03d833a15726..55bb825d509e 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -71,7 +71,8 @@ enum coresight_dev_subtype_source {
>
> enum coresight_dev_subtype_helper {
> CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
> - CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI
> + CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI,
> + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,
> };
>
> /**
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path
2025-02-21 10:30 ` Suzuki K Poulose
@ 2025-02-24 2:35 ` Jie Gan
0 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-24 2:35 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 2/21/2025 6:30 PM, Suzuki K Poulose wrote:
> On 17/02/2025 09:30, Jie Gan wrote:
>> Add 'struct coresight_path' to store the data that is needed by
>> coresight_enable_path/coresight_disable_path. The structure will be
>> transmitted to any required devices to enable related funcationalities.
>>
>> The trace_id will be allocated after the path is built. Consequently,
>> The ETM3x and ETM4x devices will directly read the trace_id from path
>> which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id
>> being deleted.
>>
>> Co-developed-by: James Clark <james.clark@linaro.org>
>> Signed-off-by: James Clark <james.clark@linaro.org>
>> Reviewed-by: James Clark <james.clark@linaro.org>
>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>> ---
>
> Personally, I find this patch doing 3 things in one shot, which is
> complicated TBH for the patch review.
>
> 1. Introduce coresight_path
> 2. Move trace-id to coresight_path and allocate it after building the path.
> 3. Change enable/disable to accept the "coresight_path"
>
> Please do not repeat this in the future, split them accordingly. At the
> least we could split this patch into 1 and 2+3
>
Hi Suzuki,
Thanks for comments.
I will spilit this patch and send them with V14, please ignore V13.
Sorry for the inconvenience for the patch review.
>
>> drivers/hwtracing/coresight/coresight-core.c | 106 +++++++++++++-----
>> drivers/hwtracing/coresight/coresight-dummy.c | 5 +-
>> .../hwtracing/coresight/coresight-etm-perf.c | 24 ++--
>> .../hwtracing/coresight/coresight-etm-perf.h | 2 +-
>> drivers/hwtracing/coresight/coresight-etm.h | 1 -
>> .../coresight/coresight-etm3x-core.c | 54 ++-------
>> .../coresight/coresight-etm4x-core.c | 54 ++-------
>> drivers/hwtracing/coresight/coresight-etm4x.h | 1 -
>> drivers/hwtracing/coresight/coresight-priv.h | 12 +-
>> drivers/hwtracing/coresight/coresight-stm.c | 3 +-
>> drivers/hwtracing/coresight/coresight-sysfs.c | 17 ++-
>> drivers/hwtracing/coresight/coresight-tpdm.c | 3 +-
>> include/linux/coresight.h | 12 +-
>> 13 files changed, 140 insertions(+), 154 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/
>> hwtracing/coresight/coresight-core.c
>> index 6cad777757f3..182bfa2420cc 100644
>> --- a/drivers/hwtracing/coresight/coresight-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-core.c
>> @@ -76,14 +76,14 @@ struct coresight_device
>> *coresight_get_percpu_sink(int cpu)
>> }
>> EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);
>> -static struct coresight_device *coresight_get_source(struct list_head
>> *path)
>> +static struct coresight_device *coresight_get_source(struct
>> coresight_path *path)
>> {
>> struct coresight_device *csdev;
>> if (!path)
>> return NULL;
>> - csdev = list_first_entry(path, struct coresight_node, link)->csdev;
>> + csdev = list_first_entry(path->path_list, struct coresight_node,
>> link)->csdev;
>> if (!coresight_is_device_source(csdev))
>> return NULL;
>> @@ -332,12 +332,12 @@ static int coresight_enable_helper(struct
>> coresight_device *csdev,
>> return helper_ops(csdev)->enable(csdev, mode, data);
>> }
>> -static void coresight_disable_helper(struct coresight_device *csdev)
>> +static void coresight_disable_helper(struct coresight_device *csdev,
>> void *data)
>> {
>> - helper_ops(csdev)->disable(csdev, NULL);
>> + helper_ops(csdev)->disable(csdev, data);
>> }
>> -static void coresight_disable_helpers(struct coresight_device *csdev)
>> +static void coresight_disable_helpers(struct coresight_device *csdev,
>> void *data)
>> {
>> int i;
>> struct coresight_device *helper;
>> @@ -345,7 +345,7 @@ static void coresight_disable_helpers(struct
>> coresight_device *csdev)
>> for (i = 0; i < csdev->pdata->nr_outconns; ++i) {
>> helper = csdev->pdata->out_conns[i]->dest_dev;
>> if (helper && coresight_is_helper(helper))
>> - coresight_disable_helper(helper);
>> + coresight_disable_helper(helper, data);
>> }
>> }
>> @@ -362,7 +362,7 @@ static void coresight_disable_helpers(struct
>> coresight_device *csdev)
>> void coresight_disable_source(struct coresight_device *csdev, void
>> *data)
>> {
>> source_ops(csdev)->disable(csdev, data);
>> - coresight_disable_helpers(csdev);
>> + coresight_disable_helpers(csdev, NULL);
>> }
>> EXPORT_SYMBOL_GPL(coresight_disable_source);
>> @@ -371,16 +371,16 @@ EXPORT_SYMBOL_GPL(coresight_disable_source);
>> * @nd in the list. If @nd is NULL, all the components, except the
>> SOURCE are
>> * disabled.
>> */
>> -static void coresight_disable_path_from(struct list_head *path,
>> +static void coresight_disable_path_from(struct coresight_path *path,
>> struct coresight_node *nd)
>> {
>> u32 type;
>> struct coresight_device *csdev, *parent, *child;
>> if (!nd)
>> - nd = list_first_entry(path, struct coresight_node, link);
>> + nd = list_first_entry(path->path_list, struct coresight_node,
>> link);
>> - list_for_each_entry_continue(nd, path, link) {
>> + list_for_each_entry_continue(nd, path->path_list, link) {
>> csdev = nd->csdev;
>> type = csdev->type;
>> @@ -418,11 +418,11 @@ static void coresight_disable_path_from(struct
>> list_head *path,
>> }
>> /* Disable all helpers adjacent along the path last */
>> - coresight_disable_helpers(csdev);
>> + coresight_disable_helpers(csdev, path);
>> }
>> }
>> -void coresight_disable_path(struct list_head *path)
>> +void coresight_disable_path(struct coresight_path *path)
>> {
>> coresight_disable_path_from(path, NULL);
>> }
>> @@ -447,7 +447,7 @@ static int coresight_enable_helpers(struct
>> coresight_device *csdev,
>> return 0;
>> }
>> -int coresight_enable_path(struct list_head *path, enum cs_mode mode,
>> +int coresight_enable_path(struct coresight_path *path, enum cs_mode
>> mode,
>> void *sink_data)
>> {
>> int ret = 0;
>> @@ -457,12 +457,12 @@ int coresight_enable_path(struct list_head
>> *path, enum cs_mode mode,
>> struct coresight_device *source;
>> source = coresight_get_source(path);
>> - list_for_each_entry_reverse(nd, path, link) {
>> + list_for_each_entry_reverse(nd, path->path_list, link) {
>> csdev = nd->csdev;
>> type = csdev->type;
>> /* Enable all helpers adjacent to the path first */
>> - ret = coresight_enable_helpers(csdev, mode, sink_data);
>> + ret = coresight_enable_helpers(csdev, mode, path);
>> if (ret)
>> goto err;
>> /*
>> @@ -510,20 +510,21 @@ int coresight_enable_path(struct list_head
>> *path, enum cs_mode mode,
>> goto out;
>> }
>> -struct coresight_device *coresight_get_sink(struct list_head *path)
>> +struct coresight_device *coresight_get_sink(struct coresight_path *path)
>> {
>> struct coresight_device *csdev;
>> if (!path)
>> return NULL;
>> - csdev = list_last_entry(path, struct coresight_node, link)->csdev;
>> + csdev = list_last_entry(path->path_list, struct coresight_node,
>> link)->csdev;
>> if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
>> csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
>> return NULL;
>> return csdev;
>> }
>> +EXPORT_SYMBOL_GPL(coresight_get_sink);
>> u32 coresight_get_sink_id(struct coresight_device *csdev)
>> {
>> @@ -654,6 +655,51 @@ static void coresight_drop_device(struct
>> coresight_device *csdev)
>> }
>> }
>> +/*
>> + * Links or sources will read their existing or alloc a trace ID, if
>> their ID
>> + * callback is set.
>> + */
>
> Please could we document the return value conditions here ?
Sure, will do.
>
>> +static int coresight_get_trace_id(struct coresight_device *csdev,
>> + enum cs_mode mode,
>> + struct coresight_device *sink)
>> +{
>> + if (csdev->type == CORESIGHT_DEV_TYPE_LINK && link_ops(csdev)-
>> >trace_id)
>> + return link_ops(csdev)->trace_id(csdev, mode, sink);
>> +
>> + if (csdev->type == CORESIGHT_DEV_TYPE_SOURCE &&
>> source_ops(csdev)->trace_id)
>> + return source_ops(csdev)->trace_id(csdev, mode, sink);
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Call this after creating the path and before enabling it. This leaves
>> + * the trace ID set on the path and returns the ID, or an error if it
>> + * couldn't be assigned.
>> + */
>> +int coresight_path_assign_trace_id(struct coresight_path *path,
>> + enum cs_mode mode)
>> +{
>> + struct coresight_device *sink = coresight_get_sink(path);
>> + struct coresight_node *nd;
>> + int ret;
>
> Might be better to rename this as "trace_id" ? As we return the trace id
> not a status of whether it was allocated or not. Or drop it completely
> and return path->trace_id, below when we succeed. Or it could even
> be a void, as the caller can check IS_VALID(path->trace_id)
>
I think it's better to rename the ret to trace_id and make the function
be a void.
Then we can check the path->trace_id with
IS_VALID_CS_TRACE_ID(path->trace_id) in both sysfs and perf modes.
>
>> +
>> + list_for_each_entry(nd, path->path_list, link) {
>> + /* Assign a trace ID to the path for the first device that
>> wants to do it */
>> + ret = coresight_get_trace_id(nd->csdev, mode, sink);
>> +
>> + /*
>> + * 0 in this context is that it didn't want to assign so keep
>> searching.
>> + * Non 0 is either success or fail, return it either way.
>> + */
>> + if (ret != 0) {
>> + path->trace_id = ret;
>> + return ret;
>> + }
>> + }
>> + return 0;
>> +}
>> +
>> /**
>> * _coresight_build_path - recursively build a path from a @csdev to
>> a sink.
>> * @csdev: The device to start from.
>> @@ -669,7 +715,7 @@ static void coresight_drop_device(struct
>> coresight_device *csdev)
>> static int _coresight_build_path(struct coresight_device *csdev,
>> struct coresight_device *source,
>> struct coresight_device *sink,
>> - struct list_head *path)
>> + struct coresight_path *path)
>> {
>> int i, ret;
>> bool found = false;
>> @@ -722,28 +768,37 @@ static int _coresight_build_path(struct
>> coresight_device *csdev,
>> return -ENOMEM;
>> node->csdev = csdev;
>> - list_add(&node->link, path);
>> + list_add(&node->link, path->path_list);
>> return 0;
>> }
>> -struct list_head *coresight_build_path(struct coresight_device *source,
>> +struct coresight_path *coresight_build_path(struct coresight_device
>> *source,
>> struct coresight_device *sink)
>> {
>> - struct list_head *path;
>> + struct coresight_path *path;
>> + struct list_head *path_list;
>> int rc;
>> if (!sink)
>> return ERR_PTR(-EINVAL);
>> - path = kzalloc(sizeof(struct list_head), GFP_KERNEL);
>> + path = kzalloc(sizeof(struct coresight_path), GFP_KERNEL);
>> if (!path)
>> return ERR_PTR(-ENOMEM);
>> - INIT_LIST_HEAD(path);
>> + path_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
>> + if (!path_list) {
>> + kfree(path);
>> + return ERR_PTR(-ENOMEM);
>> + }
>
>
>
>> +
>> + INIT_LIST_HEAD(path_list);
>> + path->path_list = path_list;
>> rc = _coresight_build_path(source, source, sink, path);
>> if (rc) {
>> + kfree(path_list);
>> kfree(path);
>> return ERR_PTR(rc);
>> }
>> @@ -758,12 +813,12 @@ struct list_head *coresight_build_path(struct
>> coresight_device *source,
>> * Go through all the elements of a path and 1) removed it from the
>> list and
>> * 2) free the memory allocated for each node.
>> */
>> -void coresight_release_path(struct list_head *path)
>> +void coresight_release_path(struct coresight_path *path)
>> {
>> struct coresight_device *csdev;
>> struct coresight_node *nd, *next;
>> - list_for_each_entry_safe(nd, next, path, link) {
>> + list_for_each_entry_safe(nd, next, path->path_list, link) {
>> csdev = nd->csdev;
>> coresight_drop_device(csdev);
>> @@ -771,6 +826,7 @@ void coresight_release_path(struct list_head *path)
>> kfree(nd);
>> }
>> + kfree(path->path_list);
>> kfree(path);
>> }
>> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/
>> hwtracing/coresight/coresight-dummy.c
>> index c47f0382b943..d9a811d44885 100644
>> --- a/drivers/hwtracing/coresight/coresight-dummy.c
>> +++ b/drivers/hwtracing/coresight/coresight-dummy.c
>> @@ -22,9 +22,8 @@ struct dummy_drvdata {
>> DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source");
>> DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink");
>> -static int dummy_source_enable(struct coresight_device *csdev,
>> - struct perf_event *event, enum cs_mode mode,
>> - __maybe_unused struct coresight_trace_id_map *id_map)
>> +static int dummy_source_enable(struct coresight_device *csdev, struct
>> perf_event *event,
>> + enum cs_mode mode, struct coresight_path *path)
>> {
>> if (!coresight_take_mode(csdev, mode))
>> return -EBUSY;
>> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/
>> drivers/hwtracing/coresight/coresight-etm-perf.c
>> index ad6a8f4b70b6..ebdcf56b7463 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
>> @@ -136,13 +136,13 @@ static const struct attribute_group
>> *etm_pmu_attr_groups[] = {
>> NULL,
>> };
>> -static inline struct list_head **
>> +static inline struct coresight_path **
>> etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu)
>> {
>> return per_cpu_ptr(data->path, cpu);
>> }
>> -static inline struct list_head *
>> +static inline struct coresight_path *
>> etm_event_cpu_path(struct etm_event_data *data, int cpu)
>> {
>> return *etm_event_cpu_path_ptr(data, cpu);
>> @@ -226,7 +226,7 @@ static void free_event_data(struct work_struct *work)
>> cscfg_deactivate_config(event_data->cfg_hash);
>> for_each_cpu(cpu, mask) {
>> - struct list_head **ppath;
>> + struct coresight_path **ppath;
>> ppath = etm_event_cpu_path_ptr(event_data, cpu);
>> if (!(IS_ERR_OR_NULL(*ppath))) {
>> @@ -276,7 +276,7 @@ static void *alloc_event_data(int cpu)
>> * unused memory when dealing with single CPU trace scenarios is
>> small
>> * compared to the cost of searching through an optimized array.
>> */
>> - event_data->path = alloc_percpu(struct list_head *);
>> + event_data->path = alloc_percpu(struct coresight_path *);
>> if (!event_data->path) {
>> kfree(event_data);
>> @@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event
>> *event, void **pages,
>> * CPUs, we can handle it and fail the session.
>> */
>> for_each_cpu(cpu, mask) {
>> - struct list_head *path;
>> + struct coresight_path *path;
>> struct coresight_device *csdev;
>> csdev = per_cpu(csdev_src, cpu);
>> @@ -407,7 +407,7 @@ static void *etm_setup_aux(struct perf_event
>> *event, void **pages,
>> }
>> /* ensure we can allocate a trace ID for this CPU */
>> - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink-
>> >perf_sink_id_map);
>> + trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF);
>> if (!IS_VALID_CS_TRACE_ID(trace_id)) {
>> cpumask_clear_cpu(cpu, mask);
>> coresight_release_path(path);
>> @@ -458,9 +458,8 @@ static void etm_event_start(struct perf_event
>> *event, int flags)
>> struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
>> struct perf_output_handle *handle = &ctxt->handle;
>> struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
>> - struct list_head *path;
>> + struct coresight_path *path;
>> u64 hw_id;
>> - u8 trace_id;
>> if (!csdev)
>> goto fail;
>> @@ -503,8 +502,7 @@ static void etm_event_start(struct perf_event
>> *event, int flags)
>> goto fail_end_stop;
>> /* Finally enable the tracer */
>> - if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF,
>> - &sink->perf_sink_id_map))
>> + if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, path))
>> goto fail_disable_path;
>> /*
>> @@ -514,13 +512,11 @@ static void etm_event_start(struct perf_event
>> *event, int flags)
>> if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) {
>> cpumask_set_cpu(cpu, &event_data->aux_hwid_done);
>> - trace_id = coresight_trace_id_read_cpu_id_map(cpu, &sink-
>> >perf_sink_id_map);
>> -
>> hw_id = FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK,
>> CS_AUX_HW_ID_MAJOR_VERSION);
>> hw_id |= FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK,
>> CS_AUX_HW_ID_MINOR_VERSION);
>> - hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, trace_id);
>> + hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, path->trace_id);
>> hw_id |= FIELD_PREP(CS_AUX_HW_ID_SINK_ID_MASK,
>> coresight_get_sink_id(sink));
>> perf_report_aux_output_id(event, hw_id);
>> @@ -558,7 +554,7 @@ static void etm_event_stop(struct perf_event
>> *event, int mode)
>> struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
>> struct perf_output_handle *handle = &ctxt->handle;
>> struct etm_event_data *event_data;
>> - struct list_head *path;
>> + struct coresight_path *path;
>> /*
>> * If we still have access to the event_data via handle,
>> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/
>> drivers/hwtracing/coresight/coresight-etm-perf.h
>> index 744531158d6b..5febbcdb8696 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm-perf.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
>> @@ -59,7 +59,7 @@ struct etm_event_data {
>> cpumask_t aux_hwid_done;
>> void *snk_config;
>> u32 cfg_hash;
>> - struct list_head * __percpu *path;
>> + struct coresight_path * __percpu *path;
>> };
>> int etm_perf_symlink(struct coresight_device *csdev, bool link);
>> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/
>> hwtracing/coresight/coresight-etm.h
>> index e02c3ea972c9..171f1384f7c0 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm.h
>> @@ -284,6 +284,5 @@ extern const struct attribute_group
>> *coresight_etm_groups[];
>> void etm_set_default(struct etm_config *config);
>> void etm_config_trace_mode(struct etm_config *config);
>> struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
>> -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata);
>> void etm_release_trace_id(struct etm_drvdata *drvdata);
>> #endif
>> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/
>> drivers/hwtracing/coresight/coresight-etm3x-core.c
>> index a38e72ef8e79..cb8a30a3b48e 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
>> @@ -455,26 +455,6 @@ static int etm_cpu_id(struct coresight_device
>> *csdev)
>> return drvdata->cpu;
>> }
>> -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata)
>> -{
>> - int trace_id;
>> -
>> - /*
>> - * This will allocate a trace ID to the cpu,
>> - * or return the one currently allocated.
>> - *
>> - * trace id function has its own lock
>> - */
>> - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
>> - if (IS_VALID_CS_TRACE_ID(trace_id))
>> - drvdata->traceid = (u8)trace_id;
>> - else
>> - dev_err(&drvdata->csdev->dev,
>> - "Failed to allocate trace ID for %s on CPU%d\n",
>> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
>> - return trace_id;
>> -}
>> -
>> void etm_release_trace_id(struct etm_drvdata *drvdata)
>> {
>> coresight_trace_id_put_cpu_id(drvdata->cpu);
>> @@ -482,38 +462,22 @@ void etm_release_trace_id(struct etm_drvdata
>> *drvdata)
>> static int etm_enable_perf(struct coresight_device *csdev,
>> struct perf_event *event,
>> - struct coresight_trace_id_map *id_map)
>> + struct coresight_path *path)
>> {
>> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> - int trace_id;
>> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
>> return -EINVAL;
>> /* Configure the tracer based on the session's specifics */
>> etm_parse_event_config(drvdata, event);
>> -
>> - /*
>> - * perf allocates cpu ids as part of _setup_aux() - device needs
>> to use
>> - * the allocated ID. This reads the current version without
>> allocation.
>> - *
>> - * This does not use the trace id lock to prevent lock_dep issues
>> - * with perf locks - we know the ID cannot change until perf
>> shuts down
>> - * the session
>> - */
>> - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
>> - if (!IS_VALID_CS_TRACE_ID(trace_id)) {
>> - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s
>> on CPU%d\n",
>> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
>> - return -EINVAL;
>> - }
>> - drvdata->traceid = (u8)trace_id;
>> + drvdata->traceid = path->trace_id;
>> /* And enable it */
>> return etm_enable_hw(drvdata);
>> }
>> -static int etm_enable_sysfs(struct coresight_device *csdev)
>> +static int etm_enable_sysfs(struct coresight_device *csdev, struct
>> coresight_path *path)
>> {
>> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> struct etm_enable_arg arg = { };
>> @@ -521,10 +485,7 @@ static int etm_enable_sysfs(struct
>> coresight_device *csdev)
>> spin_lock(&drvdata->spinlock);
>> - /* sysfs needs to allocate and set a trace ID */
>> - ret = etm_read_alloc_trace_id(drvdata);
>> - if (ret < 0)
>> - goto unlock_enable_sysfs;
>> + drvdata->traceid = path->trace_id;
>> /*
>> * Configure the ETM only if the CPU is online. If it isn't online
>> @@ -545,7 +506,6 @@ static int etm_enable_sysfs(struct
>> coresight_device *csdev)
>> if (ret)
>> etm_release_trace_id(drvdata);
>> -unlock_enable_sysfs:
>> spin_unlock(&drvdata->spinlock);
>> if (!ret)
>> @@ -554,7 +514,7 @@ static int etm_enable_sysfs(struct
>> coresight_device *csdev)
>> }
>> static int etm_enable(struct coresight_device *csdev, struct
>> perf_event *event,
>> - enum cs_mode mode, struct coresight_trace_id_map *id_map)
>> + enum cs_mode mode, struct coresight_path *path)
>> {
>> int ret;
>> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> @@ -566,10 +526,10 @@ static int etm_enable(struct coresight_device
>> *csdev, struct perf_event *event,
>> switch (mode) {
>> case CS_MODE_SYSFS:
>> - ret = etm_enable_sysfs(csdev);
>> + ret = etm_enable_sysfs(csdev, path);
>> break;
>> case CS_MODE_PERF:
>> - ret = etm_enable_perf(csdev, event, id_map);
>> + ret = etm_enable_perf(csdev, event, path);
>> break;
>> default:
>> ret = -EINVAL;
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/
>> drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index 1a993d5380e7..3d0fc25085ea 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -233,25 +233,6 @@ static int etm4_cpu_id(struct coresight_device
>> *csdev)
>> return drvdata->cpu;
>> }
>> -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
>> -{
>> - int trace_id;
>> -
>> - /*
>> - * This will allocate a trace ID to the cpu,
>> - * or return the one currently allocated.
>> - * The trace id function has its own lock
>> - */
>> - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
>> - if (IS_VALID_CS_TRACE_ID(trace_id))
>> - drvdata->trcid = (u8)trace_id;
>> - else
>> - dev_err(&drvdata->csdev->dev,
>> - "Failed to allocate trace ID for %s on CPU%d\n",
>> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
>> - return trace_id;
>> -}
>> -
>> void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
>> {
>> coresight_trace_id_put_cpu_id(drvdata->cpu);
>> @@ -788,9 +769,9 @@ static int etm4_parse_event_config(struct
>> coresight_device *csdev,
>> static int etm4_enable_perf(struct coresight_device *csdev,
>> struct perf_event *event,
>> - struct coresight_trace_id_map *id_map)
>> + struct coresight_path *path)
>> {
>> - int ret = 0, trace_id;
>> + int ret = 0;
>> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
>> @@ -803,22 +784,7 @@ static int etm4_enable_perf(struct
>> coresight_device *csdev,
>> if (ret)
>> goto out;
>> - /*
>> - * perf allocates cpu ids as part of _setup_aux() - device needs
>> to use
>> - * the allocated ID. This reads the current version without
>> allocation.
>> - *
>> - * This does not use the trace id lock to prevent lock_dep issues
>> - * with perf locks - we know the ID cannot change until perf
>> shuts down
>> - * the session
>> - */
>> - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
>> - if (!IS_VALID_CS_TRACE_ID(trace_id)) {
>> - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s
>> on CPU%d\n",
>> - dev_name(&drvdata->csdev->dev), drvdata->cpu);
>> - ret = -EINVAL;
>> - goto out;
>> - }
>> - drvdata->trcid = (u8)trace_id;
>> + drvdata->trcid = path->trace_id;
>> /* And enable it */
>> ret = etm4_enable_hw(drvdata);
>> @@ -827,7 +793,7 @@ static int etm4_enable_perf(struct
>> coresight_device *csdev,
>> return ret;
>> }
>> -static int etm4_enable_sysfs(struct coresight_device *csdev)
>> +static int etm4_enable_sysfs(struct coresight_device *csdev, struct
>> coresight_path *path)
>> {
>> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> struct etm4_enable_arg arg = { };
>> @@ -844,10 +810,7 @@ static int etm4_enable_sysfs(struct
>> coresight_device *csdev)
>> spin_lock(&drvdata->spinlock);
>> - /* sysfs needs to read and allocate a trace ID */
>> - ret = etm4_read_alloc_trace_id(drvdata);
>> - if (ret < 0)
>> - goto unlock_sysfs_enable;
>> + drvdata->trcid = path->trace_id;
>> /*
>> * Executing etm4_enable_hw on the cpu whose ETM is being enabled
>> @@ -864,7 +827,6 @@ static int etm4_enable_sysfs(struct
>> coresight_device *csdev)
>> if (ret)
>> etm4_release_trace_id(drvdata);
>> -unlock_sysfs_enable:
>> spin_unlock(&drvdata->spinlock);
>> if (!ret)
>> @@ -873,7 +835,7 @@ static int etm4_enable_sysfs(struct
>> coresight_device *csdev)
>> }
>> static int etm4_enable(struct coresight_device *csdev, struct
>> perf_event *event,
>> - enum cs_mode mode, struct coresight_trace_id_map *id_map)
>> + enum cs_mode mode, struct coresight_path *path)
>> {
>> int ret;
>> @@ -884,10 +846,10 @@ static int etm4_enable(struct coresight_device
>> *csdev, struct perf_event *event,
>> switch (mode) {
>> case CS_MODE_SYSFS:
>> - ret = etm4_enable_sysfs(csdev);
>> + ret = etm4_enable_sysfs(csdev, path);
>> break;
>> case CS_MODE_PERF:
>> - ret = etm4_enable_perf(csdev, event, id_map);
>> + ret = etm4_enable_perf(csdev, event, path);
>> break;
>> default:
>> ret = -EINVAL;
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/
>> hwtracing/coresight/coresight-etm4x.h
>> index 1119762b5cec..2b92de17b5a2 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
>> @@ -1066,6 +1066,5 @@ static inline bool etm4x_is_ete(struct
>> etmv4_drvdata *drvdata)
>> return drvdata->arch >= ETM_ARCH_ETE;
>> }
>> -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata);
>> void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
>> #endif
>> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/
>> hwtracing/coresight/coresight-priv.h
>> index 76403530f33e..c10dd3643854 100644
>> --- a/drivers/hwtracing/coresight/coresight-priv.h
>> +++ b/drivers/hwtracing/coresight/coresight-priv.h
>> @@ -132,16 +132,16 @@ static inline void CS_UNLOCK(void __iomem *addr)
>> } while (0);
>> }
>> -void coresight_disable_path(struct list_head *path);
>> -int coresight_enable_path(struct list_head *path, enum cs_mode mode,
>> +void coresight_disable_path(struct coresight_path *path);
>> +int coresight_enable_path(struct coresight_path *path, enum cs_mode
>> mode,
>> void *sink_data);
>> -struct coresight_device *coresight_get_sink(struct list_head *path);
>> +struct coresight_device *coresight_get_sink(struct coresight_path
>> *path);
>> struct coresight_device *coresight_get_sink_by_id(u32 id);
>> struct coresight_device *
>> coresight_find_default_sink(struct coresight_device *csdev);
>> -struct list_head *coresight_build_path(struct coresight_device *csdev,
>> +struct coresight_path *coresight_build_path(struct coresight_device
>> *csdev,
>> struct coresight_device *sink);
>> -void coresight_release_path(struct list_head *path);
>> +void coresight_release_path(struct coresight_path *path);
>> int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
>> void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
>> int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
>> @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device
>> *orig,
>> void coresight_remove_links(struct coresight_device *orig,
>> struct coresight_connection *conn);
>> u32 coresight_get_sink_id(struct coresight_device *csdev);
>> +int coresight_path_assign_trace_id(struct coresight_path *path,
>> + enum cs_mode mode);
>> #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
>> extern int etm_readl_cp14(u32 off, unsigned int *val);
>> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/
>> hwtracing/coresight/coresight-stm.c
>> index 64fcfa916562..0d4a9d325df4 100644
>> --- a/drivers/hwtracing/coresight/coresight-stm.c
>> +++ b/drivers/hwtracing/coresight/coresight-stm.c
>> @@ -194,8 +194,7 @@ static void stm_enable_hw(struct stm_drvdata
>> *drvdata)
>> }
>> static int stm_enable(struct coresight_device *csdev, struct
>> perf_event *event,
>> - enum cs_mode mode,
>> - __maybe_unused struct coresight_trace_id_map *trace_id)
>> + enum cs_mode mode, struct coresight_path *path)
>> {
>> struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/
>> hwtracing/coresight/coresight-sysfs.c
>> index a01c9e54e2ed..c2b0a1f59d1a 100644
>> --- a/drivers/hwtracing/coresight/coresight-sysfs.c
>> +++ b/drivers/hwtracing/coresight/coresight-sysfs.c
>> @@ -22,7 +22,7 @@ static DEFINE_IDR(path_idr);
>> * When operating Coresight drivers from the sysFS interface, only a
>> single
>> * path can exist from a tracer (associated to a CPU) to a sink.
>> */
>> -static DEFINE_PER_CPU(struct list_head *, tracer_path);
>> +static DEFINE_PER_CPU(struct coresight_path *, tracer_path);
>> ssize_t coresight_simple_show_pair(struct device *_dev,
>> struct device_attribute *attr, char *buf)
>> @@ -53,7 +53,8 @@ ssize_t coresight_simple_show32(struct device *_dev,
>> EXPORT_SYMBOL_GPL(coresight_simple_show32);
>> static int coresight_enable_source_sysfs(struct coresight_device
>> *csdev,
>> - enum cs_mode mode, void *data)
>> + enum cs_mode mode,
>> + struct coresight_path *path)
>> {
>> int ret;
>> @@ -64,7 +65,7 @@ static int coresight_enable_source_sysfs(struct
>> coresight_device *csdev,
>> */
>> lockdep_assert_held(&coresight_mutex);
>> if (coresight_get_mode(csdev) != CS_MODE_SYSFS) {
>> - ret = source_ops(csdev)->enable(csdev, data, mode, NULL);
>> + ret = source_ops(csdev)->enable(csdev, NULL, mode, path);
>> if (ret)
>> return ret;
>> }
>> @@ -167,7 +168,7 @@ int coresight_enable_sysfs(struct coresight_device
>> *csdev)
>> {
>> int cpu, ret = 0;
>> struct coresight_device *sink;
>> - struct list_head *path;
>> + struct coresight_path *path;
>> enum coresight_dev_subtype_source subtype;
>> u32 hash;
>> @@ -209,11 +210,15 @@ int coresight_enable_sysfs(struct
>> coresight_device *csdev)
>> goto out;
>> }
>> + ret = coresight_path_assign_trace_id(path, CS_MODE_SYSFS);
>> + if (ret < 0)
>> + goto err_path;
>> +
>> ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL);
>> if (ret)
>> goto err_path;
>> - ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, NULL);
>> + ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, path);
>> if (ret)
>> goto err_source;
>> @@ -262,7 +267,7 @@ EXPORT_SYMBOL_GPL(coresight_enable_sysfs);
>> void coresight_disable_sysfs(struct coresight_device *csdev)
>> {
>> int cpu, ret;
>> - struct list_head *path = NULL;
>> + struct coresight_path *path = NULL;
>> u32 hash;
>> mutex_lock(&coresight_mutex);
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/
>> hwtracing/coresight/coresight-tpdm.c
>> index c38f9701665e..f0880a62028f 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>> @@ -439,8 +439,7 @@ static void __tpdm_enable(struct tpdm_drvdata
>> *drvdata)
>> }
>> static int tpdm_enable(struct coresight_device *csdev, struct
>> perf_event *event,
>> - enum cs_mode mode,
>> - __maybe_unused struct coresight_trace_id_map *id_map)
>> + enum cs_mode mode, struct coresight_path *path)
>> {
>> struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
>> index 70407d61262e..03d833a15726 100644
>> --- a/include/linux/coresight.h
>> +++ b/include/linux/coresight.h
>> @@ -329,6 +329,16 @@ static struct coresight_dev_list (var) =
>> { \
>> #define to_coresight_device(d) container_of(d, struct
>> coresight_device, dev)
>> +/**
>> + * struct coresight_path - data needed by enable/disable path
>> + * @path: path from source to sink.
>> + * @trace_id: trace_id of the whole path.
>> + */
>> +struct coresight_path {
>> + struct list_head *path_list;
>
> Minor nit: We could do
>
> struct list_head path_list;
>
> to avoid allocating/freeing the head node without multiple
> kzalloc/kfree
>
>
> Suzuki
Sure, will do. With the optimization, we dont need to manager the memory
alloc/free for the list head in build/release path functions.
Thanks,
Jie
>
>
>
>> + u8 trace_id;
>> +};
>> +
>> enum cs_mode {
>> CS_MODE_DISABLED,
>> CS_MODE_SYSFS,
>> @@ -393,7 +403,7 @@ struct coresight_ops_link {
>> struct coresight_ops_source {
>> int (*cpu_id)(struct coresight_device *csdev);
>> int (*enable)(struct coresight_device *csdev, struct perf_event
>> *event,
>> - enum cs_mode mode, struct coresight_trace_id_map *id_map);
>> + enum cs_mode mode, struct coresight_path *path);
>> void (*disable)(struct coresight_device *csdev,
>> struct perf_event *event);
>> int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-21 11:39 ` Suzuki K Poulose
@ 2025-02-24 3:32 ` Jie Gan
2025-02-24 9:53 ` James Clark
2025-02-24 10:22 ` Suzuki K Poulose
0 siblings, 2 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-24 3:32 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 2/21/2025 7:39 PM, Suzuki K Poulose wrote:
> On 17/02/2025 09:30, Jie Gan wrote:
>> The Coresight TMC Control Unit hosts miscellaneous configuration
>> registers
>> which control various features related to TMC ETR sink.
>>
>> Based on the trace ID, which is programmed in the related CTCU ATID
>> register of a specific ETR, trace data with that trace ID gets into
>> the ETR buffer, while other trace data gets dropped.
>>
>> Enabling source device sets one bit of the ATID register based on
>> source device's trace ID.
>> Disabling source device resets the bit according to the source
>> device's trace ID.
>>
>> Reviewed-by: James Clark <james.clark@linaro.org>
>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>> ---
>> drivers/hwtracing/coresight/Kconfig | 12 +
>> drivers/hwtracing/coresight/Makefile | 1 +
>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
>> include/linux/coresight.h | 3 +-
>> 5 files changed, 307 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>>
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/
>> coresight/Kconfig
>> index 06f0a7594169..ecd7086a5b83 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -133,6 +133,18 @@ config CORESIGHT_STM
>> To compile this driver as a module, choose M here: the
>> module will be called coresight-stm.
>> +config CORESIGHT_CTCU
>> + tristate "CoreSight TMC Control Unit driver"
>> + depends on CORESIGHT_LINK_AND_SINK_TMC
>> + help
>> + This driver provides support for CoreSight TMC Control Unit
>> + that hosts miscellaneous configuration registers. This is
>> + primarily used for controlling the behaviors of the TMC
>> + ETR device.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called coresight-ctcu.
>> +
>> config CORESIGHT_CPU_DEBUG
>> tristate "CoreSight CPU Debug driver"
>> depends on ARM || ARM64
>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/
>> coresight/Makefile
>> index 4ba478211b31..1b7869910a12 100644
>> --- a/drivers/hwtracing/coresight/Makefile
>> +++ b/drivers/hwtracing/coresight/Makefile
>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o
>> coresight-cti-platform.o \
>> coresight-cti-sysfs.o
>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/
>> hwtracing/coresight/coresight-ctcu.c
>> new file mode 100644
>> index 000000000000..e1460a627c4d
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
>> @@ -0,0 +1,268 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/coresight.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +
>> +#include "coresight-ctcu.h"
>> +#include "coresight-priv.h"
>> +
>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
>> +
>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val),
>> drvdata->base + offset)
>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base
>> + offset)
>> +
>> +/*
>> + * The TMC Coresight Control Unit uses four ATID registers to control
>> the data
>> + * filter function based on the trace ID for each TMC ETR sink. The
>> length of
>> + * each ATID register is 32 bits. Therefore, the ETR has a related
>> field in
>> + * CTCU that is 128 bits long. Each trace ID is represented by one
>> bit in that
>> + * filed.
>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
>> + * bit5
>> + * ------------------------------------------------------
>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
>> + * ------------------------------------------------------
>> + *
>> + * e.g. ETR0:
>> + * 127 0 from ATID_offset for ETR0ATID0
>> + * -------------------------
>> + * |ATID3|ATID2|ATID1|ATID0|
>> + */
>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
>> + ((traceid / 32) * 4 + atid_offset)
>> +
>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
>> +#define CTCU_ATID_REG_SIZE 0x10
>> +
>> +struct ctcu_atid_config {
>> + const u32 atid_offset;
>> + const u32 port_num;
>> +};
>> +
>> +struct ctcu_config {
>> + const struct ctcu_atid_config *atid_config;
>> + int num_atid_config;
>> +};
>> +
>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
>> + {0xf8, 0},
>> + {0x108, 1},
>> +};
>> +
>> +static const struct ctcu_config sa8775p_cfgs = {
>> + .atid_config = sa8775p_atid_cfgs,
>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
>> +};
>> +
>> +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata,
>> u32 reg_offset,
>> + u8 bit, bool enable)
>> +{
>> + u32 val;
>> +
>> + CS_UNLOCK(drvdata->base);
>> + val = ctcu_readl(drvdata, reg_offset);
>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
>
> minor nit: If possible do not use the ternary operator like this. It is
> much better readable as:
>
> if (enable)
> val |= BIT(bit);
> else
> val &= ~BIT(bit);
>
Will do this way.
>> + ctcu_writel(drvdata, val, reg_offset);
>> + CS_LOCK(drvdata->base);
>> +}
>> +
>> +/*
>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on
>> trace ID when enable is true.
>> + * Reset the bit of the ATID register based on trace ID when enable
>> is false.
>> + *
>> + * @csdev: coresight_device struct related to the device
>> + * @traceid: trace ID of the source tracer.
>> + * @port_num: port number from TMC ETR sink.
>> + * @enable: True for set bit and false for reset bit.
>> + *
>> + * Returns 0 indicates success. Non-zero result means failure.
>> + */
>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8
>> traceid, int port_num,
>> + bool enable)
>> +{
>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> + u32 atid_offset, reg_offset;
>> + u8 refcnt, bit;
>> +
>> + atid_offset = drvdata->atid_offset[port_num];
>> + if (atid_offset == 0)
>> + return -EINVAL;
>> +
>> + bit = CTCU_ATID_REG_BIT(traceid);
>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
>> + return -EINVAL;
>> +
>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
>> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
>> + /* Only program the atid register when the refcnt value is 0 or 1 */
>
> A normal trace source won't be enabled more than once (e.g., ETM). The
> only odd one out is the STM, which may be driven by multiple agents.
> So this refcounting looks necessary.
>
Besides, for the TPDMs which shared the trace_id of the TPDA also need
the refcnt. Consider we have TPDM1 and TPDM2 connected to the same TPDA
device. Once we disable one of the TPDM without checking the refcnt, the
filter function will be disabled for another TPDM.
>> + if (enable && (++refcnt == 1))
>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>> + else if (!enable && (--refcnt == 0))
>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>
> minor nit:
>
> if ((enable && !refcount++) ||
> (!enable && --refcount))
> ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>
>
I did (enable && (++refcnt == 1)) just because I think we only need
program the register when refcnt is equal to 1. We dont need reprogram
the register with same value when refcnt greater than 1. So I think it's
better for the performance?
> Also, see my comment the bottom for "refcount" being u8 .
Sure, will check.
>
>
>> +
>> + drvdata->traceid_refcnt[port_num][traceid] = refcnt;
>> +
>> + return 0;
>> +}
>> +
>> +static int ctcu_get_active_port(struct coresight_device *sink, struct
>> coresight_device *helper)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < sink->pdata->nr_outconns; ++i) {
>> + if (sink->pdata->out_conns[i]->dest_dev)
>> + return sink->pdata->out_conns[i]->dest_port;
>
> Don't we need to make sure it matches the helper ? What if there are
> multiple helpers ? e.g, a CATU connected to the ETR and CTCU ?
> Or even try the opposite ? i.e. search the helper and find the port
> matching the sink ?
>
> struct coresight_platform_data *pdata = helper->pdata;
>
> for (i = 0; i < pdata->nr_inconns; ++i)
> if (pdata->in_conns[i]->dest_dev == sink)
> return pdata->in_conns[i]->src_port;
>
> Not sure if that works with the helper device connection, James ?
Can we check the subtype of the helper device? We should only have one
CTCU helper device for each ETR.
enum coresight_dev_subtype_helper subtype;
for (i = 0; i < sink->pdata->nr_outconns; ++i) {
subtype = sink->pdata->out_conns[i]->dest_dev->subtype.helper_subtype;
if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CTCU)
return sink->pdata->out_conns[i]->dest_port;
>
>
>> + }
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static int ctcu_set_etr_traceid(struct coresight_device *csdev,
>> struct coresight_path *path,
>> + bool enable)
>> +{
>> + struct coresight_device *sink = coresight_get_sink(path);
>> + u8 traceid = path->trace_id;
>> + int port_num;
>> +
>> + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(traceid)) {
>> + dev_err(&csdev->dev, "Invalid parameters\n");
>> + return -EINVAL;
>> + }
>> +
>> + port_num = ctcu_get_active_port(sink, csdev);
>> + if (port_num < 0)
>> + return -EINVAL;
>> +
>> + dev_dbg(&csdev->dev, "traceid is %d\n", traceid);
>> +
>> + return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable);
>> +}
>> +
>> +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode
>> mode,
>> + void *data)
>> +{
>> + struct coresight_path *path = (struct coresight_path *)data;
>> +
>> + return ctcu_set_etr_traceid(csdev, path, true);
>> +}
>> +
>> +static int ctcu_disable(struct coresight_device *csdev, void *data)
>> +{
>> + struct coresight_path *path = (struct coresight_path *)data;
>> +
>> + return ctcu_set_etr_traceid(csdev, path, false);
>> +}
>> +
>> +static const struct coresight_ops_helper ctcu_helper_ops = {
>> + .enable = ctcu_enable,
>> + .disable = ctcu_disable,
>> +};
>> +
>> +static const struct coresight_ops ctcu_ops = {
>> + .helper_ops = &ctcu_helper_ops,
>> +};
>> +
>> +static int ctcu_probe(struct platform_device *pdev)
>> +{
>> + int i;
>> + void __iomem *base;
>> + struct device *dev = &pdev->dev;
>> + struct coresight_platform_data *pdata;
>> + struct ctcu_drvdata *drvdata;
>> + struct coresight_desc desc = { 0 };
>> + const struct ctcu_config *cfgs;
>> + const struct ctcu_atid_config *atid_cfg;
>> +
>> + desc.name = coresight_alloc_device_name(&ctcu_devs, dev);
>> + if (!desc.name)
>> + return -ENOMEM;
>> +
>> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> + if (!drvdata)
>> + return -ENOMEM;
>> +
>> + pdata = coresight_get_platform_data(dev);
>> + if (IS_ERR(pdata))
>> + return PTR_ERR(pdata);
>> + dev->platform_data = pdata;
>> +
>> + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
>> + if (!base)
>> + return -ENOMEM;
>> +
>> + drvdata->apb_clk = coresight_get_enable_apb_pclk(dev);
>> + if (IS_ERR(drvdata->apb_clk))
>> + return -ENODEV;
>> +
>> + cfgs = of_device_get_match_data(dev);
>> + if (cfgs) {
>> + if (cfgs->num_atid_config <= ATID_MAX_NUM) {
>> + for (i = 0; i < cfgs->num_atid_config; i++) {
>> + atid_cfg = &cfgs->atid_config[i];
>> + drvdata->atid_offset[i] = atid_cfg->atid_offset;
>> + }
>> + }
>> + }
>> +
>> + drvdata->base = base;
>> + drvdata->dev = dev;
>> + platform_set_drvdata(pdev, drvdata);
>> +
>> + desc.type = CORESIGHT_DEV_TYPE_HELPER;
>> + desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU;
>> + desc.pdata = pdata;
>> + desc.dev = dev;
>> + desc.ops = &ctcu_ops;
>
> Please set the desc.access
>
> desc.access = CSDEV_ACCESS_IOMEM(drvdata->base);
>
Sure, will do.
>> +
>> + drvdata->csdev = coresight_register(&desc);
>> + if (IS_ERR(drvdata->csdev)) {
>> + if (!IS_ERR_OR_NULL(drvdata->apb_clk))
>> + clk_put(drvdata->apb_clk);
>> +
>> + return PTR_ERR(drvdata->csdev);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void ctcu_remove(struct platform_device *pdev)
>> +{
>> + struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev);
>> +
>> + coresight_unregister(drvdata->csdev);
>> + if (!IS_ERR_OR_NULL(drvdata->apb_clk))
>> + clk_put(drvdata->apb_clk);
>
> Why isn't the clock get/put at runtime via pm_runtime calls ?
> See coresight-replicator driver for e.g.
>
Sure, will check.
>
>> +}
>> +
>> +static const struct of_device_id ctcu_match[] = {
>> + {.compatible = "qcom,sa8775p-ctcu", .data = &sa8775p_cfgs},
>> + {}
>> +};
>> +
>> +static struct platform_driver ctcu_driver = {
>> + .probe = ctcu_probe,
>> + .remove = ctcu_remove,
>> + .driver = {
>> + .name = "coresight-ctcu",
>> + .of_match_table = ctcu_match,
>> + .suppress_bind_attrs = true,
>> + },
>> +};
>> +module_platform_driver(ctcu_driver);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_DESCRIPTION("CoreSight TMC Control Unit driver");
>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/
>> hwtracing/coresight/coresight-ctcu.h
>> new file mode 100644
>> index 000000000000..9890c3da5ec8
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.h
>> @@ -0,0 +1,24 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> + */
>> +
>> +#ifndef _CORESIGHT_CTCU_H
>> +#define _CORESIGHT_CTCU_H
>> +#include "coresight-trace-id.h"
>> +
>> +/* Maximum number of supported sink devices for a single CTCU in
>> current projects. */
>> +#define ATID_MAX_NUM 2
>> +
>> +struct ctcu_drvdata {
>> + void __iomem *base;
>> + struct clk *apb_clk;
>> + phys_addr_t pbase;
>
> Where is this used ?
Sorry for the mistake, it's used by downstream code, should not be there.
>
>> + struct device *dev;
>> + struct coresight_device *csdev;
>> + raw_spinlock_t spin_lock;
>> + u32 atid_offset[ATID_MAX_NUM];
>> + /* refcnt for each traceid of each sink */
>> + u8 traceid_refcnt[ATID_MAX_NUM]
>> [CORESIGHT_TRACE_ID_RES_TOP];
>
> Hopefully u8 is sufficient, but is it ? Why don't we check this in
> "enable" path to see if we are going to overflow ?
>
I was thinking this is the refcnt for each trace_id and the repeated
enablemant for each same source device will not reach this point. So I
think it's impossible to enable one trace_id more than hunderd times?
However, I will check it according to the suggestion. Make sure there is
no overflow happened.
Thanks,
Jie
>
>
>> +};
>> +#endif
>> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
>> index 03d833a15726..55bb825d509e 100644
>> --- a/include/linux/coresight.h
>> +++ b/include/linux/coresight.h
>> @@ -71,7 +71,8 @@ enum coresight_dev_subtype_source {
>> enum coresight_dev_subtype_helper {
>> CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
>> - CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI
>> + CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI,
>> + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,
>> };
>> /**
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-24 3:32 ` Jie Gan
@ 2025-02-24 9:53 ` James Clark
2025-02-24 10:04 ` Jie Gan
2025-02-24 10:22 ` Suzuki K Poulose
1 sibling, 1 reply; 22+ messages in thread
From: James Clark @ 2025-02-24 9:53 UTC (permalink / raw)
To: Jie Gan, Suzuki K Poulose
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32, Mike Leach,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
On 24/02/2025 3:32 am, Jie Gan wrote:
>
>
> On 2/21/2025 7:39 PM, Suzuki K Poulose wrote:
>> On 17/02/2025 09:30, Jie Gan wrote:
>>> The Coresight TMC Control Unit hosts miscellaneous configuration
>>> registers
>>> which control various features related to TMC ETR sink.
>>>
>>> Based on the trace ID, which is programmed in the related CTCU ATID
>>> register of a specific ETR, trace data with that trace ID gets into
>>> the ETR buffer, while other trace data gets dropped.
>>>
>>> Enabling source device sets one bit of the ATID register based on
>>> source device's trace ID.
>>> Disabling source device resets the bit according to the source
>>> device's trace ID.
>>>
>>> Reviewed-by: James Clark <james.clark@linaro.org>
>>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>>> ---
>>> drivers/hwtracing/coresight/Kconfig | 12 +
>>> drivers/hwtracing/coresight/Makefile | 1 +
>>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++
>>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
>>> include/linux/coresight.h | 3 +-
>>> 5 files changed, 307 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>>>
>>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/
>>> coresight/Kconfig
>>> index 06f0a7594169..ecd7086a5b83 100644
>>> --- a/drivers/hwtracing/coresight/Kconfig
>>> +++ b/drivers/hwtracing/coresight/Kconfig
>>> @@ -133,6 +133,18 @@ config CORESIGHT_STM
>>> To compile this driver as a module, choose M here: the
>>> module will be called coresight-stm.
>>> +config CORESIGHT_CTCU
>>> + tristate "CoreSight TMC Control Unit driver"
>>> + depends on CORESIGHT_LINK_AND_SINK_TMC
>>> + help
>>> + This driver provides support for CoreSight TMC Control Unit
>>> + that hosts miscellaneous configuration registers. This is
>>> + primarily used for controlling the behaviors of the TMC
>>> + ETR device.
>>> +
>>> + To compile this driver as a module, choose M here: the
>>> + module will be called coresight-ctcu.
>>> +
>>> config CORESIGHT_CPU_DEBUG
>>> tristate "CoreSight CPU Debug driver"
>>> depends on ARM || ARM64
>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/
>>> hwtracing/ coresight/Makefile
>>> index 4ba478211b31..1b7869910a12 100644
>>> --- a/drivers/hwtracing/coresight/Makefile
>>> +++ b/drivers/hwtracing/coresight/Makefile
>>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-
>>> cti-platform.o \
>>> coresight-cti-sysfs.o
>>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
>>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
>>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
>>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/
>>> hwtracing/coresight/coresight-ctcu.c
>>> new file mode 100644
>>> index 000000000000..e1460a627c4d
>>> --- /dev/null
>>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
>>> @@ -0,0 +1,268 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>>> rights reserved.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/coresight.h>
>>> +#include <linux/device.h>
>>> +#include <linux/err.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/init.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/mutex.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/slab.h>
>>> +
>>> +#include "coresight-ctcu.h"
>>> +#include "coresight-priv.h"
>>> +
>>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
>>> +
>>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val),
>>> drvdata->base + offset)
>>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base
>>> + offset)
>>> +
>>> +/*
>>> + * The TMC Coresight Control Unit uses four ATID registers to
>>> control the data
>>> + * filter function based on the trace ID for each TMC ETR sink. The
>>> length of
>>> + * each ATID register is 32 bits. Therefore, the ETR has a related
>>> field in
>>> + * CTCU that is 128 bits long. Each trace ID is represented by one
>>> bit in that
>>> + * filed.
>>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
>>> + * bit5
>>> + * ------------------------------------------------------
>>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
>>> + * ------------------------------------------------------
>>> + *
>>> + * e.g. ETR0:
>>> + * 127 0 from ATID_offset for ETR0ATID0
>>> + * -------------------------
>>> + * |ATID3|ATID2|ATID1|ATID0|
>>> + */
>>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
>>> + ((traceid / 32) * 4 + atid_offset)
>>> +
>>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
>>> +#define CTCU_ATID_REG_SIZE 0x10
>>> +
>>> +struct ctcu_atid_config {
>>> + const u32 atid_offset;
>>> + const u32 port_num;
>>> +};
>>> +
>>> +struct ctcu_config {
>>> + const struct ctcu_atid_config *atid_config;
>>> + int num_atid_config;
>>> +};
>>> +
>>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
>>> + {0xf8, 0},
>>> + {0x108, 1},
>>> +};
>>> +
>>> +static const struct ctcu_config sa8775p_cfgs = {
>>> + .atid_config = sa8775p_atid_cfgs,
>>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
>>> +};
>>> +
>>> +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata,
>>> u32 reg_offset,
>>> + u8 bit, bool enable)
>>> +{
>>> + u32 val;
>>> +
>>> + CS_UNLOCK(drvdata->base);
>>> + val = ctcu_readl(drvdata, reg_offset);
>>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
>>
>> minor nit: If possible do not use the ternary operator like this. It
>> is much better readable as:
>>
>> if (enable)
>> val |= BIT(bit);
>> else
>> val &= ~BIT(bit);
>>
>
> Will do this way.
>
>>> + ctcu_writel(drvdata, val, reg_offset);
>>> + CS_LOCK(drvdata->base);
>>> +}
>>> +
>>> +/*
>>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on
>>> trace ID when enable is true.
>>> + * Reset the bit of the ATID register based on trace ID when enable
>>> is false.
>>> + *
>>> + * @csdev: coresight_device struct related to the device
>>> + * @traceid: trace ID of the source tracer.
>>> + * @port_num: port number from TMC ETR sink.
>>> + * @enable: True for set bit and false for reset bit.
>>> + *
>>> + * Returns 0 indicates success. Non-zero result means failure.
>>> + */
>>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8
>>> traceid, int port_num,
>>> + bool enable)
>>> +{
>>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>> + u32 atid_offset, reg_offset;
>>> + u8 refcnt, bit;
>>> +
>>> + atid_offset = drvdata->atid_offset[port_num];
>>> + if (atid_offset == 0)
>>> + return -EINVAL;
>>> +
>>> + bit = CTCU_ATID_REG_BIT(traceid);
>>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
>>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
>>> + return -EINVAL;
>>> +
>>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
>>> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
>>> + /* Only program the atid register when the refcnt value is 0 or
>>> 1 */
>>
>> A normal trace source won't be enabled more than once (e.g., ETM). The
>> only odd one out is the STM, which may be driven by multiple agents.
>> So this refcounting looks necessary.
>>
>
> Besides, for the TPDMs which shared the trace_id of the TPDA also need
> the refcnt. Consider we have TPDM1 and TPDM2 connected to the same TPDA
> device. Once we disable one of the TPDM without checking the refcnt, the
> filter function will be disabled for another TPDM.
>
>>> + if (enable && (++refcnt == 1))
>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>> + else if (!enable && (--refcnt == 0))
>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>
>> minor nit:
>>
>> if ((enable && !refcount++) ||
>> (!enable && --refcount))
>> ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>
>>
>
> I did (enable && (++refcnt == 1)) just because I think we only need
> program the register when refcnt is equal to 1. We dont need reprogram
> the register with same value when refcnt greater than 1. So I think it's
> better for the performance?
>
>> Also, see my comment the bottom for "refcount" being u8 .
>
> Sure, will check.
>
>>
>>
>>> +
>>> + drvdata->traceid_refcnt[port_num][traceid] = refcnt;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int ctcu_get_active_port(struct coresight_device *sink,
>>> struct coresight_device *helper)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0; i < sink->pdata->nr_outconns; ++i) {
>>> + if (sink->pdata->out_conns[i]->dest_dev)
>>> + return sink->pdata->out_conns[i]->dest_port;
>>
>> Don't we need to make sure it matches the helper ? What if there are
>> multiple helpers ? e.g, a CATU connected to the ETR and CTCU ?
>> Or even try the opposite ? i.e. search the helper and find the port
>> matching the sink ?
Good catch, looks like this should be done the opposite way around.
>>
>> struct coresight_platform_data *pdata = helper->pdata;
>>
>> for (i = 0; i < pdata->nr_inconns; ++i)
>> if (pdata->in_conns[i]->dest_dev == sink)
>> return pdata->in_conns[i]->src_port;
>>
>> Not sure if that works with the helper device connection, James ?
Yeah connections are always made in both directions.
> Can we check the subtype of the helper device? We should only have one
> CTCU helper device for each ETR.
>
> enum coresight_dev_subtype_helper subtype;
>
> for (i = 0; i < sink->pdata->nr_outconns; ++i) {
> subtype = sink->pdata->out_conns[i]->dest_dev->subtype.helper_subtype;
> if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CTCU)
> return sink->pdata->out_conns[i]->dest_port;
>
I don't think we need to check the type, just search all the CTCU's
in_conns until you find the sink.
As Suzuki says, by looking at the out_conns of the sink you might find a
different helper device. Checking that it really is connected to the
sink is probably more robust that relying on the type anyway.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-24 9:53 ` James Clark
@ 2025-02-24 10:04 ` Jie Gan
2025-02-24 10:33 ` Jie Gan
0 siblings, 1 reply; 22+ messages in thread
From: Jie Gan @ 2025-02-24 10:04 UTC (permalink / raw)
To: James Clark, Suzuki K Poulose
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32, Mike Leach,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
On 2/24/2025 5:53 PM, James Clark wrote:
>
>
> On 24/02/2025 3:32 am, Jie Gan wrote:
>>
>>
>> On 2/21/2025 7:39 PM, Suzuki K Poulose wrote:
>>> On 17/02/2025 09:30, Jie Gan wrote:
>>>> The Coresight TMC Control Unit hosts miscellaneous configuration
>>>> registers
>>>> which control various features related to TMC ETR sink.
>>>>
>>>> Based on the trace ID, which is programmed in the related CTCU ATID
>>>> register of a specific ETR, trace data with that trace ID gets into
>>>> the ETR buffer, while other trace data gets dropped.
>>>>
>>>> Enabling source device sets one bit of the ATID register based on
>>>> source device's trace ID.
>>>> Disabling source device resets the bit according to the source
>>>> device's trace ID.
>>>>
>>>> Reviewed-by: James Clark <james.clark@linaro.org>
>>>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>>>> ---
>>>> drivers/hwtracing/coresight/Kconfig | 12 +
>>>> drivers/hwtracing/coresight/Makefile | 1 +
>>>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++
>>>> ++++
>>>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
>>>> include/linux/coresight.h | 3 +-
>>>> 5 files changed, 307 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>>>>
>>>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/
>>>> hwtracing/ coresight/Kconfig
>>>> index 06f0a7594169..ecd7086a5b83 100644
>>>> --- a/drivers/hwtracing/coresight/Kconfig
>>>> +++ b/drivers/hwtracing/coresight/Kconfig
>>>> @@ -133,6 +133,18 @@ config CORESIGHT_STM
>>>> To compile this driver as a module, choose M here: the
>>>> module will be called coresight-stm.
>>>> +config CORESIGHT_CTCU
>>>> + tristate "CoreSight TMC Control Unit driver"
>>>> + depends on CORESIGHT_LINK_AND_SINK_TMC
>>>> + help
>>>> + This driver provides support for CoreSight TMC Control Unit
>>>> + that hosts miscellaneous configuration registers. This is
>>>> + primarily used for controlling the behaviors of the TMC
>>>> + ETR device.
>>>> +
>>>> + To compile this driver as a module, choose M here: the
>>>> + module will be called coresight-ctcu.
>>>> +
>>>> config CORESIGHT_CPU_DEBUG
>>>> tristate "CoreSight CPU Debug driver"
>>>> depends on ARM || ARM64
>>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/
>>>> hwtracing/ coresight/Makefile
>>>> index 4ba478211b31..1b7869910a12 100644
>>>> --- a/drivers/hwtracing/coresight/Makefile
>>>> +++ b/drivers/hwtracing/coresight/Makefile
>>>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-
>>>> cti-platform.o \
>>>> coresight-cti-sysfs.o
>>>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
>>>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
>>>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
>>>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/
>>>> hwtracing/coresight/coresight-ctcu.c
>>>> new file mode 100644
>>>> index 000000000000..e1460a627c4d
>>>> --- /dev/null
>>>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
>>>> @@ -0,0 +1,268 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +/*
>>>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>>>> rights reserved.
>>>> + */
>>>> +
>>>> +#include <linux/clk.h>
>>>> +#include <linux/coresight.h>
>>>> +#include <linux/device.h>
>>>> +#include <linux/err.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/init.h>
>>>> +#include <linux/io.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/mutex.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/slab.h>
>>>> +
>>>> +#include "coresight-ctcu.h"
>>>> +#include "coresight-priv.h"
>>>> +
>>>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
>>>> +
>>>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val),
>>>> drvdata->base + offset)
>>>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata-
>>>> >base + offset)
>>>> +
>>>> +/*
>>>> + * The TMC Coresight Control Unit uses four ATID registers to
>>>> control the data
>>>> + * filter function based on the trace ID for each TMC ETR sink. The
>>>> length of
>>>> + * each ATID register is 32 bits. Therefore, the ETR has a related
>>>> field in
>>>> + * CTCU that is 128 bits long. Each trace ID is represented by one
>>>> bit in that
>>>> + * filed.
>>>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
>>>> + * bit5
>>>> + * ------------------------------------------------------
>>>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
>>>> + * ------------------------------------------------------
>>>> + *
>>>> + * e.g. ETR0:
>>>> + * 127 0 from ATID_offset for ETR0ATID0
>>>> + * -------------------------
>>>> + * |ATID3|ATID2|ATID1|ATID0|
>>>> + */
>>>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
>>>> + ((traceid / 32) * 4 + atid_offset)
>>>> +
>>>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
>>>> +#define CTCU_ATID_REG_SIZE 0x10
>>>> +
>>>> +struct ctcu_atid_config {
>>>> + const u32 atid_offset;
>>>> + const u32 port_num;
>>>> +};
>>>> +
>>>> +struct ctcu_config {
>>>> + const struct ctcu_atid_config *atid_config;
>>>> + int num_atid_config;
>>>> +};
>>>> +
>>>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
>>>> + {0xf8, 0},
>>>> + {0x108, 1},
>>>> +};
>>>> +
>>>> +static const struct ctcu_config sa8775p_cfgs = {
>>>> + .atid_config = sa8775p_atid_cfgs,
>>>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
>>>> +};
>>>> +
>>>> +static void ctcu_program_atid_register(struct ctcu_drvdata
>>>> *drvdata, u32 reg_offset,
>>>> + u8 bit, bool enable)
>>>> +{
>>>> + u32 val;
>>>> +
>>>> + CS_UNLOCK(drvdata->base);
>>>> + val = ctcu_readl(drvdata, reg_offset);
>>>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
>>>
>>> minor nit: If possible do not use the ternary operator like this. It
>>> is much better readable as:
>>>
>>> if (enable)
>>> val |= BIT(bit);
>>> else
>>> val &= ~BIT(bit);
>>>
>>
>> Will do this way.
>>
>>>> + ctcu_writel(drvdata, val, reg_offset);
>>>> + CS_LOCK(drvdata->base);
>>>> +}
>>>> +
>>>> +/*
>>>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on
>>>> trace ID when enable is true.
>>>> + * Reset the bit of the ATID register based on trace ID when enable
>>>> is false.
>>>> + *
>>>> + * @csdev: coresight_device struct related to the device
>>>> + * @traceid: trace ID of the source tracer.
>>>> + * @port_num: port number from TMC ETR sink.
>>>> + * @enable: True for set bit and false for reset bit.
>>>> + *
>>>> + * Returns 0 indicates success. Non-zero result means failure.
>>>> + */
>>>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev,
>>>> u8 traceid, int port_num,
>>>> + bool enable)
>>>> +{
>>>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>>> + u32 atid_offset, reg_offset;
>>>> + u8 refcnt, bit;
>>>> +
>>>> + atid_offset = drvdata->atid_offset[port_num];
>>>> + if (atid_offset == 0)
>>>> + return -EINVAL;
>>>> +
>>>> + bit = CTCU_ATID_REG_BIT(traceid);
>>>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
>>>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
>>>> + return -EINVAL;
>>>> +
>>>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
>>>> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
>>>> + /* Only program the atid register when the refcnt value is 0 or
>>>> 1 */
>>>
>>> A normal trace source won't be enabled more than once (e.g., ETM).
>>> The only odd one out is the STM, which may be driven by multiple agents.
>>> So this refcounting looks necessary.
>>>
>>
>> Besides, for the TPDMs which shared the trace_id of the TPDA also need
>> the refcnt. Consider we have TPDM1 and TPDM2 connected to the same
>> TPDA device. Once we disable one of the TPDM without checking the
>> refcnt, the filter function will be disabled for another TPDM.
>>
>>>> + if (enable && (++refcnt == 1))
>>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>> + else if (!enable && (--refcnt == 0))
>>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>
>>> minor nit:
>>>
>>> if ((enable && !refcount++) ||
>>> (!enable && --refcount))
>>> ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>
>>>
>>
>> I did (enable && (++refcnt == 1)) just because I think we only need
>> program the register when refcnt is equal to 1. We dont need reprogram
>> the register with same value when refcnt greater than 1. So I think
>> it's better for the performance?
>>
>>> Also, see my comment the bottom for "refcount" being u8 .
>>
>> Sure, will check.
>>
>>>
>>>
>>>> +
>>>> + drvdata->traceid_refcnt[port_num][traceid] = refcnt;
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int ctcu_get_active_port(struct coresight_device *sink,
>>>> struct coresight_device *helper)
>>>> +{
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < sink->pdata->nr_outconns; ++i) {
>>>> + if (sink->pdata->out_conns[i]->dest_dev)
>>>> + return sink->pdata->out_conns[i]->dest_port;
>>>
>>> Don't we need to make sure it matches the helper ? What if there are
>>> multiple helpers ? e.g, a CATU connected to the ETR and CTCU ?
>>> Or even try the opposite ? i.e. search the helper and find the port
>>> matching the sink ?
>
> Good catch, looks like this should be done the opposite way around.
>
>>>
>>> struct coresight_platform_data *pdata = helper->pdata;
>>>
>>> for (i = 0; i < pdata->nr_inconns; ++i)
>>> if (pdata->in_conns[i]->dest_dev == sink)
>>> return pdata->in_conns[i]->src_port;
>>>
>>> Not sure if that works with the helper device connection, James ?
>
> Yeah connections are always made in both directions.
>
>> Can we check the subtype of the helper device? We should only have one
>> CTCU helper device for each ETR.
>>
>> enum coresight_dev_subtype_helper subtype;
>>
>> for (i = 0; i < sink->pdata->nr_outconns; ++i) {
>> subtype = sink->pdata->out_conns[i]->dest_dev-
>> >subtype.helper_subtype;
>> if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CTCU)
>> return sink->pdata->out_conns[i]->dest_port;
>>
>
> I don't think we need to check the type, just search all the CTCU's
> in_conns until you find the sink.
>
> As Suzuki says, by looking at the out_conns of the sink you might find a
> different helper device. Checking that it really is connected to the
> sink is probably more robust that relying on the type anyway.
>
Hi James,
Thanks for explaination, will update per Suzuki's suggestion.
Jie
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-24 3:32 ` Jie Gan
2025-02-24 9:53 ` James Clark
@ 2025-02-24 10:22 ` Suzuki K Poulose
2025-02-24 10:26 ` Jie Gan
1 sibling, 1 reply; 22+ messages in thread
From: Suzuki K Poulose @ 2025-02-24 10:22 UTC (permalink / raw)
To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 24/02/2025 03:32, Jie Gan wrote:
>
>
> On 2/21/2025 7:39 PM, Suzuki K Poulose wrote:
>> On 17/02/2025 09:30, Jie Gan wrote:
>>> The Coresight TMC Control Unit hosts miscellaneous configuration
>>> registers
>>> which control various features related to TMC ETR sink.
>>>
>>> Based on the trace ID, which is programmed in the related CTCU ATID
>>> register of a specific ETR, trace data with that trace ID gets into
>>> the ETR buffer, while other trace data gets dropped.
>>>
>>> Enabling source device sets one bit of the ATID register based on
>>> source device's trace ID.
>>> Disabling source device resets the bit according to the source
>>> device's trace ID.
>>>
>>> Reviewed-by: James Clark <james.clark@linaro.org>
>>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>>> ---
>>> drivers/hwtracing/coresight/Kconfig | 12 +
>>> drivers/hwtracing/coresight/Makefile | 1 +
>>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++
>>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
>>> include/linux/coresight.h | 3 +-
>>> 5 files changed, 307 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>>>
>>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/
>>> coresight/Kconfig
>>> index 06f0a7594169..ecd7086a5b83 100644
>>> --- a/drivers/hwtracing/coresight/Kconfig
>>> +++ b/drivers/hwtracing/coresight/Kconfig
>>> @@ -133,6 +133,18 @@ config CORESIGHT_STM
>>> To compile this driver as a module, choose M here: the
>>> module will be called coresight-stm.
>>> +config CORESIGHT_CTCU
>>> + tristate "CoreSight TMC Control Unit driver"
>>> + depends on CORESIGHT_LINK_AND_SINK_TMC
>>> + help
>>> + This driver provides support for CoreSight TMC Control Unit
>>> + that hosts miscellaneous configuration registers. This is
>>> + primarily used for controlling the behaviors of the TMC
>>> + ETR device.
>>> +
>>> + To compile this driver as a module, choose M here: the
>>> + module will be called coresight-ctcu.
>>> +
>>> config CORESIGHT_CPU_DEBUG
>>> tristate "CoreSight CPU Debug driver"
>>> depends on ARM || ARM64
>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/
>>> hwtracing/ coresight/Makefile
>>> index 4ba478211b31..1b7869910a12 100644
>>> --- a/drivers/hwtracing/coresight/Makefile
>>> +++ b/drivers/hwtracing/coresight/Makefile
>>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-
>>> cti-platform.o \
>>> coresight-cti-sysfs.o
>>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
>>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
>>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
>>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/
>>> hwtracing/coresight/coresight-ctcu.c
>>> new file mode 100644
>>> index 000000000000..e1460a627c4d
>>> --- /dev/null
>>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
>>> @@ -0,0 +1,268 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>>> rights reserved.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/coresight.h>
>>> +#include <linux/device.h>
>>> +#include <linux/err.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/init.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/mutex.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/slab.h>
>>> +
>>> +#include "coresight-ctcu.h"
>>> +#include "coresight-priv.h"
>>> +
>>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
>>> +
>>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val),
>>> drvdata->base + offset)
>>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base
>>> + offset)
>>> +
>>> +/*
>>> + * The TMC Coresight Control Unit uses four ATID registers to
>>> control the data
>>> + * filter function based on the trace ID for each TMC ETR sink. The
>>> length of
>>> + * each ATID register is 32 bits. Therefore, the ETR has a related
>>> field in
>>> + * CTCU that is 128 bits long. Each trace ID is represented by one
>>> bit in that
>>> + * filed.
>>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
>>> + * bit5
>>> + * ------------------------------------------------------
>>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
>>> + * ------------------------------------------------------
>>> + *
>>> + * e.g. ETR0:
>>> + * 127 0 from ATID_offset for ETR0ATID0
>>> + * -------------------------
>>> + * |ATID3|ATID2|ATID1|ATID0|
>>> + */
>>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
>>> + ((traceid / 32) * 4 + atid_offset)
>>> +
>>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
>>> +#define CTCU_ATID_REG_SIZE 0x10
>>> +
>>> +struct ctcu_atid_config {
>>> + const u32 atid_offset;
>>> + const u32 port_num;
>>> +};
>>> +
>>> +struct ctcu_config {
>>> + const struct ctcu_atid_config *atid_config;
>>> + int num_atid_config;
>>> +};
>>> +
>>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
>>> + {0xf8, 0},
>>> + {0x108, 1},
>>> +};
>>> +
>>> +static const struct ctcu_config sa8775p_cfgs = {
>>> + .atid_config = sa8775p_atid_cfgs,
>>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
>>> +};
>>> +
>>> +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata,
>>> u32 reg_offset,
>>> + u8 bit, bool enable)
>>> +{
>>> + u32 val;
>>> +
>>> + CS_UNLOCK(drvdata->base);
>>> + val = ctcu_readl(drvdata, reg_offset);
>>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
>>
>> minor nit: If possible do not use the ternary operator like this. It
>> is much better readable as:
>>
>> if (enable)
>> val |= BIT(bit);
>> else
>> val &= ~BIT(bit);
>>
>
> Will do this way.
>
>>> + ctcu_writel(drvdata, val, reg_offset);
>>> + CS_LOCK(drvdata->base);
>>> +}
>>> +
>>> +/*
>>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on
>>> trace ID when enable is true.
>>> + * Reset the bit of the ATID register based on trace ID when enable
>>> is false.
>>> + *
>>> + * @csdev: coresight_device struct related to the device
>>> + * @traceid: trace ID of the source tracer.
>>> + * @port_num: port number from TMC ETR sink.
>>> + * @enable: True for set bit and false for reset bit.
>>> + *
>>> + * Returns 0 indicates success. Non-zero result means failure.
>>> + */
>>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8
>>> traceid, int port_num,
>>> + bool enable)
>>> +{
>>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>> + u32 atid_offset, reg_offset;
>>> + u8 refcnt, bit;
>>> +
>>> + atid_offset = drvdata->atid_offset[port_num];
>>> + if (atid_offset == 0)
>>> + return -EINVAL;
>>> +
>>> + bit = CTCU_ATID_REG_BIT(traceid);
>>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
>>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
>>> + return -EINVAL;
>>> +
>>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
>>> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
>>> + /* Only program the atid register when the refcnt value is 0 or
>>> 1 */
>>
>> A normal trace source won't be enabled more than once (e.g., ETM). The
>> only odd one out is the STM, which may be driven by multiple agents.
>> So this refcounting looks necessary.
>>
>
> Besides, for the TPDMs which shared the trace_id of the TPDA also need
> the refcnt. Consider we have TPDM1 and TPDM2 connected to the same TPDA
> device. Once we disable one of the TPDM without checking the refcnt, the
> filter function will be disabled for another TPDM.
>
>>> + if (enable && (++refcnt == 1))
>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>> + else if (!enable && (--refcnt == 0))
>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>
>> minor nit:
>>
>> if ((enable && !refcount++) ||
>> (!enable && --refcount))
>> ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>
>>
>
> I did (enable && (++refcnt == 1)) just because I think we only need
> program the register when refcnt is equal to 1. We dont need reprogram
> the register with same value when refcnt greater than 1. So I think it's
> better for the performance?
The code above is similar to yours. It would "set" only for the first
time, when
enable == 0, refcount == 0 now, but will be incremented to 1.
Suzuki
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-24 10:22 ` Suzuki K Poulose
@ 2025-02-24 10:26 ` Jie Gan
0 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-24 10:26 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32
On 2/24/2025 6:22 PM, Suzuki K Poulose wrote:
> On 24/02/2025 03:32, Jie Gan wrote:
>>
>>
>> On 2/21/2025 7:39 PM, Suzuki K Poulose wrote:
>>> On 17/02/2025 09:30, Jie Gan wrote:
>>>> The Coresight TMC Control Unit hosts miscellaneous configuration
>>>> registers
>>>> which control various features related to TMC ETR sink.
>>>>
>>>> Based on the trace ID, which is programmed in the related CTCU ATID
>>>> register of a specific ETR, trace data with that trace ID gets into
>>>> the ETR buffer, while other trace data gets dropped.
>>>>
>>>> Enabling source device sets one bit of the ATID register based on
>>>> source device's trace ID.
>>>> Disabling source device resets the bit according to the source
>>>> device's trace ID.
>>>>
>>>> Reviewed-by: James Clark <james.clark@linaro.org>
>>>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>>>> ---
>>>> drivers/hwtracing/coresight/Kconfig | 12 +
>>>> drivers/hwtracing/coresight/Makefile | 1 +
>>>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++
>>>> ++++
>>>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
>>>> include/linux/coresight.h | 3 +-
>>>> 5 files changed, 307 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>>>>
>>>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/
>>>> hwtracing/ coresight/Kconfig
>>>> index 06f0a7594169..ecd7086a5b83 100644
>>>> --- a/drivers/hwtracing/coresight/Kconfig
>>>> +++ b/drivers/hwtracing/coresight/Kconfig
>>>> @@ -133,6 +133,18 @@ config CORESIGHT_STM
>>>> To compile this driver as a module, choose M here: the
>>>> module will be called coresight-stm.
>>>> +config CORESIGHT_CTCU
>>>> + tristate "CoreSight TMC Control Unit driver"
>>>> + depends on CORESIGHT_LINK_AND_SINK_TMC
>>>> + help
>>>> + This driver provides support for CoreSight TMC Control Unit
>>>> + that hosts miscellaneous configuration registers. This is
>>>> + primarily used for controlling the behaviors of the TMC
>>>> + ETR device.
>>>> +
>>>> + To compile this driver as a module, choose M here: the
>>>> + module will be called coresight-ctcu.
>>>> +
>>>> config CORESIGHT_CPU_DEBUG
>>>> tristate "CoreSight CPU Debug driver"
>>>> depends on ARM || ARM64
>>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/
>>>> hwtracing/ coresight/Makefile
>>>> index 4ba478211b31..1b7869910a12 100644
>>>> --- a/drivers/hwtracing/coresight/Makefile
>>>> +++ b/drivers/hwtracing/coresight/Makefile
>>>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-
>>>> cti-platform.o \
>>>> coresight-cti-sysfs.o
>>>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
>>>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
>>>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
>>>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/
>>>> hwtracing/coresight/coresight-ctcu.c
>>>> new file mode 100644
>>>> index 000000000000..e1460a627c4d
>>>> --- /dev/null
>>>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
>>>> @@ -0,0 +1,268 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +/*
>>>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>>>> rights reserved.
>>>> + */
>>>> +
>>>> +#include <linux/clk.h>
>>>> +#include <linux/coresight.h>
>>>> +#include <linux/device.h>
>>>> +#include <linux/err.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/init.h>
>>>> +#include <linux/io.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/mutex.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/slab.h>
>>>> +
>>>> +#include "coresight-ctcu.h"
>>>> +#include "coresight-priv.h"
>>>> +
>>>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
>>>> +
>>>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val),
>>>> drvdata->base + offset)
>>>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata-
>>>> >base + offset)
>>>> +
>>>> +/*
>>>> + * The TMC Coresight Control Unit uses four ATID registers to
>>>> control the data
>>>> + * filter function based on the trace ID for each TMC ETR sink. The
>>>> length of
>>>> + * each ATID register is 32 bits. Therefore, the ETR has a related
>>>> field in
>>>> + * CTCU that is 128 bits long. Each trace ID is represented by one
>>>> bit in that
>>>> + * filed.
>>>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
>>>> + * bit5
>>>> + * ------------------------------------------------------
>>>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
>>>> + * ------------------------------------------------------
>>>> + *
>>>> + * e.g. ETR0:
>>>> + * 127 0 from ATID_offset for ETR0ATID0
>>>> + * -------------------------
>>>> + * |ATID3|ATID2|ATID1|ATID0|
>>>> + */
>>>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
>>>> + ((traceid / 32) * 4 + atid_offset)
>>>> +
>>>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
>>>> +#define CTCU_ATID_REG_SIZE 0x10
>>>> +
>>>> +struct ctcu_atid_config {
>>>> + const u32 atid_offset;
>>>> + const u32 port_num;
>>>> +};
>>>> +
>>>> +struct ctcu_config {
>>>> + const struct ctcu_atid_config *atid_config;
>>>> + int num_atid_config;
>>>> +};
>>>> +
>>>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
>>>> + {0xf8, 0},
>>>> + {0x108, 1},
>>>> +};
>>>> +
>>>> +static const struct ctcu_config sa8775p_cfgs = {
>>>> + .atid_config = sa8775p_atid_cfgs,
>>>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
>>>> +};
>>>> +
>>>> +static void ctcu_program_atid_register(struct ctcu_drvdata
>>>> *drvdata, u32 reg_offset,
>>>> + u8 bit, bool enable)
>>>> +{
>>>> + u32 val;
>>>> +
>>>> + CS_UNLOCK(drvdata->base);
>>>> + val = ctcu_readl(drvdata, reg_offset);
>>>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
>>>
>>> minor nit: If possible do not use the ternary operator like this. It
>>> is much better readable as:
>>>
>>> if (enable)
>>> val |= BIT(bit);
>>> else
>>> val &= ~BIT(bit);
>>>
>>
>> Will do this way.
>>
>>>> + ctcu_writel(drvdata, val, reg_offset);
>>>> + CS_LOCK(drvdata->base);
>>>> +}
>>>> +
>>>> +/*
>>>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on
>>>> trace ID when enable is true.
>>>> + * Reset the bit of the ATID register based on trace ID when enable
>>>> is false.
>>>> + *
>>>> + * @csdev: coresight_device struct related to the device
>>>> + * @traceid: trace ID of the source tracer.
>>>> + * @port_num: port number from TMC ETR sink.
>>>> + * @enable: True for set bit and false for reset bit.
>>>> + *
>>>> + * Returns 0 indicates success. Non-zero result means failure.
>>>> + */
>>>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev,
>>>> u8 traceid, int port_num,
>>>> + bool enable)
>>>> +{
>>>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>>> + u32 atid_offset, reg_offset;
>>>> + u8 refcnt, bit;
>>>> +
>>>> + atid_offset = drvdata->atid_offset[port_num];
>>>> + if (atid_offset == 0)
>>>> + return -EINVAL;
>>>> +
>>>> + bit = CTCU_ATID_REG_BIT(traceid);
>>>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
>>>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
>>>> + return -EINVAL;
>>>> +
>>>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
>>>> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
>>>> + /* Only program the atid register when the refcnt value is 0 or
>>>> 1 */
>>>
>>> A normal trace source won't be enabled more than once (e.g., ETM).
>>> The only odd one out is the STM, which may be driven by multiple agents.
>>> So this refcounting looks necessary.
>>>
>>
>> Besides, for the TPDMs which shared the trace_id of the TPDA also need
>> the refcnt. Consider we have TPDM1 and TPDM2 connected to the same
>> TPDA device. Once we disable one of the TPDM without checking the
>> refcnt, the filter function will be disabled for another TPDM.
>>
>>>> + if (enable && (++refcnt == 1))
>>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>> + else if (!enable && (--refcnt == 0))
>>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>
>>> minor nit:
>>>
>>> if ((enable && !refcount++) ||
>>> (!enable && --refcount))
>>> ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>
>>>
>>
>> I did (enable && (++refcnt == 1)) just because I think we only need
>> program the register when refcnt is equal to 1. We dont need reprogram
>> the register with same value when refcnt greater than 1. So I think
>> it's better for the performance?
>
> The code above is similar to yours. It would "set" only for the first
> time, when
>
> enable == 0, refcount == 0 now, but will be incremented to 1.
>
Hi Suzuki,
Thanks for expalaination, got your point, just missed !refcnt++, plus 1
after !refcnt.
Jie
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver
2025-02-24 10:04 ` Jie Gan
@ 2025-02-24 10:33 ` Jie Gan
0 siblings, 0 replies; 22+ messages in thread
From: Jie Gan @ 2025-02-24 10:33 UTC (permalink / raw)
To: James Clark, Suzuki K Poulose
Cc: Tingwei Zhang, Jinlong Mao, coresight, linux-arm-kernel,
linux-kernel, devicetree, linux-arm-msm, linux-stm32, Mike Leach,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
On 2/24/2025 6:04 PM, Jie Gan wrote:
>
>
> On 2/24/2025 5:53 PM, James Clark wrote:
>>
>>
>> On 24/02/2025 3:32 am, Jie Gan wrote:
>>>
>>>
>>> On 2/21/2025 7:39 PM, Suzuki K Poulose wrote:
>>>> On 17/02/2025 09:30, Jie Gan wrote:
>>>>> The Coresight TMC Control Unit hosts miscellaneous configuration
>>>>> registers
>>>>> which control various features related to TMC ETR sink.
>>>>>
>>>>> Based on the trace ID, which is programmed in the related CTCU ATID
>>>>> register of a specific ETR, trace data with that trace ID gets into
>>>>> the ETR buffer, while other trace data gets dropped.
>>>>>
>>>>> Enabling source device sets one bit of the ATID register based on
>>>>> source device's trace ID.
>>>>> Disabling source device resets the bit according to the source
>>>>> device's trace ID.
>>>>>
>>>>> Reviewed-by: James Clark <james.clark@linaro.org>
>>>>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>>>>> ---
>>>>> drivers/hwtracing/coresight/Kconfig | 12 +
>>>>> drivers/hwtracing/coresight/Makefile | 1 +
>>>>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 ++++++++++++++
>>>>> + ++++
>>>>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++
>>>>> include/linux/coresight.h | 3 +-
>>>>> 5 files changed, 307 insertions(+), 1 deletion(-)
>>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
>>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>>>>>
>>>>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/
>>>>> hwtracing/ coresight/Kconfig
>>>>> index 06f0a7594169..ecd7086a5b83 100644
>>>>> --- a/drivers/hwtracing/coresight/Kconfig
>>>>> +++ b/drivers/hwtracing/coresight/Kconfig
>>>>> @@ -133,6 +133,18 @@ config CORESIGHT_STM
>>>>> To compile this driver as a module, choose M here: the
>>>>> module will be called coresight-stm.
>>>>> +config CORESIGHT_CTCU
>>>>> + tristate "CoreSight TMC Control Unit driver"
>>>>> + depends on CORESIGHT_LINK_AND_SINK_TMC
>>>>> + help
>>>>> + This driver provides support for CoreSight TMC Control Unit
>>>>> + that hosts miscellaneous configuration registers. This is
>>>>> + primarily used for controlling the behaviors of the TMC
>>>>> + ETR device.
>>>>> +
>>>>> + To compile this driver as a module, choose M here: the
>>>>> + module will be called coresight-ctcu.
>>>>> +
>>>>> config CORESIGHT_CPU_DEBUG
>>>>> tristate "CoreSight CPU Debug driver"
>>>>> depends on ARM || ARM64
>>>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/
>>>>> hwtracing/ coresight/Makefile
>>>>> index 4ba478211b31..1b7869910a12 100644
>>>>> --- a/drivers/hwtracing/coresight/Makefile
>>>>> +++ b/drivers/hwtracing/coresight/Makefile
>>>>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o
>>>>> coresight- cti-platform.o \
>>>>> coresight-cti-sysfs.o
>>>>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
>>>>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
>>>>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
>>>>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/
>>>>> drivers/ hwtracing/coresight/coresight-ctcu.c
>>>>> new file mode 100644
>>>>> index 000000000000..e1460a627c4d
>>>>> --- /dev/null
>>>>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c
>>>>> @@ -0,0 +1,268 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>> +/*
>>>>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All
>>>>> rights reserved.
>>>>> + */
>>>>> +
>>>>> +#include <linux/clk.h>
>>>>> +#include <linux/coresight.h>
>>>>> +#include <linux/device.h>
>>>>> +#include <linux/err.h>
>>>>> +#include <linux/kernel.h>
>>>>> +#include <linux/init.h>
>>>>> +#include <linux/io.h>
>>>>> +#include <linux/module.h>
>>>>> +#include <linux/mutex.h>
>>>>> +#include <linux/of.h>
>>>>> +#include <linux/platform_device.h>
>>>>> +#include <linux/slab.h>
>>>>> +
>>>>> +#include "coresight-ctcu.h"
>>>>> +#include "coresight-priv.h"
>>>>> +
>>>>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
>>>>> +
>>>>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val),
>>>>> drvdata->base + offset)
>>>>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata-
>>>>> >base + offset)
>>>>> +
>>>>> +/*
>>>>> + * The TMC Coresight Control Unit uses four ATID registers to
>>>>> control the data
>>>>> + * filter function based on the trace ID for each TMC ETR sink.
>>>>> The length of
>>>>> + * each ATID register is 32 bits. Therefore, the ETR has a related
>>>>> field in
>>>>> + * CTCU that is 128 bits long. Each trace ID is represented by one
>>>>> bit in that
>>>>> + * filed.
>>>>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5
>>>>> + * bit5
>>>>> + * ------------------------------------------------------
>>>>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0|
>>>>> + * ------------------------------------------------------
>>>>> + *
>>>>> + * e.g. ETR0:
>>>>> + * 127 0 from ATID_offset for ETR0ATID0
>>>>> + * -------------------------
>>>>> + * |ATID3|ATID2|ATID1|ATID0|
>>>>> + */
>>>>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \
>>>>> + ((traceid / 32) * 4 + atid_offset)
>>>>> +
>>>>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
>>>>> +#define CTCU_ATID_REG_SIZE 0x10
>>>>> +
>>>>> +struct ctcu_atid_config {
>>>>> + const u32 atid_offset;
>>>>> + const u32 port_num;
>>>>> +};
>>>>> +
>>>>> +struct ctcu_config {
>>>>> + const struct ctcu_atid_config *atid_config;
>>>>> + int num_atid_config;
>>>>> +};
>>>>> +
>>>>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = {
>>>>> + {0xf8, 0},
>>>>> + {0x108, 1},
>>>>> +};
>>>>> +
>>>>> +static const struct ctcu_config sa8775p_cfgs = {
>>>>> + .atid_config = sa8775p_atid_cfgs,
>>>>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs),
>>>>> +};
>>>>> +
>>>>> +static void ctcu_program_atid_register(struct ctcu_drvdata
>>>>> *drvdata, u32 reg_offset,
>>>>> + u8 bit, bool enable)
>>>>> +{
>>>>> + u32 val;
>>>>> +
>>>>> + CS_UNLOCK(drvdata->base);
>>>>> + val = ctcu_readl(drvdata, reg_offset);
>>>>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit));
>>>>
>>>> minor nit: If possible do not use the ternary operator like this. It
>>>> is much better readable as:
>>>>
>>>> if (enable)
>>>> val |= BIT(bit);
>>>> else
>>>> val &= ~BIT(bit);
>>>>
>>>
>>> Will do this way.
>>>
>>>>> + ctcu_writel(drvdata, val, reg_offset);
>>>>> + CS_LOCK(drvdata->base);
>>>>> +}
>>>>> +
>>>>> +/*
>>>>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on
>>>>> trace ID when enable is true.
>>>>> + * Reset the bit of the ATID register based on trace ID when
>>>>> enable is false.
>>>>> + *
>>>>> + * @csdev: coresight_device struct related to the device
>>>>> + * @traceid: trace ID of the source tracer.
>>>>> + * @port_num: port number from TMC ETR sink.
>>>>> + * @enable: True for set bit and false for reset bit.
>>>>> + *
>>>>> + * Returns 0 indicates success. Non-zero result means failure.
>>>>> + */
>>>>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev,
>>>>> u8 traceid, int port_num,
>>>>> + bool enable)
>>>>> +{
>>>>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev-
>>>>> >dev.parent);
>>>>> + u32 atid_offset, reg_offset;
>>>>> + u8 refcnt, bit;
>>>>> +
>>>>> + atid_offset = drvdata->atid_offset[port_num];
>>>>> + if (atid_offset == 0)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + bit = CTCU_ATID_REG_BIT(traceid);
>>>>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);
>>>>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock);
>>>>> + refcnt = drvdata->traceid_refcnt[port_num][traceid];
>>>>> + /* Only program the atid register when the refcnt value is 0
>>>>> or 1 */
>>>>
>>>> A normal trace source won't be enabled more than once (e.g., ETM).
>>>> The only odd one out is the STM, which may be driven by multiple
>>>> agents.
>>>> So this refcounting looks necessary.
>>>>
>>>
>>> Besides, for the TPDMs which shared the trace_id of the TPDA also
>>> need the refcnt. Consider we have TPDM1 and TPDM2 connected to the
>>> same TPDA device. Once we disable one of the TPDM without checking
>>> the refcnt, the filter function will be disabled for another TPDM.
>>>
>>>>> + if (enable && (++refcnt == 1))
>>>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>>> + else if (!enable && (--refcnt == 0))
>>>>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>>
>>>> minor nit:
>>>>
>>>> if ((enable && !refcount++) ||
>>>> (!enable && --refcount))
>>>> ctcu_program_atid_register(drvdata, reg_offset, bit, enable);
>>>>
>>>>
>>>
>>> I did (enable && (++refcnt == 1)) just because I think we only need
>>> program the register when refcnt is equal to 1. We dont need
>>> reprogram the register with same value when refcnt greater than 1. So
>>> I think it's better for the performance?
>>>
>>>> Also, see my comment the bottom for "refcount" being u8 .
>>>
>>> Sure, will check.
>>>
>>>>
>>>>
>>>>> +
>>>>> + drvdata->traceid_refcnt[port_num][traceid] = refcnt;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int ctcu_get_active_port(struct coresight_device *sink,
>>>>> struct coresight_device *helper)
>>>>> +{
>>>>> + int i;
>>>>> +
>>>>> + for (i = 0; i < sink->pdata->nr_outconns; ++i) {
>>>>> + if (sink->pdata->out_conns[i]->dest_dev)
>>>>> + return sink->pdata->out_conns[i]->dest_port;
>>>>
>>>> Don't we need to make sure it matches the helper ? What if there are
>>>> multiple helpers ? e.g, a CATU connected to the ETR and CTCU ?
>>>> Or even try the opposite ? i.e. search the helper and find the port
>>>> matching the sink ?
>>
>> Good catch, looks like this should be done the opposite way around.
>>
>>>>
>>>> struct coresight_platform_data *pdata = helper->pdata;
>>>>
>>>> for (i = 0; i < pdata->nr_inconns; ++i)
>>>> if (pdata->in_conns[i]->dest_dev == sink)
>>>> return pdata->in_conns[i]->src_port;
>>>>
>>>> Not sure if that works with the helper device connection, James ?
>>
>> Yeah connections are always made in both directions.
>>
>>> Can we check the subtype of the helper device? We should only have
>>> one CTCU helper device for each ETR.
>>>
>>> enum coresight_dev_subtype_helper subtype;
>>>
>>> for (i = 0; i < sink->pdata->nr_outconns; ++i) {
>>> subtype = sink->pdata->out_conns[i]->dest_dev-
>>> >subtype.helper_subtype;
>>> if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CTCU)
>>> return sink->pdata->out_conns[i]->dest_port;
>>>
>>
>> I don't think we need to check the type, just search all the CTCU's
>> in_conns until you find the sink.
>>
>> As Suzuki says, by looking at the out_conns of the sink you might find
>> a different helper device. Checking that it really is connected to the
>> sink is probably more robust that relying on the type anyway.
>>
>
> Hi James,
>
> Thanks for explaination, will update per Suzuki's suggestion.
>
> Jie
>
Hi Suzuki James,
Just for confirm, the updated codes from opposite way should be:
struct coresight_platform_data *pdata = helper->pdata;
for (i = 0; i < pdata->nr_inconns; ++i)
if (pdata->in_conns[i]->src_dev == sink)
return pdata->in_conns[i]->dest_port;
Just because the direction when create connection is sink->helper, am right?
-------------------------- ---------------------------
src_dev(sink) src_port| --> |dest_port dest_dev(helper)
-------------------------- ---------------------------
Thanks,
Jie
>>
>
>
>
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2025-02-24 10:34 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-17 9:30 [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2025-02-17 9:30 ` [PATCH v12 1/7] Coresight: Add support for new APB clock name Jie Gan
2025-02-17 9:30 ` [PATCH v12 2/7] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
2025-02-20 17:34 ` Suzuki K Poulose
2025-02-21 1:23 ` Jie Gan
2025-02-17 9:30 ` [PATCH v12 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show() Jie Gan
2025-02-18 10:03 ` James Clark
2025-02-17 9:30 ` [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path Jie Gan
2025-02-21 10:30 ` Suzuki K Poulose
2025-02-24 2:35 ` Jie Gan
2025-02-17 9:30 ` [PATCH v12 5/7] dt-bindings: arm: Add Coresight TMC Control Unit hardware Jie Gan
2025-02-17 9:30 ` [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2025-02-21 11:39 ` Suzuki K Poulose
2025-02-24 3:32 ` Jie Gan
2025-02-24 9:53 ` James Clark
2025-02-24 10:04 ` Jie Gan
2025-02-24 10:33 ` Jie Gan
2025-02-24 10:22 ` Suzuki K Poulose
2025-02-24 10:26 ` Jie Gan
2025-02-17 9:30 ` [PATCH v12 7/7] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
2025-02-18 10:05 ` [PATCH v12 0/7] Coresight: Add Coresight TMC Control Unit driver James Clark
2025-02-19 0:59 ` Jie Gan
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