From: fange zhang <quic_fangez@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: <kernel@quicinc.com>, <quic_lliu6@quicinc.com>,
<quic_xiangxuy@quicinc.com>, <linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCH 5/6] dt-bindings: display/msm: Add QCS615 MDSS & DPU
Date: Thu, 21 Nov 2024 17:20:02 +0800 [thread overview]
Message-ID: <3e4e3640-8afe-4e73-90f3-8bd53850197c@quicinc.com> (raw)
In-Reply-To: <cq2qg5womfgrp422s3epsobad7lzhvawjnepmj6wsw2rzemarc@75jq4exnyqhn>
On 2024/10/14 18:35, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:31PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
>>
>> Add bindings for the display hardware on QCS615.
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>> .../bindings/display/msm/qcom,qcs615-dpu.yaml | 117 +++++++++
>> .../bindings/display/msm/qcom,qcs615-mdss.yaml | 278 +++++++++++++++++++++
>> 2 files changed, 395 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..35339092cb4f905541a7f70f42166bd0b0b7dee7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
>> @@ -0,0 +1,117 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-dpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QCS615 Display DPU
>> +
>> +maintainers:
>> + - lliu6 <quic_lliu6@quicinc.com>
>
> No, you are not. Please at least list Abhinav and me.
fixed in v2, change to
- Abhinav Kumar <quic_abhinavk@quicinc.com>
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
will replace qcs615 to sm6150 for whole patch
>
>> +
>> +$ref: /schemas/display/msm/dpu-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: qcom,qcs615-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display ahb clock
>> + - description: Display hf axi clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: bus
>> + - const: core
>> + - const: vsync
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
>
> I can not pick this up, these headers are not present in the msm-next
> tree. Please use ephemeral nodes instead.
will remove
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
and use ephemeral nodes instead
>
>> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>> + #include <dt-bindings/interconnect/qcom,icc.h>
>> + #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> + display-controller@ae01000 {
>> + compatible = "qcom,qcs615-dpu";
>> + reg = <0x0ae01000 0x8f000>,
>> + <0x0aeb0000 0x2008>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface", "bus", "lut" "core", "vsync";
>> +
>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + assigned-clock-rates = <19200000>;
>> +
>> + operating-points-v2 = <&mdp_opp_table>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dpu_intf0_out: endpoint {
>> + };
>> + };
>
> Indentation is definitely wrong.
fixed in v2
>
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> +
>> + };
>> +
>> + mdp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> +
>> + opp-575000000 {
>> + opp-hz = /bits/ 64 <575000000>;
>> + required-opps = <&rpmhpd_opp_turbo>;
>> + };
>> +
>> + opp-650000000 {
>> + opp-hz = /bits/ 64 <650000000>;
>> + required-opps = <&rpmhpd_opp_turbo_l1>;
>> + };
>> + };
>> + };
>> +...
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..fdad15c358892306dcb2c1b78319934c504cfc2b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
>> @@ -0,0 +1,278 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-mdss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QCS615 Display MDSS
>> +
>> +maintainers:
>> + - lliu6 <quic_lliu6@quicinc.com>
>> +
>> +description:
>> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
>> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
>> + bindings of MDSS are mentioned for QCS615 target.
>> +
>> +$ref: /schemas/display/msm/mdss-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,qcs615-mdss
>> +
>> + clocks:
>> + items:
>> + - description: Display AHB clock from gcc
>> + - description: Display hf axi clock
>> + - description: Display sf axi clock
>> + - description: Display core clock
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: bus
>> + - const: nrt_bus
>> + - const: core
>> +
>> + iommus:
>> + maxItems: 1
>> +
>> + interconnects:
>> + maxItems: 2
>> +
>> + interconnect-names:
>> + maxItems: 2
>> +
>> +patternProperties:
>> + "^display-controller@[0-9a-f]+$":
>> + type: object
>> + additionalProperties: true
>> +
>> + properties:
>> + compatible:
>> + const: qcom,qcs615-dpu
>> +
>> + "^displayport-controller@[0-9a-f]+$":
>> + type: object
>> + additionalProperties: true
>> +
>> + properties:
>> + compatible:
>> + contains:
>> + const: qcom,qcs615-dp
>
> It is not described anywhere, isn't it?
will remove this prop
>
>> +
>> + "^dsi@[0-9a-f]+$":
>> + type: object
>> + additionalProperties: true
>> +
>
> No empty line
fixed in v2
>
>> + properties:
>> + compatible:
>> + items:
>> + - const: qcom,qcs615-dsi-ctrl
>> + - const: qcom,mdss-dsi-ctrl
>> +
>> + "^phy@[0-9a-f]+$":
>> + type: object
>> + additionalProperties: true
>> +
>
> No empty line
fixed in v2
>
>> + properties:
>> + compatible:
>> + const: qcom,qcs615-dsi-phy-14nm
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
>> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>
> Same comment, use ephemeral nodes instead of listing the clocks exactly.
will remove
#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
and use ephemeral nodes instead
>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>> + #include <dt-bindings/interconnect/qcom,icc.h>
>> + #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> + display-subsystem@ae00000 {
>> + compatible = "qcom,qcs615-mdss";
>> + reg = <0x0ae00000 0x1000>;
>> + reg-names = "mdss";
>> +
>> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> + interconnect-names = "mdp0-mem", "cpu-cfg";
>
> Wrong indentation. No tabs in yaml files. Did it even compile?
will fix them in next version
>
>> +
>> + power-domains = <&dispcc MDSS_CORE_GDSC>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> +
>> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + iommus = <&apps_smmu 0x800 0x0>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + display-controller@ae01000 {
>> + compatible = "qcom,qcs615-dpu";
>> + reg = <0x0ae01000 0x8f000>,
>> + <0x0aeb0000 0x2008>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface", "bus", "lut", "core", "vsync";
>> +
>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + assigned-clock-rates = <19200000>;
>> +
>> + operating-points-v2 = <&mdp_opp_table>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dpu_intf0_out: endpoint {
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> +
>> + };
>> +
>> + mdp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> +
>> + opp-575000000 {
>> + opp-hz = /bits/ 64 <575000000>;
>> + required-opps = <&rpmhpd_opp_turbo>;
>> + };
>> +
>> + opp-650000000 {
>> + opp-hz = /bits/ 64 <650000000>;
>> + required-opps = <&rpmhpd_opp_turbo_l1>;
>> + };
>> + };
>> + };
>> +
>> + dsi@ae94000 {
>> + compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
>> + reg = <0x0ae94000 0x400>;
>> + reg-names = "dsi_ctrl";
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <4>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>;
>> + clock-names = "byte",
>> + "byte_intf",
>> + "pixel",
>> + "core",
>> + "iface",
>> + "bus";
>> +
>> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
>> + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
>> +
>> + operating-points-v2 = <&dsi0_opp_table>;
>> +
>> + phys = <&mdss_dsi0_phy>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + mdss_dsi0_in: endpoint {
>> + remote-endpoint = <&dpu_intf1_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + mdss_dsi0_out: endpoint {
>> + };
>> + };
>> + };
>> +
>> + dsi0_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-164000000 {
>> + opp-hz = /bits/ 64 <164000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-187500000 {
>> + opp-hz = /bits/ 64 <187500000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-225000000 {
>> + opp-hz = /bits/ 64 <225000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-262500000 {
>> + opp-hz = /bits/ 64 <262500000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> + };
>> +
>> + mdss_dsi0_phy: phy@ae94400 {
>> + compatible = "qcom,qcs615-dsi-phy-14nm";
>> + reg = <0x0ae94400 0x100>,
>> + <0x0ae94500 0x300>,
>> + <0x0ae94800 0x188>;
>> + reg-names = "dsi_phy",
>> + "dsi_phy_lane",
>> + "dsi_pll";
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "iface", "ref";
>> + vdds-supply = <&vreg_dsi_phy>;
>> + };
>> + };
>> +...
>>
>> --
>> 2.25.1
>>
>>
>
next prev parent reply other threads:[~2024-11-21 9:20 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-14 9:47 [PATCH 0/6] add_display_support_for_QCS615 fangez via B4 Relay
2024-10-14 9:47 ` [PATCH 1/6] arm64: defconfig: Enable SX150X fangez via B4 Relay
2024-10-14 10:12 ` Dmitry Baryshkov
2024-11-22 7:51 ` fange zhang
2024-10-14 10:37 ` Dmitry Baryshkov
2024-11-22 7:57 ` fange zhang
2024-11-22 8:09 ` Dmitry Baryshkov
2024-10-14 9:47 ` [PATCH 2/6] arm64: dts: qcom: qcs615: Add display mdss and dsi configuration fangez via B4 Relay
2024-10-14 10:27 ` Dmitry Baryshkov
2024-11-21 2:41 ` fange zhang
2024-10-14 9:47 ` [PATCH 3/6] drm/msm/dpu: Add QCS615 support fangez via B4 Relay
2024-10-14 10:47 ` Dmitry Baryshkov
2024-11-18 8:52 ` fange zhang
2024-11-18 10:55 ` Dmitry Baryshkov
2024-11-22 7:36 ` fange zhang
2024-11-22 7:37 ` Dmitry Baryshkov
2024-11-22 7:48 ` fange zhang
2024-10-14 9:47 ` [PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy fangez via B4 Relay
2024-10-14 10:30 ` Dmitry Baryshkov
2024-11-19 4:45 ` fange zhang
2024-11-20 12:22 ` Dmitry Baryshkov
2024-11-21 1:34 ` fange zhang
2024-10-14 11:49 ` Krzysztof Kozlowski
2024-10-14 9:47 ` [PATCH 5/6] dt-bindings: display/msm: Add QCS615 MDSS & DPU fangez via B4 Relay
2024-10-14 10:35 ` Dmitry Baryshkov
2024-11-21 9:20 ` fange zhang [this message]
2024-10-14 11:50 ` Krzysztof Kozlowski
2024-10-14 9:47 ` [PATCH 6/6] dt-bindings: display/msm: dsi-controller-main: Document QCS615 fangez via B4 Relay
2024-10-14 10:39 ` Dmitry Baryshkov
2024-11-19 4:20 ` fange zhang
2024-10-14 10:36 ` [PATCH 0/6] add_display_support_for_QCS615 Dmitry Baryshkov
2024-10-14 10:48 ` Dmitry Baryshkov
[not found] ` <SJ0PR02MB8750D786748D105839EE905BE3442@SJ0PR02MB8750.namprd02.prod.outlook.com>
2024-10-14 11:59 ` Dmitry Baryshkov
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