[PATCH 0/6] add_display_support_for_QCS615

[PATCH 0/6] add_display_support_for_QCS615

[fangez via B4 Relay]

Signed-off-by: fangez <quic_fangez@quicinc.com>
---
lliu6 (6):
      arm64: defconfig: Enable SX150X
      arm64: dts: qcom: qcs615: Add display mdss and dsi configuration
      drm/msm/dpu: Add QCS615 support
      dt-bindings: display/msm: Add QCS615 DSI phy
      dt-bindings: display/msm: Add QCS615 MDSS & DPU
      dt-bindings: display/msm: dsi-controller-main: Document QCS615

 .../bindings/display/msm/dsi-controller-main.yaml  |   1 +
 .../bindings/display/msm/dsi-phy-14nm.yaml         |   1 +
 .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
 .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs615-ride.dts           | 101 ++++++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi               | 195 +++++++++++++++
 arch/arm64/configs/defconfig                       |   1 +
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
 drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
 drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
 17 files changed, 1014 insertions(+)
---
base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a
change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e

Best regards,
-- 
fangez <quic_fangez@quicinc.com>

[PATCH 1/6] arm64: defconfig: Enable SX150X

[fangez via B4 Relay]

From: lliu6 <quic_lliu6@quicinc.com>

Enable SX150X pinctrl driver.

Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y
 CONFIG_PINCTRL_SM8450=y
 CONFIG_PINCTRL_SM8550=y
 CONFIG_PINCTRL_SM8650=y
+CONFIG_PINCTRL_SX150X=y
 CONFIG_PINCTRL_X1E80100=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
 CONFIG_PINCTRL_LPASS_LPI=m

-- 
2.25.1

Re: [PATCH 1/6] arm64: defconfig: Enable SX150X

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:27PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>

This is not the name

> 
> Enable SX150X pinctrl driver.

... which is used for the abcdef board.

> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y
>  CONFIG_PINCTRL_SM8450=y
>  CONFIG_PINCTRL_SM8550=y
>  CONFIG_PINCTRL_SM8650=y
> +CONFIG_PINCTRL_SX150X=y
>  CONFIG_PINCTRL_X1E80100=y
>  CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
>  CONFIG_PINCTRL_LPASS_LPI=m
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 1/6] arm64: defconfig: Enable SX150X

[fange zhang]

On 2024/10/14 18:12, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:27PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
> 
> This is not the name
sorry for the mistake.
fixed in v2
> 
>>
>> Enable SX150X pinctrl driver.
> 
> ... which is used for the abcdef board.
will remove this patch in v3
> 
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>>   arch/arm64/configs/defconfig | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y
>>   CONFIG_PINCTRL_SM8450=y
>>   CONFIG_PINCTRL_SM8550=y
>>   CONFIG_PINCTRL_SM8650=y
>> +CONFIG_PINCTRL_SX150X=y
>>   CONFIG_PINCTRL_X1E80100=y
>>   CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
>>   CONFIG_PINCTRL_LPASS_LPI=m
>>
>> -- 
>> 2.25.1
>>
>>
> 

Re: [PATCH 1/6] arm64: defconfig: Enable SX150X

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:27PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> Enable SX150X pinctrl driver.
> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>

Ok, even worse. fangez, you are not the author of the patches, so there
is a missing S-o-B.

> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y
>  CONFIG_PINCTRL_SM8450=y
>  CONFIG_PINCTRL_SM8550=y
>  CONFIG_PINCTRL_SM8650=y
> +CONFIG_PINCTRL_SX150X=y
>  CONFIG_PINCTRL_X1E80100=y
>  CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
>  CONFIG_PINCTRL_LPASS_LPI=m
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 1/6] arm64: defconfig: Enable SX150X

[fange zhang]

On 2024/10/14 18:37, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:27PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
>>
>> Enable SX150X pinctrl driver.
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> 
> Ok, even worse. fangez, you are not the author of the patches, so there
> is a missing S-o-B.
Got it, fixed in v2 for other patches, and will remove the defconfig patch

and I believe all items have been addressed. May I ask if we can start 
sending v3 now?
> 
>> ---
>>   arch/arm64/configs/defconfig | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y
>>   CONFIG_PINCTRL_SM8450=y
>>   CONFIG_PINCTRL_SM8550=y
>>   CONFIG_PINCTRL_SM8650=y
>> +CONFIG_PINCTRL_SX150X=y
>>   CONFIG_PINCTRL_X1E80100=y
>>   CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
>>   CONFIG_PINCTRL_LPASS_LPI=m
>>
>> -- 
>> 2.25.1
>>
>>
> 

Re: [PATCH 1/6] arm64: defconfig: Enable SX150X

[Dmitry Baryshkov]

On Fri, 22 Nov 2024 at 09:57, fange zhang <quic_fangez@quicinc.com> wrote:
>
>
>
> On 2024/10/14 18:37, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 05:47:27PM +0800, fangez via B4 Relay wrote:
> >> From: lliu6 <quic_lliu6@quicinc.com>
> >>
> >> Enable SX150X pinctrl driver.
> >>
> >> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> >
> > Ok, even worse. fangez, you are not the author of the patches, so there
> > is a missing S-o-B.
> Got it, fixed in v2 for other patches, and will remove the defconfig patch
>
> and I believe all items have been addressed. May I ask if we can start
> sending v3 now?

Of course.

> >
> >> ---
> >>   arch/arm64/configs/defconfig | 1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> >> index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644
> >> --- a/arch/arm64/configs/defconfig
> >> +++ b/arch/arm64/configs/defconfig
> >> @@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y
> >>   CONFIG_PINCTRL_SM8450=y
> >>   CONFIG_PINCTRL_SM8550=y
> >>   CONFIG_PINCTRL_SM8650=y
> >> +CONFIG_PINCTRL_SX150X=y
> >>   CONFIG_PINCTRL_X1E80100=y
> >>   CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
> >>   CONFIG_PINCTRL_LPASS_LPI=m
> >>
> >> --
> >> 2.25.1
> >>
> >>
> >
>


-- 
With best wishes
Dmitry

[PATCH 2/6] arm64: dts: qcom: qcs615: Add display mdss and dsi configuration

[fangez via B4 Relay]

From: lliu6 <quic_lliu6@quicinc.com>

Add display mdss and dsi configuration for QCS615 SoC.

Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi     | 195 +++++++++++++++++++++++++++++++
 2 files changed, 296 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index d05a881d7ffeca9de175af2a9062f5bccadcbdfd..f275145c395aedb71bdcd8a88b82917db53e7167 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -207,6 +207,107 @@ &gcc {
 		 <&sleep_clk>;
 };
 
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&qup_i2c2_data_clk &ioexp_intr_active &ioexp_reset_active>;
+	pinctrl-names = "default";
+	status = "okay";
+	ioexp: gpio@3e {
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		compatible = "semtech,sx1509q";
+		reg = <0x3e>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <58 0>;
+		gpio-controller;
+		interrupt-controller;
+		semtech,probe-reset;
+		pinctrl-names = "default";
+		pinctrl-0 = <&dsi0_hpd_cfg_pins &dsi0_cdet_cfg_pins &dp_hpd_cfg_pins>;
+		dsi0_hpd_cfg_pins: gpio0-cfg {
+			pins = "gpio0";
+			bias-pull-up;
+		};
+		dsi0_cdet_cfg_pins: gpio1-cfg {
+			pins = "gpio1";
+			bias-pull-down;
+		};
+		dp_hpd_cfg_pins: gpio8-cfg {
+			pins = "gpio8";
+			bias-pull-down;
+		};
+	};
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9542";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			anx_7625_1: anx7625@2c {
+				compatible = "analogix,anx7625";
+				reg = <0x58>;
+				interrupt-parent = <&ioexp>;
+				interrupts = <0 0>;
+				enable-gpios = <&tlmm 4 0>;
+				reset-gpios = <&tlmm 5 0>;
+				wakeup-source;
+			};
+		};
+	};
+};
+
+&anx_7625_1 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			anx_7625_1_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	status = "okay";
+	vdda-supply = <&vreg_l11a>;
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&anx_7625_1_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	status = "okay";
+	vdds-supply = <&vreg_l5a>;
+};
+
+&tlmm {
+	ioexp_intr_active: ioexp_intr_active {
+		pins = "gpio58";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+	ioexp_reset_active: ioexp_reset_active {
+		pins = "gpio3";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-high;
+	};
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 8e2199bb180d85a86a882c4253778c7e8f34798b..2a6c08220e6c4ded49861754d81d0924389dd93e 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -1266,6 +1266,201 @@ camcc: clock-controller@ad00000 {
 			#power-domain-cells = <1>;
 		};
 
+		mdss: display-subsystem@ae00000 {
+			compatible = "qcom,qcs615-mdss";
+			reg = <0 0x0ae00000 0 0x1000>;
+			reg-names = "mdss";
+
+			interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "mdp0-mem",
+					     "cpu-cfg";
+
+			power-domains = <&dispcc MDSS_CORE_GDSC>;
+
+			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			iommus = <&apps_smmu 0x800 0x0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			mdss_mdp: display-controller@ae01000 {
+				compatible = "qcom,qcs615-dpu";
+				reg = <0 0x0ae01000 0 0x8f000>,
+				      <0 0x0aeb0000 0 0x2008>;
+				reg-names = "mdp", "vbif";
+
+				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+						 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+						 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+						 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+						 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "bus",
+							  "iface",
+							  "lut",
+							  "core",
+							  "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+
+				operating-points-v2 = <&mdp_opp_table>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf0_out: endpoint {
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+				};
+
+				mdp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-375000000 {
+						opp-hz = /bits/ 64 <375000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-500000000 {
+						opp-hz = /bits/ 64 <500000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+
+					opp-575000000 {
+						opp-hz = /bits/ 64 <575000000>;
+						required-opps = <&rpmhpd_opp_turbo>;
+					};
+
+					opp-650000000 {
+						opp-hz = /bits/ 64 <650000000>;
+						required-opps = <&rpmhpd_opp_turbo_l1>;
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@ae94000 {
+				compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae94000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+						 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+						 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+						 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+						 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+						 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+							  "byte_intf",
+							  "pixel",
+							  "core",
+							  "iface",
+							  "bus";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+							 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>,
+							 <&mdss_dsi0_phy 1>;
+
+				operating-points-v2 = <&dsi0_opp_table>;
+
+				phys = <&mdss_dsi0_phy>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				dsi0_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-164000000 {
+						opp-hz = /bits/ 64 <164000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-187500000 {
+						opp-hz = /bits/ 64 <187500000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-225000000 {
+						opp-hz = /bits/ 64 <225000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-262500000 {
+						opp-hz = /bits/ 64 <262500000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@ae94400 {
+				compatible = "qcom,qcs615-dsi-phy-14nm";
+				reg = <0 0x0ae94400 0 0x100>,
+				      <0 0x0ae94500 0 0x300>,
+				      <0 0x0ae94800 0 0x188>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+		};
+
 		dispcc: clock-controller@af00000 {
 			compatible = "qcom,qcs615-dispcc";
 			reg = <0 0xaf00000 0 0x20000>;

-- 
2.25.1

Re: [PATCH 2/6] arm64: dts: qcom: qcs615: Add display mdss and dsi configuration

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:28PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>

This is not a name.

> 
> Add display mdss and dsi configuration for QCS615 SoC.

MDSS, DSI

separate Ride configuration to a separate commit

Patch order is wrong.
- dt-bindings
- driver changes
- dtsi
- dts

> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++++++++++
>  arch/arm64/boot/dts/qcom/qcs615.dtsi     | 195 +++++++++++++++++++++++++++++++
>  2 files changed, 296 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> index d05a881d7ffeca9de175af2a9062f5bccadcbdfd..f275145c395aedb71bdcd8a88b82917db53e7167 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -207,6 +207,107 @@ &gcc {
>  		 <&sleep_clk>;
>  };
>  
> +&i2c2 {
> +	clock-frequency = <400000>;
> +	pinctrl-0 = <&qup_i2c2_data_clk &ioexp_intr_active &ioexp_reset_active>;
> +	pinctrl-names = "default";
> +	status = "okay";

empty line

> +	ioexp: gpio@3e {
> +		#gpio-cells = <2>;
> +		#interrupt-cells = <2>;
> +		compatible = "semtech,sx1509q";
> +		reg = <0x3e>;
> +		interrupt-parent = <&tlmm>;
> +		interrupts = <58 0>;
> +		gpio-controller;
> +		interrupt-controller;
> +		semtech,probe-reset;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&dsi0_hpd_cfg_pins &dsi0_cdet_cfg_pins &dp_hpd_cfg_pins>;

No, these pins are not used by the IO expander. Please moved them to the
corresponding devices.


empty line

> +		dsi0_hpd_cfg_pins: gpio0-cfg {

What exactly is DSI HPD?

> +			pins = "gpio0";
> +			bias-pull-up;
> +		};

and here (and you'll guess all other relevant places, I hope it's
obvious).

> +		dsi0_cdet_cfg_pins: gpio1-cfg {
> +			pins = "gpio1";
> +			bias-pull-down;
> +		};
> +		dp_hpd_cfg_pins: gpio8-cfg {
> +			pins = "gpio8";
> +			bias-pull-down;
> +		};
> +	};
> +
> +	i2c-mux@77 {
> +		compatible = "nxp,pca9542";
> +		reg = <0x77>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			anx_7625_1: anx7625@2c {

Are there more than one?

> +				compatible = "analogix,anx7625";
> +				reg = <0x58>;
> +				interrupt-parent = <&ioexp>;
> +				interrupts = <0 0>;
> +				enable-gpios = <&tlmm 4 0>;

Use defines for the GPIO flags instead of 0

> +				reset-gpios = <&tlmm 5 0>;
> +				wakeup-source;
> +			};
> +		};
> +	};
> +};
> +
> +&anx_7625_1 {

No need to, keep it in the same node.

> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		port@0 {
> +			reg = <0>;
> +			anx_7625_1_in: endpoint {
> +				remote-endpoint = <&mdss_dsi0_out>;
> +			};
> +		};

Missing port@1 and the connector node.

> +	};
> +};
> +
> +&mdss {
> +	status = "okay";
> +};
> +
> +&mdss_dsi0 {
> +	status = "okay";

Status is the last property.

> +	vdda-supply = <&vreg_l11a>;
> +};
> +
> +&mdss_dsi0_out {
> +	remote-endpoint = <&anx_7625_1_in>;
> +	data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> +	status = "okay";
> +	vdds-supply = <&vreg_l5a>;
> +};
> +
> +&tlmm {
> +	ioexp_intr_active: ioexp_intr_active {

This doesn't seem to be validated. Please check your patches before
sending.

> +		pins = "gpio58";
> +		function = "gpio";
> +		drive-strength = <2>;
> +		bias-pull-up;
> +	};
> +	ioexp_reset_active: ioexp_reset_active {
> +		pins = "gpio3";
> +		function = "gpio";
> +		drive-strength = <2>;
> +		bias-disable;
> +		output-high;
> +	};
> +};
> +
>  &qupv3_id_0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 8e2199bb180d85a86a882c4253778c7e8f34798b..2a6c08220e6c4ded49861754d81d0924389dd93e 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -1266,6 +1266,201 @@ camcc: clock-controller@ad00000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		mdss: display-subsystem@ae00000 {
> +			compatible = "qcom,qcs615-mdss";
> +			reg = <0 0x0ae00000 0 0x1000>;
> +			reg-names = "mdss";
> +
> +			interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,

QCOM_ICC_TAG_ALWAYS

> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +					&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> +			interconnect-names = "mdp0-mem",
> +					     "cpu-cfg";
> +
> +			power-domains = <&dispcc MDSS_CORE_GDSC>;
> +
> +			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +					 <&gcc GCC_DISP_HF_AXI_CLK>,
> +					 <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +
> +			iommus = <&apps_smmu 0x800 0x0>;
> +
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			status = "disabled";
> +
> +			mdss_mdp: display-controller@ae01000 {
> +				compatible = "qcom,qcs615-dpu";
> +				reg = <0 0x0ae01000 0 0x8f000>,
> +				      <0 0x0aeb0000 0 0x2008>;
> +				reg-names = "mdp", "vbif";
> +
> +				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> +						 <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +						 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> +						 <&dispcc DISP_CC_MDSS_MDP_CLK>,
> +						 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

Please indent lists so that the values are one under another, starting
at the same column.

> +				clock-names = "bus",
> +							  "iface",
> +							  "lut",
> +							  "core",
> +							  "vsync";
> +
> +				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +				assigned-clock-rates = <19200000>;
> +
> +				operating-points-v2 = <&mdp_opp_table>;
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <0>;
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +						dpu_intf0_out: endpoint {
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +						dpu_intf1_out: endpoint {
> +							remote-endpoint = <&mdss_dsi0_in>;
> +						};
> +					};
> +				};
> +
> +				mdp_opp_table: opp-table {
> +					compatible = "operating-points-v2";
> +
> +					opp-375000000 {
> +						opp-hz = /bits/ 64 <375000000>;
> +						required-opps = <&rpmhpd_opp_svs_l1>;
> +					};
> +
> +					opp-500000000 {
> +						opp-hz = /bits/ 64 <500000000>;
> +						required-opps = <&rpmhpd_opp_nom>;
> +					};
> +
> +					opp-575000000 {
> +						opp-hz = /bits/ 64 <575000000>;
> +						required-opps = <&rpmhpd_opp_turbo>;
> +					};
> +
> +					opp-650000000 {
> +						opp-hz = /bits/ 64 <650000000>;
> +						required-opps = <&rpmhpd_opp_turbo_l1>;
> +					};
> +				};
> +			};
> +
> +			mdss_dsi0: dsi@ae94000 {
> +				compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> +				reg = <0 0x0ae94000 0 0x400>;
> +				reg-names = "dsi_ctrl";
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <4>;
> +
> +				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> +						 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +						 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> +						 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> +						 <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +						 <&gcc GCC_DISP_HF_AXI_CLK>;
> +				clock-names = "byte",
> +							  "byte_intf",
> +							  "pixel",
> +							  "core",
> +							  "iface",
> +							  "bus";
> +
> +				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> +							 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> +				assigned-clock-parents = <&mdss_dsi0_phy 0>,
> +							 <&mdss_dsi0_phy 1>;
> +
> +				operating-points-v2 = <&dsi0_opp_table>;
> +
> +				phys = <&mdss_dsi0_phy>;
> +
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				status = "disabled";
> +
> +				dsi0_opp_table: opp-table {
> +					compatible = "operating-points-v2";
> +
> +					opp-164000000 {
> +						opp-hz = /bits/ 64 <164000000>;
> +						required-opps = <&rpmhpd_opp_low_svs>;
> +					};
> +
> +					opp-187500000 {
> +						opp-hz = /bits/ 64 <187500000>;
> +						required-opps = <&rpmhpd_opp_svs>;
> +					};
> +
> +					opp-225000000 {
> +						opp-hz = /bits/ 64 <225000000>;
> +						required-opps = <&rpmhpd_opp_svs_l1>;
> +					};
> +
> +					opp-262500000 {
> +						opp-hz = /bits/ 64 <262500000>;
> +						required-opps = <&rpmhpd_opp_nom>;
> +					};
> +				};
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +						mdss_dsi0_in: endpoint {
> +							remote-endpoint = <&dpu_intf1_out>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +						mdss_dsi0_out: endpoint {
> +						};
> +					};
> +				};
> +			};
> +
> +			mdss_dsi0_phy: phy@ae94400 {
> +				compatible = "qcom,qcs615-dsi-phy-14nm";
> +				reg = <0 0x0ae94400 0 0x100>,
> +				      <0 0x0ae94500 0 0x300>,
> +				      <0 0x0ae94800 0 0x188>;
> +				reg-names = "dsi_phy",
> +					    "dsi_phy_lane",
> +					    "dsi_pll";
> +
> +				#clock-cells = <1>;
> +				#phy-cells = <0>;
> +
> +				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +					 <&rpmhcc RPMH_CXO_CLK>;
> +				clock-names = "iface", "ref";
> +
> +				status = "disabled";
> +			};

Does QCS615 have a DP controller? Please mention it in the commit
message.

> +		};
> +
>  		dispcc: clock-controller@af00000 {
>  			compatible = "qcom,qcs615-dispcc";
>  			reg = <0 0xaf00000 0 0x20000>;
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 2/6] arm64: dts: qcom: qcs615: Add display mdss and dsi configuration

[fange zhang]

On 2024/10/14 18:27, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:28PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
> 
> This is not a name.
fixed in v2
> 
>>
>> Add display mdss and dsi configuration for QCS615 SoC.
> 
> MDSS, DSI
> 
> separate Ride configuration to a separate commit
> 
> Patch order is wrong.
> - dt-bindings
> - driver changes
> - dtsi
> - dts
> 
ok will fix it in next version
it will be:
- dtb
dt-bindings: display/msm: Add SM6150 DSI phy
dt-bindings: display/msm: dsi-controller-main: Document SM6150
dt-bindings: display/msm: Add SM6150 MDSS & DPU

- driver
drm/msm: mdss: Add SM6150 support
drm/msm/dpu: Add SM6150 support
drm/msm/dsi: Add dsi phy support for SM6150
drm/msm/dsi: Add support for SM6150

- dtsi
arm64: dts: qcom: Add display support for QCS615
- dts
arm64: dts: qcom: Add display support for QCS615 RIDE board

>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++++++++++
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi     | 195 +++++++++++++++++++++++++++++++
>>   2 files changed, 296 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> index d05a881d7ffeca9de175af2a9062f5bccadcbdfd..f275145c395aedb71bdcd8a88b82917db53e7167 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> @@ -207,6 +207,107 @@ &gcc {
>>   		 <&sleep_clk>;
>>   };
>>   
>> +&i2c2 {
>> +	clock-frequency = <400000>;
>> +	pinctrl-0 = <&qup_i2c2_data_clk &ioexp_intr_active &ioexp_reset_active>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
> 
> empty line
fixed in v2
> 
>> +	ioexp: gpio@3e {
>> +		#gpio-cells = <2>;
>> +		#interrupt-cells = <2>;
>> +		compatible = "semtech,sx1509q";
>> +		reg = <0x3e>;
>> +		interrupt-parent = <&tlmm>;
>> +		interrupts = <58 0>;
>> +		gpio-controller;
>> +		interrupt-controller;
>> +		semtech,probe-reset;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&dsi0_hpd_cfg_pins &dsi0_cdet_cfg_pins &dp_hpd_cfg_pins>;
> 
> No, these pins are not used by the IO expander. Please moved them to the
> corresponding devices.
will remove pinctrl part
- pinctrl-names = "default";
- pinctrl-0 = <&dsi0_hpd_cfg_pins &dsi0_cdet_cfg_pins &dp_hpd_cfg_pins>;

> 
> 
> empty line
fixed in v2
> 
>> +		dsi0_hpd_cfg_pins: gpio0-cfg {
> 
> What exactly is DSI HPD?
> 
>> +			pins = "gpio0";
>> +			bias-pull-up;
>> +		};
> 
> and here (and you'll guess all other relevant places, I hope it's
> obvious).
> 
>> +		dsi0_cdet_cfg_pins: gpio1-cfg {
>> +			pins = "gpio1";
>> +			bias-pull-down;
>> +		};
>> +		dp_hpd_cfg_pins: gpio8-cfg {
>> +			pins = "gpio8";
>> +			bias-pull-down;
>> +		};
>> +	};
will remove dsi0_hpd_cfg_pins, dsi0_cdet_cfg_pins and dp_hpd_cfg_pins
>> +
>> +	i2c-mux@77 {
>> +		compatible = "nxp,pca9542";
>> +		reg = <0x77>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		i2c@0 {
>> +			reg = <0>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			anx_7625_1: anx7625@2c {
> 
> Are there more than one?
fixed in v2
change anx_7625_1 to anx_7625
> 
>> +				compatible = "analogix,anx7625";
>> +				reg = <0x58>;
>> +				interrupt-parent = <&ioexp>;
>> +				interrupts = <0 0>;
>> +				enable-gpios = <&tlmm 4 0>;
> 
> Use defines for the GPIO flags instead of 0
fixed in v2
change 0 to GPIO_ACTIVE_HIGH botin in enable and reset gpios
> 
>> +				reset-gpios = <&tlmm 5 0>;
>> +				wakeup-source;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&anx_7625_1 {
> 
> No need to, keep it in the same node.
fixed in v2
> 
>> +	ports {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		port@0 {
>> +			reg = <0>;
>> +			anx_7625_1_in: endpoint {
>> +				remote-endpoint = <&mdss_dsi0_out>;
>> +			};
>> +		};
> 
> Missing port@1 and the connector node.
fixed in v2
> 
>> +	};
>> +};
>> +
>> +&mdss {
>> +	status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> +	status = "okay";
> 
> Status is the last property.
> 
>> +	vdda-supply = <&vreg_l11a>;
>> +};
>> +
>> +&mdss_dsi0_out {
>> +	remote-endpoint = <&anx_7625_1_in>;
>> +	data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> +	status = "okay";
>> +	vdds-supply = <&vreg_l5a>;
>> +};
>> +
>> +&tlmm {
>> +	ioexp_intr_active: ioexp_intr_active {
> 
> This doesn't seem to be validated. Please check your patches before
> sending.
will remove tlmm for this part
> 
>> +		pins = "gpio58";
>> +		function = "gpio";
>> +		drive-strength = <2>;
>> +		bias-pull-up;
>> +	};
>> +	ioexp_reset_active: ioexp_reset_active {
>> +		pins = "gpio3";
>> +		function = "gpio";
>> +		drive-strength = <2>;
>> +		bias-disable;
>> +		output-high;
>> +	};
>> +};
>> +
>>   &qupv3_id_0 {
>>   	status = "okay";
>>   };
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 8e2199bb180d85a86a882c4253778c7e8f34798b..2a6c08220e6c4ded49861754d81d0924389dd93e 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -1266,6 +1266,201 @@ camcc: clock-controller@ad00000 {
>>   			#power-domain-cells = <1>;
>>   		};
>>   
>> +		mdss: display-subsystem@ae00000 {
>> +			compatible = "qcom,qcs615-mdss";
>> +			reg = <0 0x0ae00000 0 0x1000>;
>> +			reg-names = "mdss";
>> +
>> +			interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> 
> QCOM_ICC_TAG_ALWAYS
fixed in v2
> 
>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> +					&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> +			interconnect-names = "mdp0-mem",
>> +					     "cpu-cfg";
>> +
>> +			power-domains = <&dispcc MDSS_CORE_GDSC>;
>> +
>> +			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +					 <&gcc GCC_DISP_HF_AXI_CLK>,
>> +					 <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> +
>> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <1>;
>> +
>> +			iommus = <&apps_smmu 0x800 0x0>;
>> +
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges;
>> +
>> +			status = "disabled";
>> +
>> +			mdss_mdp: display-controller@ae01000 {
>> +				compatible = "qcom,qcs615-dpu";
>> +				reg = <0 0x0ae01000 0 0x8f000>,
>> +				      <0 0x0aeb0000 0 0x2008>;
>> +				reg-names = "mdp", "vbif";
>> +
>> +				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> 
> Please indent lists so that the values are one under another, starting
> at the same column.
sorry, fixed in v2
> 
>> +				clock-names = "bus",
>> +							  "iface",
>> +							  "lut",
>> +							  "core",
>> +							  "vsync";
>> +
>> +				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> +				assigned-clock-rates = <19200000>;
>> +
>> +				operating-points-v2 = <&mdp_opp_table>;
>> +
>> +				interrupt-parent = <&mdss>;
>> +				interrupts = <0>;
>> +
>> +				ports {
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					port@0 {
>> +						reg = <0>;
>> +						dpu_intf0_out: endpoint {
>> +						};
>> +					};
>> +
>> +					port@1 {
>> +						reg = <1>;
>> +						dpu_intf1_out: endpoint {
>> +							remote-endpoint = <&mdss_dsi0_in>;
>> +						};
>> +					};
>> +				};
>> +
>> +				mdp_opp_table: opp-table {
>> +					compatible = "operating-points-v2";
>> +
>> +					opp-375000000 {
>> +						opp-hz = /bits/ 64 <375000000>;
>> +						required-opps = <&rpmhpd_opp_svs_l1>;
>> +					};
>> +
>> +					opp-500000000 {
>> +						opp-hz = /bits/ 64 <500000000>;
>> +						required-opps = <&rpmhpd_opp_nom>;
>> +					};
>> +
>> +					opp-575000000 {
>> +						opp-hz = /bits/ 64 <575000000>;
>> +						required-opps = <&rpmhpd_opp_turbo>;
>> +					};
>> +
>> +					opp-650000000 {
>> +						opp-hz = /bits/ 64 <650000000>;
>> +						required-opps = <&rpmhpd_opp_turbo_l1>;
>> +					};
>> +				};
>> +			};
>> +
>> +			mdss_dsi0: dsi@ae94000 {
>> +				compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
>> +				reg = <0 0x0ae94000 0 0x400>;
>> +				reg-names = "dsi_ctrl";
>> +
>> +				interrupt-parent = <&mdss>;
>> +				interrupts = <4>;
>> +
>> +				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> +						 <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +						 <&gcc GCC_DISP_HF_AXI_CLK>;
>> +				clock-names = "byte",
>> +							  "byte_intf",
>> +							  "pixel",
>> +							  "core",
>> +							  "iface",
>> +							  "bus";
>> +
>> +				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> +							 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
>> +				assigned-clock-parents = <&mdss_dsi0_phy 0>,
>> +							 <&mdss_dsi0_phy 1>;
>> +
>> +				operating-points-v2 = <&dsi0_opp_table>;
>> +
>> +				phys = <&mdss_dsi0_phy>;
>> +
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +
>> +				status = "disabled";
>> +
>> +				dsi0_opp_table: opp-table {
>> +					compatible = "operating-points-v2";
>> +
>> +					opp-164000000 {
>> +						opp-hz = /bits/ 64 <164000000>;
>> +						required-opps = <&rpmhpd_opp_low_svs>;
>> +					};
>> +
>> +					opp-187500000 {
>> +						opp-hz = /bits/ 64 <187500000>;
>> +						required-opps = <&rpmhpd_opp_svs>;
>> +					};
>> +
>> +					opp-225000000 {
>> +						opp-hz = /bits/ 64 <225000000>;
>> +						required-opps = <&rpmhpd_opp_svs_l1>;
>> +					};
>> +
>> +					opp-262500000 {
>> +						opp-hz = /bits/ 64 <262500000>;
>> +						required-opps = <&rpmhpd_opp_nom>;
>> +					};
>> +				};
>> +
>> +				ports {
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					port@0 {
>> +						reg = <0>;
>> +						mdss_dsi0_in: endpoint {
>> +							remote-endpoint = <&dpu_intf1_out>;
>> +						};
>> +					};
>> +
>> +					port@1 {
>> +						reg = <1>;
>> +						mdss_dsi0_out: endpoint {
>> +						};
>> +					};
>> +				};
>> +			};
>> +
>> +			mdss_dsi0_phy: phy@ae94400 {
>> +				compatible = "qcom,qcs615-dsi-phy-14nm";
>> +				reg = <0 0x0ae94400 0 0x100>,
>> +				      <0 0x0ae94500 0 0x300>,
>> +				      <0 0x0ae94800 0 0x188>;
>> +				reg-names = "dsi_phy",
>> +					    "dsi_phy_lane",
>> +					    "dsi_pll";
>> +
>> +				#clock-cells = <1>;
>> +				#phy-cells = <0>;
>> +
>> +				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +					 <&rpmhcc RPMH_CXO_CLK>;
>> +				clock-names = "iface", "ref";
>> +
>> +				status = "disabled";
>> +			};
> 
> Does QCS615 have a DP controller? Please mention it in the commit
> message.
yes, have DP. it's another big change, will upload in next patch series
fixed in v2, added comments in commit message
> 
>> +		};
>> +
>>   		dispcc: clock-controller@af00000 {
>>   			compatible = "qcom,qcs615-dispcc";
>>   			reg = <0 0xaf00000 0 0x20000>;
>>
>> -- 
>> 2.25.1
>>
>>
> 

[PATCH 3/6] drm/msm/dpu: Add QCS615 support

[fangez via B4 Relay]

From: lliu6 <quic_lliu6@quicinc.com>

Add support for the display hardware used on the Qualcomm QCS615 platform.

Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
 drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
 drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
 10 files changed, 320 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h
new file mode 100644
index 0000000000000000000000000000000000000000..ff7e390db2af9cded05e75b00a5778fdba2cf9ae
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h
@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_5_3_QCS615_H
+#define _DPU_5_3_QCS615_H
+
+static const struct dpu_caps qcs615_dpu_caps = {
+	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+	.max_mixer_blendstages = 0x9,
+	.has_dim_layer = true,
+	.has_idle_pc = true,
+	.max_linewidth = 2160,
+	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+	.max_hdeci_exp = MAX_HORZ_DECIMATION,
+	.max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg qcs615_mdp = {
+	.name = "top_0",
+	.base = 0x0, .len = 0x45c,
+	.features = 0,
+	.clk_ctrls = {
+		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+	},
+};
+
+static const struct dpu_ctl_cfg qcs615_ctl[] = {
+	{
+		.name = "ctl_0", .id = CTL_0,
+		.base = 0x1000, .len = 0x1e0,
+		.features = BIT(DPU_CTL_ACTIVE_CFG),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+	}, {
+		.name = "ctl_1", .id = CTL_1,
+		.base = 0x1200, .len = 0x1e0,
+		.features = BIT(DPU_CTL_ACTIVE_CFG),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+	}, {
+		.name = "ctl_2", .id = CTL_2,
+		.base = 0x1400, .len = 0x1e0,
+		.features = BIT(DPU_CTL_ACTIVE_CFG),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+	}, {
+		.name = "ctl_3", .id = CTL_3,
+		.base = 0x1600, .len = 0x1e0,
+		.features = BIT(DPU_CTL_ACTIVE_CFG),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+	}, {
+		.name = "ctl_4", .id = CTL_4,
+		.base = 0x1800, .len = 0x1e0,
+		.features = BIT(DPU_CTL_ACTIVE_CFG),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+	}, {
+		.name = "ctl_5", .id = CTL_5,
+		.base = 0x1a00, .len = 0x1e0,
+		.features = BIT(DPU_CTL_ACTIVE_CFG),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+	},
+};
+
+static const struct dpu_sspp_cfg qcs615_sspp[] = {
+	{
+		.name = "sspp_0", .id = SSPP_VIG0,
+		.base = 0x4000, .len = 0x1f0,
+		.features = VIG_SDM845_MASK,//here
+		.sblk = &dpu_vig_sblk_qseed3_2_4,
+		.xin_id = 0,
+		.type = SSPP_TYPE_VIG,
+		.clk_ctrl = DPU_CLK_CTRL_VIG0,
+	}, {
+		.name = "sspp_8", .id = SSPP_DMA0,
+		.base = 0x24000, .len = 0x1f0,
+		.features = DMA_SDM845_MASK,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 1,
+		.type = SSPP_TYPE_DMA,
+		.clk_ctrl = DPU_CLK_CTRL_DMA0,
+	}, {
+		.name = "sspp_9", .id = SSPP_DMA1,
+		.base = 0x26000, .len = 0x1f0,
+		.features = DMA_SDM845_MASK,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 5,
+		.type = SSPP_TYPE_DMA,
+		.clk_ctrl = DPU_CLK_CTRL_DMA1,
+	}, {
+		.name = "sspp_10", .id = SSPP_DMA2,
+		.base = 0x28000, .len = 0x1f0,
+		.features = DMA_CURSOR_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 9,
+		.type = SSPP_TYPE_DMA,
+		.clk_ctrl = DPU_CLK_CTRL_DMA2,
+	}, {
+		.name = "sspp_11", .id = SSPP_DMA3,
+		.base = 0x2a000, .len = 0x1f0,
+		.features = DMA_CURSOR_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 13,
+		.type = SSPP_TYPE_DMA,
+		.clk_ctrl = DPU_CLK_CTRL_DMA3,
+	},
+};
+
+static const struct dpu_lm_cfg qcs615_lm[] = {
+	{
+		.name = "lm_0", .id = LM_0,
+		.base = 0x44000, .len = 0x320,
+		.features = MIXER_QCM2290_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.pingpong = PINGPONG_0,
+		.dspp = DSPP_0,
+		.lm_pair = LM_1,
+	}, {
+		.name = "lm_1", .id = LM_1,
+		.base = 0x45000, .len = 0x320,
+		.features = MIXER_QCM2290_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.pingpong = PINGPONG_1,
+		.dspp = 0,
+		.lm_pair = LM_0,
+	}, {
+		.name = "lm_2", .id = LM_2,
+		.base = 0x46000, .len = 0x320,
+		.features = MIXER_QCM2290_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.pingpong = PINGPONG_2,
+		.dspp = 0,
+	},
+};
+
+static const struct dpu_dspp_cfg qcs615_dspp[] = {
+	{
+		.name = "dspp_0", .id = DSPP_0,
+		.base = 0x54000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sdm845_dspp_sblk,
+	},
+};
+
+static const struct dpu_pingpong_cfg qcs615_pp[] = {
+	{
+		.name = "pingpong_0", .id = PINGPONG_0,
+		.base = 0x70000, .len = 0xd4,
+		.features = PINGPONG_SM8150_MASK,
+		.merge_3d = 0,
+		.sblk = &sdm845_pp_sblk,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+	}, {
+		.name = "pingpong_1", .id = PINGPONG_1,
+		.base = 0x70800, .len = 0xd4,
+		.features = PINGPONG_SM8150_MASK,
+		.merge_3d = 0,
+		.sblk = &sdm845_pp_sblk,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+	}, {
+		.name = "pingpong_2", .id = PINGPONG_2,
+		.base = 0x71000, .len = 0xd4,
+		.features = PINGPONG_SM8150_MASK,
+		.merge_3d = 0,
+		.sblk = &sdm845_pp_sblk,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+	},
+};
+
+static const struct dpu_intf_cfg qcs615_intf[] = {
+	{
+		.name = "intf_0", .id = INTF_0,
+		.base = 0x6a000, .len = 0x280,
+		.features = INTF_SC7180_MASK,
+		.type = INTF_DP,
+		.controller_id = MSM_DP_CONTROLLER_0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+	}, {
+		.name = "intf_1", .id = INTF_1,
+		.base = 0x6a800, .len = 0x2c0,
+		.features = INTF_SC7180_MASK,
+		.type = INTF_DSI,
+		.controller_id = MSM_DSI_CONTROLLER_0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+	}, {
+		.name = "intf_2", .id = INTF_2,
+		.base = 0x6b000, .len = 0x2c0,
+		.features = INTF_SC7180_MASK,
+		.type = INTF_NONE,
+		.controller_id = 0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+	}, {
+		.name = "intf_3", .id = INTF_3,
+		.base = 0x6b800, .len = 0x280,
+		.features = INTF_SC7180_MASK,
+		.type = INTF_DP,
+		.controller_id = MSM_DP_CONTROLLER_1,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+	},
+};
+
+static const struct dpu_perf_cfg qcs615_perf_data = {//here
+	.max_bw_low = 4800000,
+	.max_bw_high = 4800000,
+	.min_core_ib = 2400000,
+	.min_llcc_ib = 0,
+	.min_dram_ib = 800000,
+	.min_prefill_lines = 24,
+	.danger_lut_tbl = {0xf, 0xffff, 0x0},
+	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
+	.qos_lut_tbl = {
+		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
+		.entries = sm8150_qos_linear
+		},
+		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+		.entries = sc7180_qos_macrotile
+		},
+		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+		.entries = sc7180_qos_nrt
+		},
+		/* TODO: macrotile-qseed is different from macrotile */
+	},
+	.cdp_cfg = {
+		{.rd_enable = 1, .wr_enable = 1},
+		{.rd_enable = 1, .wr_enable = 0}
+	},
+	.clk_inefficiency_factor = 105,
+	.bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version qcs615_mdss_ver = {
+	.core_major_ver = 5,
+	.core_minor_ver = 3,
+};
+
+const struct dpu_mdss_cfg dpu_qcs615_cfg = {
+	.mdss_ver = &qcs615_mdss_ver,
+	.caps = &qcs615_dpu_caps,
+	.mdp = &qcs615_mdp,
+	.ctl_count = ARRAY_SIZE(qcs615_ctl),
+	.ctl = qcs615_ctl,
+	.sspp_count = ARRAY_SIZE(qcs615_sspp),
+	.sspp = qcs615_sspp,
+	.mixer_count = ARRAY_SIZE(qcs615_lm),
+	.mixer = qcs615_lm,
+	.dspp_count = ARRAY_SIZE(qcs615_dspp),
+	.dspp = qcs615_dspp,
+	.pingpong_count = ARRAY_SIZE(qcs615_pp),
+	.pingpong = qcs615_pp,
+	.intf_count = ARRAY_SIZE(qcs615_intf),
+	.intf = qcs615_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.perf = &qcs615_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index dcb4fd85e73b9cc05e669043602d69229881c0b4..4b07de941e5855ea9fb1f330130d0bebc760a865 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -685,6 +685,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
 #include "catalog/dpu_5_0_sm8150.h"
 #include "catalog/dpu_5_1_sc8180x.h"
 #include "catalog/dpu_5_2_sm7150.h"
+#include "catalog/dpu_5_3_qcs615.h"
 #include "catalog/dpu_5_4_sm6125.h"
 
 #include "catalog/dpu_6_0_sm8250.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 37e18e820a20a4c4ab9a97da78df19a2ff7cfa00..8e3406ca7cb92dd4a42a7d69d4f57393a0be044a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -843,6 +843,7 @@ extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
 extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
 extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
 extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
+extern const struct dpu_mdss_cfg dpu_qcs615_cfg;
 extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
 extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9bcae53c4f458cd8e400f0e851b791c0f4165085..afa9c04fa9c87b3805ea03fc5f478fcb02cba077 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1457,6 +1457,7 @@ static const struct of_device_id dpu_dt_match[] = {
 	{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
 	{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
 	{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
+	{ .compatible = "qcom,qcs615-dpu", .data = &dpu_qcs615_cfg, },
 	{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
 	{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
 	{ .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 10ba7d153d1cfc9015f527c911c4658558f6e29e..38bcd999b97350d7b5b2a54f1c4f6534dc17ec36 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg = {
 	},
 };
 
+static const struct regulator_bulk_data qcs615_dsi_regulators[] = {
+	{ .supply = "vdda", .init_load_uA = 21800 },
+};
+
+static const struct msm_dsi_config qcs615_dsi_cfg = {
+	.io_offset = DSI_6G_REG_SHIFT,
+	.regulator_data = qcs615_dsi_regulators,
+	.num_regulators = ARRAY_SIZE(qcs615_dsi_regulators),
+	.bus_clk_names = dsi_v2_4_clk_names,
+	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
+	.io_start = {
+		{ 0xae94000 },
+	},
+};
+
 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
 	.link_clk_set_rate = dsi_link_clk_set_rate_v2,
 	.link_clk_enable = dsi_link_clk_enable_v2,
@@ -298,6 +313,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
 		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
 		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
+		&qcs615_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 };
 
 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -23,6 +23,7 @@
 #define MSM_DSI_6G_VER_MINOR_V2_2_0	0x20000000
 #define MSM_DSI_6G_VER_MINOR_V2_2_1	0x20020001
 #define MSM_DSI_6G_VER_MINOR_V2_3_0	0x20030000
+#define MSM_DSI_6G_VER_MINOR_V2_3_1	0x20030001
 #define MSM_DSI_6G_VER_MINOR_V2_4_0	0x20040000
 #define MSM_DSI_6G_VER_MINOR_V2_4_1	0x20040001
 #define MSM_DSI_6G_VER_MINOR_V2_5_0	0x20050000
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index dd58bc0a49eb5ca96370f7832d9251609ac0c552..9ada01d9d43828473501dbb2e7d2272b9dd88e08 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -567,6 +567,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
 	  .data = &dsi_phy_14nm_8953_cfgs },
 	{ .compatible = "qcom,sm6125-dsi-phy-14nm",
 	  .data = &dsi_phy_14nm_2290_cfgs },
+	{ .compatible = "qcom,qcs615-dsi-phy-14nm",
+	  .data = &dsi_phy_14nm_615_cfgs },
 #endif
 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
 	{ .compatible = "qcom,dsi-phy-10nm",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 4953459edd636363614ecad85654614fc95cfa1d..7f2e82a36a93cdd8e80aca293d94ae1566d8aebd 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -49,6 +49,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..42a1c76a25f54be4c8fa799994901e7fd7cfb9d9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = {
 	{ .supply = "vcca", .init_load_uA = 73400 },
 };
 
+static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = {
+	{ .supply = "vdda", .init_load_uA = 36000 },
+};
+
 const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
 	.has_phy_lane = true,
 	.regulator_data = dsi_phy_14nm_17mA_regulators,
@@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
 	.io_start = { 0x5e94400 },
 	.num_dsi_phy = 1,
 };
+
+const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs = {
+	.has_phy_lane = true,
+	.regulator_data = dsi_phy_14nm_36mA_regulators,
+	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators),
+	.ops = {
+		.enable = dsi_14nm_phy_enable,
+		.disable = dsi_14nm_phy_disable,
+		.pll_init = dsi_pll_14nm_init,
+		.save_pll_state = dsi_14nm_pll_save_state,
+		.restore_pll_state = dsi_14nm_pll_restore_state,
+	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
+	.io_start = { 0xae94400 },
+	.num_dsi_phy = 1,
+};
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..d50459090920b85b12d8961985313a172ffcd875 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -662,6 +662,12 @@ static const struct msm_mdss_data sm6125_data = {
 	.highest_bank_bit = 1,
 };
 
+static const struct msm_mdss_data qcs615_data = {
+	.ubwc_enc_version = UBWC_2_0,
+	.ubwc_dec_version = UBWC_2_0,
+	.highest_bank_bit = 1,
+};
+
 static const struct msm_mdss_data sm8250_data = {
 	.ubwc_enc_version = UBWC_4_0,
 	.ubwc_dec_version = UBWC_4_0,
@@ -718,6 +724,7 @@ static const struct of_device_id mdss_dt_match[] = {
 	{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
 	{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
 	{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
+	{ .compatible = "qcom,qcs615-mdss", .data = &qcs615_data },
 	{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
 	{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
 	{ .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },

-- 
2.25.1

Re: [PATCH 3/6] drm/msm/dpu: Add QCS615 support

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:29PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> Add support for the display hardware used on the Qualcomm QCS615 platform.

Not all hardware is described here, comment regarding the DP, etc.

> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +

>  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
>  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +

These changes are not related to the DPU, which you listed as a prefix
in the commit message

>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++

These changes are not related to the DPU

>  drivers/gpu/drm/msm/msm_mdss.c                     |   7 +

These changes are not related to the DPU

For the whole patch: s/qcs615/sm6150/g

>  10 files changed, 320 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..ff7e390db2af9cded05e75b00a5778fdba2cf9ae
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h
> @@ -0,0 +1,268 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DPU_5_3_QCS615_H
> +#define _DPU_5_3_QCS615_H
> +
> +static const struct dpu_caps qcs615_dpu_caps = {
> +	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> +	.max_mixer_blendstages = 0x9,
> +	.has_dim_layer = true,
> +	.has_idle_pc = true,
> +	.max_linewidth = 2160,
> +	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +	.max_hdeci_exp = MAX_HORZ_DECIMATION,
> +	.max_vdeci_exp = MAX_VERT_DECIMATION,
> +};
> +
> +static const struct dpu_mdp_cfg qcs615_mdp = {
> +	.name = "top_0",
> +	.base = 0x0, .len = 0x45c,
> +	.features = 0,
> +	.clk_ctrls = {
> +		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> +		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> +		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> +		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> +		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> +	},
> +};
> +
> +static const struct dpu_ctl_cfg qcs615_ctl[] = {
> +	{
> +		.name = "ctl_0", .id = CTL_0,
> +		.base = 0x1000, .len = 0x1e0,
> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> +	}, {
> +		.name = "ctl_1", .id = CTL_1,
> +		.base = 0x1200, .len = 0x1e0,
> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> +	}, {
> +		.name = "ctl_2", .id = CTL_2,
> +		.base = 0x1400, .len = 0x1e0,
> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> +	}, {
> +		.name = "ctl_3", .id = CTL_3,
> +		.base = 0x1600, .len = 0x1e0,
> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> +	}, {
> +		.name = "ctl_4", .id = CTL_4,
> +		.base = 0x1800, .len = 0x1e0,
> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> +	}, {
> +		.name = "ctl_5", .id = CTL_5,
> +		.base = 0x1a00, .len = 0x1e0,
> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> +	},
> +};
> +
> +static const struct dpu_sspp_cfg qcs615_sspp[] = {
> +	{
> +		.name = "sspp_0", .id = SSPP_VIG0,
> +		.base = 0x4000, .len = 0x1f0,
> +		.features = VIG_SDM845_MASK,//here

here what?

> +		.sblk = &dpu_vig_sblk_qseed3_2_4,
> +		.xin_id = 0,
> +		.type = SSPP_TYPE_VIG,
> +		.clk_ctrl = DPU_CLK_CTRL_VIG0,
> +	}, {
> +		.name = "sspp_8", .id = SSPP_DMA0,
> +		.base = 0x24000, .len = 0x1f0,
> +		.features = DMA_SDM845_MASK,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 1,
> +		.type = SSPP_TYPE_DMA,
> +		.clk_ctrl = DPU_CLK_CTRL_DMA0,
> +	}, {
> +		.name = "sspp_9", .id = SSPP_DMA1,
> +		.base = 0x26000, .len = 0x1f0,
> +		.features = DMA_SDM845_MASK,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 5,
> +		.type = SSPP_TYPE_DMA,
> +		.clk_ctrl = DPU_CLK_CTRL_DMA1,
> +	}, {
> +		.name = "sspp_10", .id = SSPP_DMA2,
> +		.base = 0x28000, .len = 0x1f0,
> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 9,
> +		.type = SSPP_TYPE_DMA,
> +		.clk_ctrl = DPU_CLK_CTRL_DMA2,
> +	}, {
> +		.name = "sspp_11", .id = SSPP_DMA3,
> +		.base = 0x2a000, .len = 0x1f0,
> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 13,
> +		.type = SSPP_TYPE_DMA,
> +		.clk_ctrl = DPU_CLK_CTRL_DMA3,
> +	},
> +};
> +
> +static const struct dpu_lm_cfg qcs615_lm[] = {
> +	{
> +		.name = "lm_0", .id = LM_0,
> +		.base = 0x44000, .len = 0x320,
> +		.features = MIXER_QCM2290_MASK,
> +		.sblk = &sdm845_lm_sblk,
> +		.pingpong = PINGPONG_0,
> +		.dspp = DSPP_0,
> +		.lm_pair = LM_1,
> +	}, {
> +		.name = "lm_1", .id = LM_1,
> +		.base = 0x45000, .len = 0x320,
> +		.features = MIXER_QCM2290_MASK,
> +		.sblk = &sdm845_lm_sblk,
> +		.pingpong = PINGPONG_1,
> +		.dspp = 0,

No need to set absent blocks to 0.

> +		.lm_pair = LM_0,
> +	}, {
> +		.name = "lm_2", .id = LM_2,
> +		.base = 0x46000, .len = 0x320,
> +		.features = MIXER_QCM2290_MASK,
> +		.sblk = &sdm845_lm_sblk,
> +		.pingpong = PINGPONG_2,
> +		.dspp = 0,
> +	},
> +};
> +
> +static const struct dpu_dspp_cfg qcs615_dspp[] = {
> +	{
> +		.name = "dspp_0", .id = DSPP_0,
> +		.base = 0x54000, .len = 0x1800,
> +		.features = DSPP_SC7180_MASK,
> +		.sblk = &sdm845_dspp_sblk,
> +	},
> +};
> +
> +static const struct dpu_pingpong_cfg qcs615_pp[] = {
> +	{
> +		.name = "pingpong_0", .id = PINGPONG_0,
> +		.base = 0x70000, .len = 0xd4,
> +		.features = PINGPONG_SM8150_MASK,
> +		.merge_3d = 0,

No merge_3d support at all? Then just don't say anything.

> +		.sblk = &sdm845_pp_sblk,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> +	}, {
> +		.name = "pingpong_1", .id = PINGPONG_1,
> +		.base = 0x70800, .len = 0xd4,
> +		.features = PINGPONG_SM8150_MASK,
> +		.merge_3d = 0,
> +		.sblk = &sdm845_pp_sblk,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> +	}, {
> +		.name = "pingpong_2", .id = PINGPONG_2,
> +		.base = 0x71000, .len = 0xd4,
> +		.features = PINGPONG_SM8150_MASK,
> +		.merge_3d = 0,
> +		.sblk = &sdm845_pp_sblk,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> +	},
> +};
> +
> +static const struct dpu_intf_cfg qcs615_intf[] = {
> +	{
> +		.name = "intf_0", .id = INTF_0,
> +		.base = 0x6a000, .len = 0x280,
> +		.features = INTF_SC7180_MASK,
> +		.type = INTF_DP,
> +		.controller_id = MSM_DP_CONTROLLER_0,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> +	}, {
> +		.name = "intf_1", .id = INTF_1,
> +		.base = 0x6a800, .len = 0x2c0,
> +		.features = INTF_SC7180_MASK,
> +		.type = INTF_DSI,
> +		.controller_id = MSM_DSI_CONTROLLER_0,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> +		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> +	}, {
> +		.name = "intf_2", .id = INTF_2,
> +		.base = 0x6b000, .len = 0x2c0,
> +		.features = INTF_SC7180_MASK,
> +		.type = INTF_NONE,
> +		.controller_id = 0,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> +	}, {
> +		.name = "intf_3", .id = INTF_3,
> +		.base = 0x6b800, .len = 0x280,
> +		.features = INTF_SC7180_MASK,
> +		.type = INTF_DP,
> +		.controller_id = MSM_DP_CONTROLLER_1,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> +	},
> +};
> +
> +static const struct dpu_perf_cfg qcs615_perf_data = {//here
> +	.max_bw_low = 4800000,
> +	.max_bw_high = 4800000,
> +	.min_core_ib = 2400000,
> +	.min_llcc_ib = 0,
> +	.min_dram_ib = 800000,
> +	.min_prefill_lines = 24,
> +	.danger_lut_tbl = {0xf, 0xffff, 0x0},
> +	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
> +	.qos_lut_tbl = {
> +		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
> +		.entries = sm8150_qos_linear
> +		},
> +		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> +		.entries = sc7180_qos_macrotile
> +		},
> +		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> +		.entries = sc7180_qos_nrt
> +		},
> +		/* TODO: macrotile-qseed is different from macrotile */
> +	},
> +	.cdp_cfg = {
> +		{.rd_enable = 1, .wr_enable = 1},
> +		{.rd_enable = 1, .wr_enable = 0}
> +	},
> +	.clk_inefficiency_factor = 105,
> +	.bw_inefficiency_factor = 120,
> +};
> +
> +static const struct dpu_mdss_version qcs615_mdss_ver = {
> +	.core_major_ver = 5,
> +	.core_minor_ver = 3,
> +};
> +
> +const struct dpu_mdss_cfg dpu_qcs615_cfg = {
> +	.mdss_ver = &qcs615_mdss_ver,
> +	.caps = &qcs615_dpu_caps,
> +	.mdp = &qcs615_mdp,
> +	.ctl_count = ARRAY_SIZE(qcs615_ctl),
> +	.ctl = qcs615_ctl,
> +	.sspp_count = ARRAY_SIZE(qcs615_sspp),
> +	.sspp = qcs615_sspp,
> +	.mixer_count = ARRAY_SIZE(qcs615_lm),
> +	.mixer = qcs615_lm,
> +	.dspp_count = ARRAY_SIZE(qcs615_dspp),
> +	.dspp = qcs615_dspp,
> +	.pingpong_count = ARRAY_SIZE(qcs615_pp),
> +	.pingpong = qcs615_pp,
> +	.intf_count = ARRAY_SIZE(qcs615_intf),
> +	.intf = qcs615_intf,
> +	.vbif_count = ARRAY_SIZE(sdm845_vbif),
> +	.vbif = sdm845_vbif,
> +	.perf = &qcs615_perf_data,
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index dcb4fd85e73b9cc05e669043602d69229881c0b4..4b07de941e5855ea9fb1f330130d0bebc760a865 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -685,6 +685,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>  #include "catalog/dpu_5_0_sm8150.h"
>  #include "catalog/dpu_5_1_sc8180x.h"
>  #include "catalog/dpu_5_2_sm7150.h"
> +#include "catalog/dpu_5_3_qcs615.h"
>  #include "catalog/dpu_5_4_sm6125.h"
>  
>  #include "catalog/dpu_6_0_sm8250.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 37e18e820a20a4c4ab9a97da78df19a2ff7cfa00..8e3406ca7cb92dd4a42a7d69d4f57393a0be044a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -843,6 +843,7 @@ extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>  extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
> +extern const struct dpu_mdss_cfg dpu_qcs615_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>  extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 9bcae53c4f458cd8e400f0e851b791c0f4165085..afa9c04fa9c87b3805ea03fc5f478fcb02cba077 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1457,6 +1457,7 @@ static const struct of_device_id dpu_dt_match[] = {
>  	{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>  	{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>  	{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
> +	{ .compatible = "qcom,qcs615-dpu", .data = &dpu_qcs615_cfg, },
>  	{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>  	{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
>  	{ .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..38bcd999b97350d7b5b2a54f1c4f6534dc17ec36 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg = {
>  	},
>  };
>  
> +static const struct regulator_bulk_data qcs615_dsi_regulators[] = {
> +	{ .supply = "vdda", .init_load_uA = 21800 },
> +};

NAK, this is not a correct description. You missed one of the supplies.

> +
> +static const struct msm_dsi_config qcs615_dsi_cfg = {
> +	.io_offset = DSI_6G_REG_SHIFT,
> +	.regulator_data = qcs615_dsi_regulators,
> +	.num_regulators = ARRAY_SIZE(qcs615_dsi_regulators),
> +	.bus_clk_names = dsi_v2_4_clk_names,
> +	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
> +	.io_start = {
> +		{ 0xae94000 },
> +	},
> +};
> +
>  static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
>  	.link_clk_set_rate = dsi_link_clk_set_rate_v2,
>  	.link_clk_enable = dsi_link_clk_enable_v2,
> @@ -298,6 +313,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>  		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>  	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
>  		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> +	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
> +		&qcs615_dsi_cfg, &msm_dsi_6g_v2_host_ops},

The lsit is sorted.

>  };
>  
>  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -23,6 +23,7 @@
>  #define MSM_DSI_6G_VER_MINOR_V2_2_0	0x20000000
>  #define MSM_DSI_6G_VER_MINOR_V2_2_1	0x20020001
>  #define MSM_DSI_6G_VER_MINOR_V2_3_0	0x20030000
> +#define MSM_DSI_6G_VER_MINOR_V2_3_1	0x20030001
>  #define MSM_DSI_6G_VER_MINOR_V2_4_0	0x20040000
>  #define MSM_DSI_6G_VER_MINOR_V2_4_1	0x20040001
>  #define MSM_DSI_6G_VER_MINOR_V2_5_0	0x20050000
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index dd58bc0a49eb5ca96370f7832d9251609ac0c552..9ada01d9d43828473501dbb2e7d2272b9dd88e08 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -567,6 +567,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>  	  .data = &dsi_phy_14nm_8953_cfgs },
>  	{ .compatible = "qcom,sm6125-dsi-phy-14nm",
>  	  .data = &dsi_phy_14nm_2290_cfgs },
> +	{ .compatible = "qcom,qcs615-dsi-phy-14nm",
> +	  .data = &dsi_phy_14nm_615_cfgs },

Sorted list

>  #endif
>  #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
>  	{ .compatible = "qcom,dsi-phy-10nm",
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 4953459edd636363614ecad85654614fc95cfa1d..7f2e82a36a93cdd8e80aca293d94ae1566d8aebd 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -49,6 +49,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs;

Keep it sorted, also it's not 615. It is qcs615, ergo sm6150.

>  extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..42a1c76a25f54be4c8fa799994901e7fd7cfb9d9 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = {
>  	{ .supply = "vcca", .init_load_uA = 73400 },
>  };
>  
> +static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = {
> +	{ .supply = "vdda", .init_load_uA = 36000 },
> +};
> +
>  const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
>  	.has_phy_lane = true,
>  	.regulator_data = dsi_phy_14nm_17mA_regulators,
> @@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
>  	.io_start = { 0x5e94400 },
>  	.num_dsi_phy = 1,
>  };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs = {
> +	.has_phy_lane = true,
> +	.regulator_data = dsi_phy_14nm_36mA_regulators,
> +	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators),
> +	.ops = {
> +		.enable = dsi_14nm_phy_enable,
> +		.disable = dsi_14nm_phy_disable,
> +		.pll_init = dsi_pll_14nm_init,
> +		.save_pll_state = dsi_14nm_pll_save_state,
> +		.restore_pll_state = dsi_14nm_pll_restore_state,
> +	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
> +	.io_start = { 0xae94400 },
> +	.num_dsi_phy = 1,
> +};
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..d50459090920b85b12d8961985313a172ffcd875 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -662,6 +662,12 @@ static const struct msm_mdss_data sm6125_data = {
>  	.highest_bank_bit = 1,
>  };
>  
> +static const struct msm_mdss_data qcs615_data = {
> +	.ubwc_enc_version = UBWC_2_0,
> +	.ubwc_dec_version = UBWC_2_0,
> +	.highest_bank_bit = 1,

missing reg_bus_bw

> +};
> +
>  static const struct msm_mdss_data sm8250_data = {
>  	.ubwc_enc_version = UBWC_4_0,
>  	.ubwc_dec_version = UBWC_4_0,
> @@ -718,6 +724,7 @@ static const struct of_device_id mdss_dt_match[] = {
>  	{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
>  	{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
>  	{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
> +	{ .compatible = "qcom,qcs615-mdss", .data = &qcs615_data },
>  	{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
>  	{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
>  	{ .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 3/6] drm/msm/dpu: Add QCS615 support

[fange zhang]

On 2024/10/14 18:47, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:29PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
>>
>> Add support for the display hardware used on the Qualcomm QCS615 platform.
> 
> Not all hardware is described here, comment regarding the DP, etc.
> 
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
> 
>>   drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
>>   drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
> 
> These changes are not related to the DPU, which you listed as a prefix
> in the commit message
ok will split it to these four parts.
1. dpu hw catalog
2. mdss
3. dsi phy
4. dsi
sorry, one more question about it.
is the driver patch order correct?
> 
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
> 
> These changes are not related to the DPU
> 
>>   drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
> 
> These changes are not related to the DPU
> 
> For the whole patch: s/qcs615/sm6150/g
> 
>>   10 files changed, 320 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..ff7e390db2af9cded05e75b00a5778fdba2cf9ae
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h
>> @@ -0,0 +1,268 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef _DPU_5_3_QCS615_H
>> +#define _DPU_5_3_QCS615_H
>> +
>> +static const struct dpu_caps qcs615_dpu_caps = {
>> +	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> +	.max_mixer_blendstages = 0x9,
>> +	.has_dim_layer = true,
>> +	.has_idle_pc = true,
>> +	.max_linewidth = 2160,
>> +	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +	.max_hdeci_exp = MAX_HORZ_DECIMATION,
>> +	.max_vdeci_exp = MAX_VERT_DECIMATION,
>> +};
>> +
>> +static const struct dpu_mdp_cfg qcs615_mdp = {
>> +	.name = "top_0",
>> +	.base = 0x0, .len = 0x45c,
>> +	.features = 0,
>> +	.clk_ctrls = {
>> +		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> +		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> +		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
>> +		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
>> +		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
>> +	},
>> +};
>> +
>> +static const struct dpu_ctl_cfg qcs615_ctl[] = {
>> +	{
>> +		.name = "ctl_0", .id = CTL_0,
>> +		.base = 0x1000, .len = 0x1e0,
>> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> +	}, {
>> +		.name = "ctl_1", .id = CTL_1,
>> +		.base = 0x1200, .len = 0x1e0,
>> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> +	}, {
>> +		.name = "ctl_2", .id = CTL_2,
>> +		.base = 0x1400, .len = 0x1e0,
>> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> +	}, {
>> +		.name = "ctl_3", .id = CTL_3,
>> +		.base = 0x1600, .len = 0x1e0,
>> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> +	}, {
>> +		.name = "ctl_4", .id = CTL_4,
>> +		.base = 0x1800, .len = 0x1e0,
>> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> +	}, {
>> +		.name = "ctl_5", .id = CTL_5,
>> +		.base = 0x1a00, .len = 0x1e0,
>> +		.features = BIT(DPU_CTL_ACTIVE_CFG),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> +	},
>> +};
>> +
>> +static const struct dpu_sspp_cfg qcs615_sspp[] = {
>> +	{
>> +		.name = "sspp_0", .id = SSPP_VIG0,
>> +		.base = 0x4000, .len = 0x1f0,
>> +		.features = VIG_SDM845_MASK,//here
> 
> here what?
removed
> 
>> +		.sblk = &dpu_vig_sblk_qseed3_2_4,
>> +		.xin_id = 0,
>> +		.type = SSPP_TYPE_VIG,
>> +		.clk_ctrl = DPU_CLK_CTRL_VIG0,
>> +	}, {
>> +		.name = "sspp_8", .id = SSPP_DMA0,
>> +		.base = 0x24000, .len = 0x1f0,
>> +		.features = DMA_SDM845_MASK,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 1,
>> +		.type = SSPP_TYPE_DMA,
>> +		.clk_ctrl = DPU_CLK_CTRL_DMA0,
>> +	}, {
>> +		.name = "sspp_9", .id = SSPP_DMA1,
>> +		.base = 0x26000, .len = 0x1f0,
>> +		.features = DMA_SDM845_MASK,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 5,
>> +		.type = SSPP_TYPE_DMA,
>> +		.clk_ctrl = DPU_CLK_CTRL_DMA1,
>> +	}, {
>> +		.name = "sspp_10", .id = SSPP_DMA2,
>> +		.base = 0x28000, .len = 0x1f0,
>> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 9,
>> +		.type = SSPP_TYPE_DMA,
>> +		.clk_ctrl = DPU_CLK_CTRL_DMA2,
>> +	}, {
>> +		.name = "sspp_11", .id = SSPP_DMA3,
>> +		.base = 0x2a000, .len = 0x1f0,
>> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 13,
>> +		.type = SSPP_TYPE_DMA,
>> +		.clk_ctrl = DPU_CLK_CTRL_DMA3,
>> +	},
>> +};
>> +
>> +static const struct dpu_lm_cfg qcs615_lm[] = {
>> +	{
>> +		.name = "lm_0", .id = LM_0,
>> +		.base = 0x44000, .len = 0x320,
>> +		.features = MIXER_QCM2290_MASK,
>> +		.sblk = &sdm845_lm_sblk,
>> +		.pingpong = PINGPONG_0,
>> +		.dspp = DSPP_0,
>> +		.lm_pair = LM_1,
>> +	}, {
>> +		.name = "lm_1", .id = LM_1,
>> +		.base = 0x45000, .len = 0x320,
>> +		.features = MIXER_QCM2290_MASK,
>> +		.sblk = &sdm845_lm_sblk,
>> +		.pingpong = PINGPONG_1,
>> +		.dspp = 0,
> 
> No need to set absent blocks to 0.
removed
> 
>> +		.lm_pair = LM_0,
>> +	}, {
>> +		.name = "lm_2", .id = LM_2,
>> +		.base = 0x46000, .len = 0x320,
>> +		.features = MIXER_QCM2290_MASK,
>> +		.sblk = &sdm845_lm_sblk,
>> +		.pingpong = PINGPONG_2,
>> +		.dspp = 0,
>> +	},
>> +};
>> +
>> +static const struct dpu_dspp_cfg qcs615_dspp[] = {
>> +	{
>> +		.name = "dspp_0", .id = DSPP_0,
>> +		.base = 0x54000, .len = 0x1800,
>> +		.features = DSPP_SC7180_MASK,
>> +		.sblk = &sdm845_dspp_sblk,
>> +	},
>> +};
>> +
>> +static const struct dpu_pingpong_cfg qcs615_pp[] = {
>> +	{
>> +		.name = "pingpong_0", .id = PINGPONG_0,
>> +		.base = 0x70000, .len = 0xd4,
>> +		.features = PINGPONG_SM8150_MASK,
>> +		.merge_3d = 0,
> 
> No merge_3d support at all? Then just don't say anything.
removed
> 
>> +		.sblk = &sdm845_pp_sblk,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> +	}, {
>> +		.name = "pingpong_1", .id = PINGPONG_1,
>> +		.base = 0x70800, .len = 0xd4,
>> +		.features = PINGPONG_SM8150_MASK,
>> +		.merge_3d = 0,
>> +		.sblk = &sdm845_pp_sblk,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> +	}, {
>> +		.name = "pingpong_2", .id = PINGPONG_2,
>> +		.base = 0x71000, .len = 0xd4,
>> +		.features = PINGPONG_SM8150_MASK,
>> +		.merge_3d = 0,
>> +		.sblk = &sdm845_pp_sblk,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
>> +	},
>> +};
>> +
>> +static const struct dpu_intf_cfg qcs615_intf[] = {
>> +	{
>> +		.name = "intf_0", .id = INTF_0,
>> +		.base = 0x6a000, .len = 0x280,
>> +		.features = INTF_SC7180_MASK,
>> +		.type = INTF_DP,
>> +		.controller_id = MSM_DP_CONTROLLER_0,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
>> +	}, {
>> +		.name = "intf_1", .id = INTF_1,
>> +		.base = 0x6a800, .len = 0x2c0,
>> +		.features = INTF_SC7180_MASK,
>> +		.type = INTF_DSI,
>> +		.controller_id = MSM_DSI_CONTROLLER_0,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> +		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
>> +	}, {
>> +		.name = "intf_2", .id = INTF_2,
>> +		.base = 0x6b000, .len = 0x2c0,
>> +		.features = INTF_SC7180_MASK,
>> +		.type = INTF_NONE,
>> +		.controller_id = 0,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
>> +	}, {
>> +		.name = "intf_3", .id = INTF_3,
>> +		.base = 0x6b800, .len = 0x280,
>> +		.features = INTF_SC7180_MASK,
>> +		.type = INTF_DP,
>> +		.controller_id = MSM_DP_CONTROLLER_1,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
>> +	},
>> +};
>> +
>> +static const struct dpu_perf_cfg qcs615_perf_data = {//here
>> +	.max_bw_low = 4800000,
>> +	.max_bw_high = 4800000,
>> +	.min_core_ib = 2400000,
>> +	.min_llcc_ib = 0,
>> +	.min_dram_ib = 800000,
>> +	.min_prefill_lines = 24,
>> +	.danger_lut_tbl = {0xf, 0xffff, 0x0},
>> +	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
>> +	.qos_lut_tbl = {
>> +		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
>> +		.entries = sm8150_qos_linear
>> +		},
>> +		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
>> +		.entries = sc7180_qos_macrotile
>> +		},
>> +		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> +		.entries = sc7180_qos_nrt
>> +		},
>> +		/* TODO: macrotile-qseed is different from macrotile */
>> +	},
>> +	.cdp_cfg = {
>> +		{.rd_enable = 1, .wr_enable = 1},
>> +		{.rd_enable = 1, .wr_enable = 0}
>> +	},
>> +	.clk_inefficiency_factor = 105,
>> +	.bw_inefficiency_factor = 120,
>> +};
>> +
>> +static const struct dpu_mdss_version qcs615_mdss_ver = {
>> +	.core_major_ver = 5,
>> +	.core_minor_ver = 3,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_qcs615_cfg = {
>> +	.mdss_ver = &qcs615_mdss_ver,
>> +	.caps = &qcs615_dpu_caps,
>> +	.mdp = &qcs615_mdp,
>> +	.ctl_count = ARRAY_SIZE(qcs615_ctl),
>> +	.ctl = qcs615_ctl,
>> +	.sspp_count = ARRAY_SIZE(qcs615_sspp),
>> +	.sspp = qcs615_sspp,
>> +	.mixer_count = ARRAY_SIZE(qcs615_lm),
>> +	.mixer = qcs615_lm,
>> +	.dspp_count = ARRAY_SIZE(qcs615_dspp),
>> +	.dspp = qcs615_dspp,
>> +	.pingpong_count = ARRAY_SIZE(qcs615_pp),
>> +	.pingpong = qcs615_pp,
>> +	.intf_count = ARRAY_SIZE(qcs615_intf),
>> +	.intf = qcs615_intf,
>> +	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>> +	.vbif = sdm845_vbif,
>> +	.perf = &qcs615_perf_data,
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index dcb4fd85e73b9cc05e669043602d69229881c0b4..4b07de941e5855ea9fb1f330130d0bebc760a865 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -685,6 +685,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>>   #include "catalog/dpu_5_0_sm8150.h"
>>   #include "catalog/dpu_5_1_sc8180x.h"
>>   #include "catalog/dpu_5_2_sm7150.h"
>> +#include "catalog/dpu_5_3_qcs615.h"
>>   #include "catalog/dpu_5_4_sm6125.h"
>>   
>>   #include "catalog/dpu_6_0_sm8250.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 37e18e820a20a4c4ab9a97da78df19a2ff7cfa00..8e3406ca7cb92dd4a42a7d69d4f57393a0be044a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -843,6 +843,7 @@ extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
>> +extern const struct dpu_mdss_cfg dpu_qcs615_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>   extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 9bcae53c4f458cd8e400f0e851b791c0f4165085..afa9c04fa9c87b3805ea03fc5f478fcb02cba077 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1457,6 +1457,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>   	{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>   	{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>   	{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
>> +	{ .compatible = "qcom,qcs615-dpu", .data = &dpu_qcs615_cfg, },
>>   	{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>   	{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
>>   	{ .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> index 10ba7d153d1cfc9015f527c911c4658558f6e29e..38bcd999b97350d7b5b2a54f1c4f6534dc17ec36 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> @@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg = {
>>   	},
>>   };
>>   
>> +static const struct regulator_bulk_data qcs615_dsi_regulators[] = {
>> +	{ .supply = "vdda", .init_load_uA = 21800 },
>> +};
> 
> NAK, this is not a correct description. You missed one of the supplies.
will remove qcs615_dsi_regulators, and reuse sdm845_dsi_cfg
> 
>> +
>> +static const struct msm_dsi_config qcs615_dsi_cfg = {
>> +	.io_offset = DSI_6G_REG_SHIFT,
>> +	.regulator_data = qcs615_dsi_regulators,
>> +	.num_regulators = ARRAY_SIZE(qcs615_dsi_regulators),
>> +	.bus_clk_names = dsi_v2_4_clk_names,
>> +	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
>> +	.io_start = {
>> +		{ 0xae94000 },
>> +	},
>> +};
>> +
>>   static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
>>   	.link_clk_set_rate = dsi_link_clk_set_rate_v2,
>>   	.link_clk_enable = dsi_link_clk_enable_v2,
>> @@ -298,6 +313,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>>   		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>>   	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
>>   		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>> +	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
>> +		&qcs615_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> 
> The lsit is sorted.
got it, will move it behind V2_3_0
and change qcs615_dsi_cfg to sdm845_dsi_cfg
> 
>>   };
>>   
>>   const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5f073bd560c496 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> @@ -23,6 +23,7 @@
>>   #define MSM_DSI_6G_VER_MINOR_V2_2_0	0x20000000
>>   #define MSM_DSI_6G_VER_MINOR_V2_2_1	0x20020001
>>   #define MSM_DSI_6G_VER_MINOR_V2_3_0	0x20030000
>> +#define MSM_DSI_6G_VER_MINOR_V2_3_1	0x20030001
>>   #define MSM_DSI_6G_VER_MINOR_V2_4_0	0x20040000
>>   #define MSM_DSI_6G_VER_MINOR_V2_4_1	0x20040001
>>   #define MSM_DSI_6G_VER_MINOR_V2_5_0	0x20050000
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> index dd58bc0a49eb5ca96370f7832d9251609ac0c552..9ada01d9d43828473501dbb2e7d2272b9dd88e08 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> @@ -567,6 +567,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>>   	  .data = &dsi_phy_14nm_8953_cfgs },
>>   	{ .compatible = "qcom,sm6125-dsi-phy-14nm",
>>   	  .data = &dsi_phy_14nm_2290_cfgs },
>> +	{ .compatible = "qcom,qcs615-dsi-phy-14nm",
>> +	  .data = &dsi_phy_14nm_615_cfgs },
> 
> Sorted list
will change 615 to 6150
> 
>>   #endif
>>   #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
>>   	{ .compatible = "qcom,dsi-phy-10nm",
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> index 4953459edd636363614ecad85654614fc95cfa1d..7f2e82a36a93cdd8e80aca293d94ae1566d8aebd 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> @@ -49,6 +49,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
>> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs;
> 
> Keep it sorted, also it's not 615. It is qcs615, ergo sm6150.
got it. will change dsi_phy_14nm_615_cfgs to dsi_phy_14nm_6150_cfgs
> 
>>   extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..42a1c76a25f54be4c8fa799994901e7fd7cfb9d9 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> @@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = {
>>   	{ .supply = "vcca", .init_load_uA = 73400 },
>>   };
>>   
>> +static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = {
>> +	{ .supply = "vdda", .init_load_uA = 36000 },
>> +};
>> +
>>   const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
>>   	.has_phy_lane = true,
>>   	.regulator_data = dsi_phy_14nm_17mA_regulators,
>> @@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
>>   	.io_start = { 0x5e94400 },
>>   	.num_dsi_phy = 1,
>>   };
>> +
>> +const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs = {
>> +	.has_phy_lane = true,
>> +	.regulator_data = dsi_phy_14nm_36mA_regulators,
>> +	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators),
>> +	.ops = {
>> +		.enable = dsi_14nm_phy_enable,
>> +		.disable = dsi_14nm_phy_disable,
>> +		.pll_init = dsi_pll_14nm_init,
>> +		.save_pll_state = dsi_14nm_pll_save_state,
>> +		.restore_pll_state = dsi_14nm_pll_restore_state,
>> +	},
>> +	.min_pll_rate = VCO_MIN_RATE,
>> +	.max_pll_rate = VCO_MAX_RATE,
>> +	.io_start = { 0xae94400 },
>> +	.num_dsi_phy = 1,
>> +};
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..d50459090920b85b12d8961985313a172ffcd875 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -662,6 +662,12 @@ static const struct msm_mdss_data sm6125_data = {
>>   	.highest_bank_bit = 1,
>>   };
>>   
>> +static const struct msm_mdss_data qcs615_data = {
>> +	.ubwc_enc_version = UBWC_2_0,
>> +	.ubwc_dec_version = UBWC_2_0,
>> +	.highest_bank_bit = 1,
> 
> missing reg_bus_bw
got it, will add this line
.reg_bus_bw = 76800,
> 
>> +};
>> +
>>   static const struct msm_mdss_data sm8250_data = {
>>   	.ubwc_enc_version = UBWC_4_0,
>>   	.ubwc_dec_version = UBWC_4_0,
>> @@ -718,6 +724,7 @@ static const struct of_device_id mdss_dt_match[] = {
>>   	{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
>>   	{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
>>   	{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
>> +	{ .compatible = "qcom,qcs615-mdss", .data = &qcs615_data },
>>   	{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
>>   	{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
>>   	{ .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
>>
>> -- 
>> 2.25.1
>>
>>
> 

Re: [PATCH 3/6] drm/msm/dpu: Add QCS615 support

[Dmitry Baryshkov]

On Mon, 18 Nov 2024 at 10:52, fange zhang <quic_fangez@quicinc.com> wrote:
>
>
>
> On 2024/10/14 18:47, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 05:47:29PM +0800, fangez via B4 Relay wrote:
> >> From: lliu6 <quic_lliu6@quicinc.com>
> >>
> >> Add support for the display hardware used on the Qualcomm QCS615 platform.
> >
> > Not all hardware is described here, comment regarding the DP, etc.
> >
> >>
> >> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> >> ---
> >>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
> >
> >>   drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
> >>   drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
> >
> > These changes are not related to the DPU, which you listed as a prefix
> > in the commit message
> ok will split it to these four parts.
> 1. dpu hw catalog
> 2. mdss
> 3. dsi phy
> 4. dsi
> sorry, one more question about it.
> is the driver patch order correct?

Usually MDSS comes before DPU

> >
> >>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
> >>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
> >>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
> >
> > These changes are not related to the DPU
> >
> >>   drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
> >
> > These changes are not related to the DPU
> >
> > For the whole patch: s/qcs615/sm6150/g
> >
> >>   10 files changed, 320 insertions(+)
> >>


-- 
With best wishes
Dmitry

Re: [PATCH 3/6] drm/msm/dpu: Add QCS615 support

[fange zhang]

On 2024/11/18 18:55, Dmitry Baryshkov wrote:
> On Mon, 18 Nov 2024 at 10:52, fange zhang <quic_fangez@quicinc.com> wrote:
>>
>>
>>
>> On 2024/10/14 18:47, Dmitry Baryshkov wrote:
>>> On Mon, Oct 14, 2024 at 05:47:29PM +0800, fangez via B4 Relay wrote:
>>>> From: lliu6 <quic_lliu6@quicinc.com>
>>>>
>>>> Add support for the display hardware used on the Qualcomm QCS615 platform.
>>>
>>> Not all hardware is described here, comment regarding the DP, etc.
Fixed in v2
for DPU part, commit message would be:

Author: Li Liu <quic_lliu6@quicinc.com>
Date:   Tue Oct 15 12:50:26 2024 +0800

     drm/msm/dpu: Add SM6150 support

     Add definitions for the display hardware
     used on the Qualcomm SM6150 platform.

     Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
     Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>

with these file changes:
  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

>>>
>>>>
>>>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>>>> ---
>>>>    .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>>>
>>>>    drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
>>>>    drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
>>>
>>> These changes are not related to the DPU, which you listed as a prefix
>>> in the commit message
>> ok will split it to these four parts.
>> 1. dpu hw catalog
>> 2. mdss
>> 3. dsi phy
>> 4. dsi
>> sorry, one more question about it.
>> is the driver patch order correct?
> 
> Usually MDSS comes before DPU
Got it, will fix in next patch.
New driver patch order as follows:
drm/msm: mdss: Add SM6150 support
drm/msm/dpu: Add SM6150 support
drm/msm/dsi: Add support for SM6150
drm/msm/dsi: Add dsi phy support for SM6150

> 
>>>
>>>>    drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
>>>>    drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
>>>>    drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
>>>
>>> These changes are not related to the DPU
>>>
>>>>    drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
>>>
>>> These changes are not related to the DPU
>>>
>>> For the whole patch: s/qcs615/sm6150/g
>>>
>>>>    10 files changed, 320 insertions(+)
>>>>
> 
> 

Re: [PATCH 3/6] drm/msm/dpu: Add QCS615 support

[Dmitry Baryshkov]

On Fri, 22 Nov 2024 at 09:36, fange zhang <quic_fangez@quicinc.com> wrote:
>
>
>
> On 2024/11/18 18:55, Dmitry Baryshkov wrote:
> > On Mon, 18 Nov 2024 at 10:52, fange zhang <quic_fangez@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 2024/10/14 18:47, Dmitry Baryshkov wrote:
> >>> On Mon, Oct 14, 2024 at 05:47:29PM +0800, fangez via B4 Relay wrote:
> >>>> From: lliu6 <quic_lliu6@quicinc.com>
> >>>>
> >>>> Add support for the display hardware used on the Qualcomm QCS615 platform.
> >>>
> >>> Not all hardware is described here, comment regarding the DP, etc.
> Fixed in v2
> for DPU part, commit message would be:
>
> Author: Li Liu <quic_lliu6@quicinc.com>
> Date:   Tue Oct 15 12:50:26 2024 +0800
>
>      drm/msm/dpu: Add SM6150 support
>
>      Add definitions for the display hardware
>      used on the Qualcomm SM6150 platform.

Please wrap the lines in the commit message according to the
established recommendations rather than doing it at some other point.

>
>      Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>      Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>
> with these file changes:
>   drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>
> >>>
> >>>>
> >>>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> >>>> ---
> >>>>    .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
> >>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
> >>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
> >>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
> >>>
> >>>>    drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
> >>>>    drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
> >>>
> >>> These changes are not related to the DPU, which you listed as a prefix
> >>> in the commit message
> >> ok will split it to these four parts.
> >> 1. dpu hw catalog
> >> 2. mdss
> >> 3. dsi phy
> >> 4. dsi
> >> sorry, one more question about it.
> >> is the driver patch order correct?
> >
> > Usually MDSS comes before DPU
> Got it, will fix in next patch.
> New driver patch order as follows:
> drm/msm: mdss: Add SM6150 support
> drm/msm/dpu: Add SM6150 support
> drm/msm/dsi: Add support for SM6150
> drm/msm/dsi: Add dsi phy support for SM6150
>
> >
> >>>
> >>>>    drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
> >>>>    drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
> >>>>    drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
> >>>
> >>> These changes are not related to the DPU
> >>>
> >>>>    drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
> >>>
> >>> These changes are not related to the DPU
> >>>
> >>> For the whole patch: s/qcs615/sm6150/g
> >>>
> >>>>    10 files changed, 320 insertions(+)
> >>>>
> >
> >
>


-- 
With best wishes
Dmitry

Re: [PATCH 3/6] drm/msm/dpu: Add QCS615 support

[fange zhang]

On 2024/11/22 15:37, Dmitry Baryshkov wrote:
> On Fri, 22 Nov 2024 at 09:36, fange zhang <quic_fangez@quicinc.com> wrote:
>>
>>
>>
>> On 2024/11/18 18:55, Dmitry Baryshkov wrote:
>>> On Mon, 18 Nov 2024 at 10:52, fange zhang <quic_fangez@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 2024/10/14 18:47, Dmitry Baryshkov wrote:
>>>>> On Mon, Oct 14, 2024 at 05:47:29PM +0800, fangez via B4 Relay wrote:
>>>>>> From: lliu6 <quic_lliu6@quicinc.com>
>>>>>>
>>>>>> Add support for the display hardware used on the Qualcomm QCS615 platform.
>>>>>
>>>>> Not all hardware is described here, comment regarding the DP, etc.
>> Fixed in v2
>> for DPU part, commit message would be:
>>
>> Author: Li Liu <quic_lliu6@quicinc.com>
>> Date:   Tue Oct 15 12:50:26 2024 +0800
>>
>>       drm/msm/dpu: Add SM6150 support
>>
>>       Add definitions for the display hardware
>>       used on the Qualcomm SM6150 platform.
> 
> Please wrap the lines in the commit message according to the
> established recommendations rather than doing it at some other point.
got it, will change it to
Add definitions for the display hardware used on the Qualcomm SM6150 
platform.
> 
>>
>>       Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>>       Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>>
>> with these file changes:
>>    drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>    drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>
>>>>>
>>>>>>
>>>>>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>>>>>> ---
>>>>>>     .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 +++++++++++++++++++++
>>>>>>     drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>>>>>>     drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>>>>>>     drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>>>>>
>>>>>>     drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
>>>>>>     drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
>>>>>
>>>>> These changes are not related to the DPU, which you listed as a prefix
>>>>> in the commit message
>>>> ok will split it to these four parts.
>>>> 1. dpu hw catalog
>>>> 2. mdss
>>>> 3. dsi phy
>>>> 4. dsi
>>>> sorry, one more question about it.
>>>> is the driver patch order correct?
>>>
>>> Usually MDSS comes before DPU
>> Got it, will fix in next patch.
>> New driver patch order as follows:
>> drm/msm: mdss: Add SM6150 support
>> drm/msm/dpu: Add SM6150 support
>> drm/msm/dsi: Add support for SM6150
>> drm/msm/dsi: Add dsi phy support for SM6150
>>
>>>
>>>>>
>>>>>>     drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
>>>>>>     drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
>>>>>>     drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
>>>>>
>>>>> These changes are not related to the DPU
>>>>>
>>>>>>     drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
>>>>>
>>>>> These changes are not related to the DPU
>>>>>
>>>>> For the whole patch: s/qcs615/sm6150/g
>>>>>
>>>>>>     10 files changed, 320 insertions(+)
>>>>>>
>>>
>>>
>>
> 
> 

[PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy

[fangez via B4 Relay]

From: lliu6 <quic_lliu6@quicinc.com>

QCS615 platform uses the 14nm DSI PHY driver.

Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
---
 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
@@ -20,6 +20,7 @@ properties:
       - qcom,dsi-phy-14nm-660
       - qcom,dsi-phy-14nm-8953
       - qcom,sm6125-dsi-phy-14nm
+      - qcom,qcs615-dsi-phy-14nm
 
   reg:
     items:

-- 
2.25.1

Re: [PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:30PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> QCS615 platform uses the 14nm DSI PHY driver.

- bindings describe the hardware, not the drivers.
- other platforms also have 14nm DSI PHY. Why do you need a separate
  compatible?

> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> @@ -20,6 +20,7 @@ properties:
>        - qcom,dsi-phy-14nm-660
>        - qcom,dsi-phy-14nm-8953
>        - qcom,sm6125-dsi-phy-14nm
> +      - qcom,qcs615-dsi-phy-14nm
>  
>    reg:
>      items:
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy

[fange zhang]

On 2024/10/14 18:30, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:30PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
>>
>> QCS615 platform uses the 14nm DSI PHY driver.
> 
> - bindings describe the hardware, not the drivers.
> - other platforms also have 14nm DSI PHY. Why do you need a separate
>    compatible?
We need to introduce a new regulator configuration for the PHY: 
dsi_phy_14nm_36mA_regulators. This configuration has not been used before.

> 
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644
>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> @@ -20,6 +20,7 @@ properties:
>>         - qcom,dsi-phy-14nm-660
>>         - qcom,dsi-phy-14nm-8953
>>         - qcom,sm6125-dsi-phy-14nm
>> +      - qcom,qcs615-dsi-phy-14nm
sorry, still have some question about this yaml file.
it's necessary for b4 check

checkpatch.pl: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:564: WARNING: DT 
compatible string "qcom,dsi-phy-14nm-6150" appears un-doc
umented -- check ./Documentation/devicetree/bindings/

need to add this new 6150 node for dsi-phy-14nm.
shall i add it?

>>   
>>     reg:
>>       items:
>>
>> -- 
>> 2.25.1
>>
>>
> 

and could you please help to review the new version?
Author: Li Liu <quic_lliu6@quicinc.com>
Date:   Tue Nov 19 12:35:12 2024 +0800

     dt-bindings: display/msm: Add SM6150 DSI phy

     Add new compatible for SM6150 with dsi_phy_14nm_36mA_regulators

     Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
     Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>

diff --git 
a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml 
b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
index 52bbe132e6da..fd6eb3434450 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
@@ -17,6 +17,7 @@ properties:
      enum:
        - qcom,dsi-phy-14nm
        - qcom,dsi-phy-14nm-2290
+      - qcom,dsi-phy-14nm-6150
        - qcom,dsi-phy-14nm-660
        - qcom,dsi-phy-14nm-8953
        - qcom,sm6125-dsi-phy-14nm

Re: [PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy

[Dmitry Baryshkov]

On Tue, Nov 19, 2024 at 12:45:00PM +0800, fange zhang wrote:
> 
> 
> On 2024/10/14 18:30, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 05:47:30PM +0800, fangez via B4 Relay wrote:
> > > From: lliu6 <quic_lliu6@quicinc.com>
> > > 
> > > QCS615 platform uses the 14nm DSI PHY driver.
> > 
> > - bindings describe the hardware, not the drivers.
> > - other platforms also have 14nm DSI PHY. Why do you need a separate
> >    compatible?
> We need to introduce a new regulator configuration for the PHY:
> dsi_phy_14nm_36mA_regulators. This configuration has not been used before.
> 
> > 
> > > 
> > > Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> > > ---
> > >   Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> > > index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644
> > > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> > > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> > > @@ -20,6 +20,7 @@ properties:
> > >         - qcom,dsi-phy-14nm-660
> > >         - qcom,dsi-phy-14nm-8953
> > >         - qcom,sm6125-dsi-phy-14nm
> > > +      - qcom,qcs615-dsi-phy-14nm

qcom,sm6150-dsi-phy-14nm

> sorry, still have some question about this yaml file.
> it's necessary for b4 check
> 
> checkpatch.pl: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:564: WARNING: DT
> compatible string "qcom,dsi-phy-14nm-6150" appears un-doc
> umented -- check ./Documentation/devicetree/bindings/
> 
> need to add this new 6150 node for dsi-phy-14nm.
> shall i add it?
> 
> > >     reg:
> > >       items:
> > > 
> > > -- 
> > > 2.25.1
> > > 
> > > 
> > 
> 
> and could you please help to review the new version?
> Author: Li Liu <quic_lliu6@quicinc.com>
> Date:   Tue Nov 19 12:35:12 2024 +0800
> 
>     dt-bindings: display/msm: Add SM6150 DSI phy
> 
>     Add new compatible for SM6150 with dsi_phy_14nm_36mA_regulators
> 
>     Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>     Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> index 52bbe132e6da..fd6eb3434450 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> @@ -17,6 +17,7 @@ properties:
>      enum:
>        - qcom,dsi-phy-14nm
>        - qcom,dsi-phy-14nm-2290
> +      - qcom,dsi-phy-14nm-6150

qcom,sm6150-dsi-phy-14nm

>        - qcom,dsi-phy-14nm-660
>        - qcom,dsi-phy-14nm-8953
>        - qcom,sm6125-dsi-phy-14nm
> 

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy

[fange zhang]

On 2024/11/20 20:22, Dmitry Baryshkov wrote:
> On Tue, Nov 19, 2024 at 12:45:00PM +0800, fange zhang wrote:
>>
>>
>> On 2024/10/14 18:30, Dmitry Baryshkov wrote:
>>> On Mon, Oct 14, 2024 at 05:47:30PM +0800, fangez via B4 Relay wrote:
>>>> From: lliu6 <quic_lliu6@quicinc.com>
>>>>
>>>> QCS615 platform uses the 14nm DSI PHY driver.
>>>
>>> - bindings describe the hardware, not the drivers.
>>> - other platforms also have 14nm DSI PHY. Why do you need a separate
>>>     compatible?
>> We need to introduce a new regulator configuration for the PHY:
>> dsi_phy_14nm_36mA_regulators. This configuration has not been used before.
>>
>>>
>>>>
>>>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>>>> ---
>>>>    Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>>>> index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644
>>>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>>>> @@ -20,6 +20,7 @@ properties:
>>>>          - qcom,dsi-phy-14nm-660
>>>>          - qcom,dsi-phy-14nm-8953
>>>>          - qcom,sm6125-dsi-phy-14nm
>>>> +      - qcom,qcs615-dsi-phy-14nm
> 
> qcom,sm6150-dsi-phy-14nm
ok, will fix it in next patch >> sorry, still have some question about 
this yaml file.
>> it's necessary for b4 check
>>
>> checkpatch.pl: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:564: WARNING: DT
>> compatible string "qcom,dsi-phy-14nm-6150" appears un-doc
>> umented -- check ./Documentation/devicetree/bindings/
>>
>> need to add this new 6150 node for dsi-phy-14nm.
>> shall i add it?
>>
>>>>      reg:
>>>>        items:
>>>>
>>>> -- 
>>>> 2.25.1
>>>>
>>>>
>>>
>>
>> and could you please help to review the new version?
>> Author: Li Liu <quic_lliu6@quicinc.com>
>> Date:   Tue Nov 19 12:35:12 2024 +0800
>>
>>      dt-bindings: display/msm: Add SM6150 DSI phy
>>
>>      Add new compatible for SM6150 with dsi_phy_14nm_36mA_regulators
>>
>>      Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>>      Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> index 52bbe132e6da..fd6eb3434450 100644
>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>> @@ -17,6 +17,7 @@ properties:
>>       enum:
>>         - qcom,dsi-phy-14nm
>>         - qcom,dsi-phy-14nm-2290
>> +      - qcom,dsi-phy-14nm-6150
> 
> qcom,sm6150-dsi-phy-14nm
ok, will fix it in next patch
> 
>>         - qcom,dsi-phy-14nm-660
>>         - qcom,dsi-phy-14nm-8953
>>         - qcom,sm6125-dsi-phy-14nm
>>
> 

Re: [PATCH 4/6] dt-bindings: display/msm: Add QCS615 DSI phy

[Krzysztof Kozlowski]

On 14/10/2024 11:47, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> QCS615 platform uses the 14nm DSI PHY driver.

This patchset is not ready for submission. Please perform first internal
review.

Please run scripts/checkpatch.pl and fix reported warnings. Then please
run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
Some warnings can be ignored, especially from --strict run, but the code
here looks like it needs a fix. Feel free to get in touch if the warning
is not clear.

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.

Please kindly resend and include all necessary To/Cc entries.
</form letter>

> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> @@ -20,6 +20,7 @@ properties:
>        - qcom,dsi-phy-14nm-660
>        - qcom,dsi-phy-14nm-8953
>        - qcom,sm6125-dsi-phy-14nm
> +      - qcom,qcs615-dsi-phy-14nm

Keep the order.

Best regards,
Krzysztof

[PATCH 5/6] dt-bindings: display/msm: Add QCS615 MDSS & DPU

[fangez via B4 Relay]

From: lliu6 <quic_lliu6@quicinc.com>

Add bindings for the display hardware on QCS615.

Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
---
 .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
 .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
 2 files changed, 395 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..35339092cb4f905541a7f70f42166bd0b0b7dee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS615 Display DPU
+
+maintainers:
+  - lliu6 <quic_lliu6@quicinc.com>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,qcs615-dpu
+
+  reg:
+    items:
+      - description: Address offset and size for mdp register set
+      - description: Address offset and size for vbif register set
+
+  reg-names:
+    items:
+      - const: mdp
+      - const: vbif
+
+  clocks:
+    items:
+      - description: Display ahb clock
+      - description: Display hf axi clock
+      - description: Display core clock
+      - description: Display vsync clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+      - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
+    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    display-controller@ae01000 {
+        compatible = "qcom,qcs615-dpu";
+        reg = <0x0ae01000 0x8f000>,
+              <0x0aeb0000 0x2008>;
+        reg-names = "mdp", "vbif";
+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&gcc GCC_DISP_HF_AXI_CLK>,
+                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+        clock-names = "iface", "bus", "lut" "core", "vsync";
+
+        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+        assigned-clock-rates = <19200000>;
+
+        operating-points-v2 = <&mdp_opp_table>;
+
+        interrupt-parent = <&mdss>;
+        interrupts = <0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+	        dpu_intf0_out: endpoint {
+		};
+	    };
+
+            port@1 {
+		reg = <1>;
+		dpu_intf1_out: endpoint {
+		    remote-endpoint = <&mdss_dsi0_in>;
+		};
+	    };
+
+        };
+
+        mdp_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-375000000 {
+                opp-hz = /bits/ 64 <375000000>;
+                required-opps = <&rpmhpd_opp_svs_l1>;
+            };
+
+            opp-500000000 {
+                opp-hz = /bits/ 64 <500000000>;
+                required-opps = <&rpmhpd_opp_nom>;
+            };
+
+            opp-575000000 {
+                opp-hz = /bits/ 64 <575000000>;
+                required-opps = <&rpmhpd_opp_turbo>;
+            };
+
+            opp-650000000 {
+                opp-hz = /bits/ 64 <650000000>;
+                required-opps = <&rpmhpd_opp_turbo_l1>;
+            };
+        };
+    };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..fdad15c358892306dcb2c1b78319934c504cfc2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
@@ -0,0 +1,278 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS615 Display MDSS
+
+maintainers:
+  - lliu6 <quic_lliu6@quicinc.com>
+
+description:
+  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+  bindings of MDSS are mentioned for QCS615 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: qcom,qcs615-mdss
+
+  clocks:
+    items:
+      - description: Display AHB clock from gcc
+      - description: Display hf axi clock
+      - description: Display sf axi clock
+      - description: Display core clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: nrt_bus
+      - const: core
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: qcom,qcs615-dpu
+
+  "^displayport-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        contains:
+          const: qcom,qcs615-dp
+
+  "^dsi@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        items:
+          - const: qcom,qcs615-dsi-ctrl
+          - const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: qcom,qcs615-dsi-phy-14nm
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
+    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    display-subsystem@ae00000 {
+        compatible = "qcom,qcs615-mdss";
+        reg = <0x0ae00000 0x1000>;
+        reg-names = "mdss";
+
+	interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+			<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+			&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+	interconnect-names = "mdp0-mem", "cpu-cfg";
+
+        power-domains = <&dispcc MDSS_CORE_GDSC>;
+
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&gcc GCC_DISP_HF_AXI_CLK>,
+                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        iommus = <&apps_smmu 0x800 0x0>;
+
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        display-controller@ae01000 {
+            compatible = "qcom,qcs615-dpu";
+            reg = <0x0ae01000 0x8f000>,
+                  <0x0aeb0000 0x2008>;
+            reg-names = "mdp", "vbif";
+
+            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                     <&gcc GCC_DISP_HF_AXI_CLK>,
+		     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+            clock-names = "iface", "bus", "lut", "core", "vsync";
+
+            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+            assigned-clock-rates = <19200000>;
+
+            operating-points-v2 = <&mdp_opp_table>;
+
+            interrupt-parent = <&mdss>;
+            interrupts = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+	            dpu_intf0_out: endpoint {
+		    };
+	        };
+
+                port@1 {
+		    reg = <1>;
+		    dpu_intf1_out: endpoint {
+		        remote-endpoint = <&mdss_dsi0_in>;
+		    };
+	        };
+
+            };
+
+            mdp_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-375000000 {
+                    opp-hz = /bits/ 64 <375000000>;
+                    required-opps = <&rpmhpd_opp_svs_l1>;
+                };
+
+                opp-500000000 {
+                    opp-hz = /bits/ 64 <500000000>;
+                    required-opps = <&rpmhpd_opp_nom>;
+                };
+
+                opp-575000000 {
+                    opp-hz = /bits/ 64 <575000000>;
+                    required-opps = <&rpmhpd_opp_turbo>;
+                };
+
+                opp-650000000 {
+                    opp-hz = /bits/ 64 <650000000>;
+                    required-opps = <&rpmhpd_opp_turbo_l1>;
+                };
+            };
+        };
+
+        dsi@ae94000 {
+            compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+            reg = <0x0ae94000 0x400>;
+            reg-names = "dsi_ctrl";
+
+            interrupt-parent = <&mdss>;
+            interrupts = <4>;
+
+            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                     <&gcc GCC_DISP_HF_AXI_CLK>;
+            clock-names = "byte",
+                          "byte_intf",
+                          "pixel",
+                          "core",
+                          "iface",
+                          "bus";
+
+            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+            operating-points-v2 = <&dsi0_opp_table>;
+
+            phys = <&mdss_dsi0_phy>;
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    mdss_dsi0_in: endpoint {
+                        remote-endpoint = <&dpu_intf1_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    mdss_dsi0_out: endpoint {
+                    };
+                };
+            };
+
+            dsi0_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-164000000 {
+                    opp-hz = /bits/ 64 <164000000>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-187500000 {
+                    opp-hz = /bits/ 64 <187500000>;
+                    required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-225000000 {
+                    opp-hz = /bits/ 64 <225000000>;
+                    required-opps = <&rpmhpd_opp_svs_l1>;
+                };
+
+                opp-262500000 {
+                    opp-hz = /bits/ 64 <262500000>;
+                    required-opps = <&rpmhpd_opp_nom>;
+                };
+            };
+        };
+
+        mdss_dsi0_phy: phy@ae94400 {
+            compatible = "qcom,qcs615-dsi-phy-14nm";
+            reg = <0x0ae94400 0x100>,
+                  <0x0ae94500 0x300>,
+                  <0x0ae94800 0x188>;
+            reg-names = "dsi_phy",
+                        "dsi_phy_lane",
+                        "dsi_pll";
+
+            #clock-cells = <1>;
+            #phy-cells = <0>;
+
+            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                     <&rpmhcc RPMH_CXO_CLK>;
+            clock-names = "iface", "ref";
+            vdds-supply = <&vreg_dsi_phy>;
+        };
+    };
+...

-- 
2.25.1

Re: [PATCH 5/6] dt-bindings: display/msm: Add QCS615 MDSS & DPU

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:31PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> Add bindings for the display hardware on QCS615.
> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
>  .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
>  2 files changed, 395 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..35339092cb4f905541a7f70f42166bd0b0b7dee7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
> @@ -0,0 +1,117 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QCS615 Display DPU
> +
> +maintainers:
> +  - lliu6 <quic_lliu6@quicinc.com>

No, you are not. Please at least list Abhinav and me.

> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,qcs615-dpu
> +
> +  reg:
> +    items:
> +      - description: Address offset and size for mdp register set
> +      - description: Address offset and size for vbif register set
> +
> +  reg-names:
> +    items:
> +      - const: mdp
> +      - const: vbif
> +
> +  clocks:
> +    items:
> +      - description: Display ahb clock
> +      - description: Display hf axi clock
> +      - description: Display core clock
> +      - description: Display vsync clock
> +
> +  clock-names:
> +    items:
> +      - const: iface
> +      - const: bus
> +      - const: core
> +      - const: vsync
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,qcs615-dispcc.h>

I can not pick this up, these headers are not present in the msm-next
tree. Please use ephemeral nodes instead.

> +    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
> +    #include <dt-bindings/interconnect/qcom,icc.h>
> +    #include <dt-bindings/power/qcom-rpmpd.h>
> +
> +    display-controller@ae01000 {
> +        compatible = "qcom,qcs615-dpu";
> +        reg = <0x0ae01000 0x8f000>,
> +              <0x0aeb0000 0x2008>;
> +        reg-names = "mdp", "vbif";
> +
> +        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                 <&gcc GCC_DISP_HF_AXI_CLK>,
> +                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> +                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
> +                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +        clock-names = "iface", "bus", "lut" "core", "vsync";
> +
> +        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +        assigned-clock-rates = <19200000>;
> +
> +        operating-points-v2 = <&mdp_opp_table>;
> +
> +        interrupt-parent = <&mdss>;
> +        interrupts = <0>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +	        dpu_intf0_out: endpoint {
> +		};
> +	    };

Indentation is definitely wrong.

> +
> +            port@1 {
> +		reg = <1>;
> +		dpu_intf1_out: endpoint {
> +		    remote-endpoint = <&mdss_dsi0_in>;
> +		};
> +	    };
> +
> +        };
> +
> +        mdp_opp_table: opp-table {
> +            compatible = "operating-points-v2";
> +
> +            opp-375000000 {
> +                opp-hz = /bits/ 64 <375000000>;
> +                required-opps = <&rpmhpd_opp_svs_l1>;
> +            };
> +
> +            opp-500000000 {
> +                opp-hz = /bits/ 64 <500000000>;
> +                required-opps = <&rpmhpd_opp_nom>;
> +            };
> +
> +            opp-575000000 {
> +                opp-hz = /bits/ 64 <575000000>;
> +                required-opps = <&rpmhpd_opp_turbo>;
> +            };
> +
> +            opp-650000000 {
> +                opp-hz = /bits/ 64 <650000000>;
> +                required-opps = <&rpmhpd_opp_turbo_l1>;
> +            };
> +        };
> +    };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..fdad15c358892306dcb2c1b78319934c504cfc2b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
> @@ -0,0 +1,278 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QCS615 Display MDSS
> +
> +maintainers:
> +  - lliu6 <quic_lliu6@quicinc.com>
> +
> +description:
> +  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
> +  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> +  bindings of MDSS are mentioned for QCS615 target.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: qcom,qcs615-mdss
> +
> +  clocks:
> +    items:
> +      - description: Display AHB clock from gcc
> +      - description: Display hf axi clock
> +      - description: Display sf axi clock
> +      - description: Display core clock
> +
> +  clock-names:
> +    items:
> +      - const: iface
> +      - const: bus
> +      - const: nrt_bus
> +      - const: core
> +
> +  iommus:
> +    maxItems: 1
> +
> +  interconnects:
> +    maxItems: 2
> +
> +  interconnect-names:
> +    maxItems: 2
> +
> +patternProperties:
> +  "^display-controller@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +
> +    properties:
> +      compatible:
> +        const: qcom,qcs615-dpu
> +
> +  "^displayport-controller@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +
> +    properties:
> +      compatible:
> +        contains:
> +          const: qcom,qcs615-dp

It is not described anywhere, isn't it?

> +
> +  "^dsi@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +

No empty line

> +    properties:
> +      compatible:
> +        items:
> +          - const: qcom,qcs615-dsi-ctrl
> +          - const: qcom,mdss-dsi-ctrl
> +
> +  "^phy@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +

No empty line

> +    properties:
> +      compatible:
> +        const: qcom,qcs615-dsi-phy-14nm
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
> +    #include <dt-bindings/clock/qcom,qcs615-gcc.h>

Same comment, use ephemeral nodes instead of listing the clocks exactly.

> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
> +    #include <dt-bindings/interconnect/qcom,icc.h>
> +    #include <dt-bindings/power/qcom-rpmpd.h>
> +
> +    display-subsystem@ae00000 {
> +        compatible = "qcom,qcs615-mdss";
> +        reg = <0x0ae00000 0x1000>;
> +        reg-names = "mdss";
> +
> +	interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> +			<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +			&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> +	interconnect-names = "mdp0-mem", "cpu-cfg";

Wrong indentation. No tabs in yaml files. Did it even compile?

> +
> +        power-domains = <&dispcc MDSS_CORE_GDSC>;
> +
> +        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                 <&gcc GCC_DISP_HF_AXI_CLK>,
> +                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +
> +        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-controller;
> +        #interrupt-cells = <1>;
> +
> +        iommus = <&apps_smmu 0x800 0x0>;
> +
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        ranges;
> +
> +        display-controller@ae01000 {
> +            compatible = "qcom,qcs615-dpu";
> +            reg = <0x0ae01000 0x8f000>,
> +                  <0x0aeb0000 0x2008>;
> +            reg-names = "mdp", "vbif";
> +
> +            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                     <&gcc GCC_DISP_HF_AXI_CLK>,
> +		     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> +                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
> +                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +            clock-names = "iface", "bus", "lut", "core", "vsync";
> +
> +            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +            assigned-clock-rates = <19200000>;
> +
> +            operating-points-v2 = <&mdp_opp_table>;
> +
> +            interrupt-parent = <&mdss>;
> +            interrupts = <0>;
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port@0 {
> +                    reg = <0>;
> +	            dpu_intf0_out: endpoint {
> +		    };
> +	        };
> +
> +                port@1 {
> +		    reg = <1>;
> +		    dpu_intf1_out: endpoint {
> +		        remote-endpoint = <&mdss_dsi0_in>;
> +		    };
> +	        };
> +
> +            };
> +
> +            mdp_opp_table: opp-table {
> +                compatible = "operating-points-v2";
> +
> +                opp-375000000 {
> +                    opp-hz = /bits/ 64 <375000000>;
> +                    required-opps = <&rpmhpd_opp_svs_l1>;
> +                };
> +
> +                opp-500000000 {
> +                    opp-hz = /bits/ 64 <500000000>;
> +                    required-opps = <&rpmhpd_opp_nom>;
> +                };
> +
> +                opp-575000000 {
> +                    opp-hz = /bits/ 64 <575000000>;
> +                    required-opps = <&rpmhpd_opp_turbo>;
> +                };
> +
> +                opp-650000000 {
> +                    opp-hz = /bits/ 64 <650000000>;
> +                    required-opps = <&rpmhpd_opp_turbo_l1>;
> +                };
> +            };
> +        };
> +
> +        dsi@ae94000 {
> +            compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> +            reg = <0x0ae94000 0x400>;
> +            reg-names = "dsi_ctrl";
> +
> +            interrupt-parent = <&mdss>;
> +            interrupts = <4>;
> +
> +            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> +                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> +                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> +                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                     <&gcc GCC_DISP_HF_AXI_CLK>;
> +            clock-names = "byte",
> +                          "byte_intf",
> +                          "pixel",
> +                          "core",
> +                          "iface",
> +                          "bus";
> +
> +            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> +                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> +            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> +
> +            operating-points-v2 = <&dsi0_opp_table>;
> +
> +            phys = <&mdss_dsi0_phy>;
> +
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port@0 {
> +                    reg = <0>;
> +                    mdss_dsi0_in: endpoint {
> +                        remote-endpoint = <&dpu_intf1_out>;
> +                    };
> +                };
> +
> +                port@1 {
> +                    reg = <1>;
> +                    mdss_dsi0_out: endpoint {
> +                    };
> +                };
> +            };
> +
> +            dsi0_opp_table: opp-table {
> +                compatible = "operating-points-v2";
> +
> +                opp-164000000 {
> +                    opp-hz = /bits/ 64 <164000000>;
> +                    required-opps = <&rpmhpd_opp_low_svs>;
> +                };
> +
> +                opp-187500000 {
> +                    opp-hz = /bits/ 64 <187500000>;
> +                    required-opps = <&rpmhpd_opp_svs>;
> +                };
> +
> +                opp-225000000 {
> +                    opp-hz = /bits/ 64 <225000000>;
> +                    required-opps = <&rpmhpd_opp_svs_l1>;
> +                };
> +
> +                opp-262500000 {
> +                    opp-hz = /bits/ 64 <262500000>;
> +                    required-opps = <&rpmhpd_opp_nom>;
> +                };
> +            };
> +        };
> +
> +        mdss_dsi0_phy: phy@ae94400 {
> +            compatible = "qcom,qcs615-dsi-phy-14nm";
> +            reg = <0x0ae94400 0x100>,
> +                  <0x0ae94500 0x300>,
> +                  <0x0ae94800 0x188>;
> +            reg-names = "dsi_phy",
> +                        "dsi_phy_lane",
> +                        "dsi_pll";
> +
> +            #clock-cells = <1>;
> +            #phy-cells = <0>;
> +
> +            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                     <&rpmhcc RPMH_CXO_CLK>;
> +            clock-names = "iface", "ref";
> +            vdds-supply = <&vreg_dsi_phy>;
> +        };
> +    };
> +...
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 5/6] dt-bindings: display/msm: Add QCS615 MDSS & DPU

[fange zhang]

On 2024/10/14 18:35, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:31PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
>>
>> Add bindings for the display hardware on QCS615.
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>>   .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
>>   .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
>>   2 files changed, 395 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..35339092cb4f905541a7f70f42166bd0b0b7dee7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml
>> @@ -0,0 +1,117 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-dpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QCS615 Display DPU
>> +
>> +maintainers:
>> +  - lliu6 <quic_lliu6@quicinc.com>
> 
> No, you are not. Please at least list Abhinav and me.
fixed in v2, change to
   - Abhinav Kumar <quic_abhinavk@quicinc.com>
   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

will replace qcs615 to sm6150 for whole patch
> 
>> +
>> +$ref: /schemas/display/msm/dpu-common.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,qcs615-dpu
>> +
>> +  reg:
>> +    items:
>> +      - description: Address offset and size for mdp register set
>> +      - description: Address offset and size for vbif register set
>> +
>> +  reg-names:
>> +    items:
>> +      - const: mdp
>> +      - const: vbif
>> +
>> +  clocks:
>> +    items:
>> +      - description: Display ahb clock
>> +      - description: Display hf axi clock
>> +      - description: Display core clock
>> +      - description: Display vsync clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: iface
>> +      - const: bus
>> +      - const: core
>> +      - const: vsync
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
> 
> I can not pick this up, these headers are not present in the msm-next
> tree. Please use ephemeral nodes instead.
will remove
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
and use ephemeral nodes instead
> 
>> +    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>> +    #include <dt-bindings/interconnect/qcom,icc.h>
>> +    #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> +    display-controller@ae01000 {
>> +        compatible = "qcom,qcs615-dpu";
>> +        reg = <0x0ae01000 0x8f000>,
>> +              <0x0aeb0000 0x2008>;
>> +        reg-names = "mdp", "vbif";
>> +
>> +        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +                 <&gcc GCC_DISP_HF_AXI_CLK>,
>> +                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> +                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> +                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> +        clock-names = "iface", "bus", "lut" "core", "vsync";
>> +
>> +        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> +        assigned-clock-rates = <19200000>;
>> +
>> +        operating-points-v2 = <&mdp_opp_table>;
>> +
>> +        interrupt-parent = <&mdss>;
>> +        interrupts = <0>;
>> +
>> +        ports {
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +
>> +            port@0 {
>> +                reg = <0>;
>> +	        dpu_intf0_out: endpoint {
>> +		};
>> +	    };
> 
> Indentation is definitely wrong.
fixed in v2
> 
>> +
>> +            port@1 {
>> +		reg = <1>;
>> +		dpu_intf1_out: endpoint {
>> +		    remote-endpoint = <&mdss_dsi0_in>;
>> +		};
>> +	    };
>> +
>> +        };
>> +
>> +        mdp_opp_table: opp-table {
>> +            compatible = "operating-points-v2";
>> +
>> +            opp-375000000 {
>> +                opp-hz = /bits/ 64 <375000000>;
>> +                required-opps = <&rpmhpd_opp_svs_l1>;
>> +            };
>> +
>> +            opp-500000000 {
>> +                opp-hz = /bits/ 64 <500000000>;
>> +                required-opps = <&rpmhpd_opp_nom>;
>> +            };
>> +
>> +            opp-575000000 {
>> +                opp-hz = /bits/ 64 <575000000>;
>> +                required-opps = <&rpmhpd_opp_turbo>;
>> +            };
>> +
>> +            opp-650000000 {
>> +                opp-hz = /bits/ 64 <650000000>;
>> +                required-opps = <&rpmhpd_opp_turbo_l1>;
>> +            };
>> +        };
>> +    };
>> +...
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..fdad15c358892306dcb2c1b78319934c504cfc2b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml
>> @@ -0,0 +1,278 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-mdss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QCS615 Display MDSS
>> +
>> +maintainers:
>> +  - lliu6 <quic_lliu6@quicinc.com>
>> +
>> +description:
>> +  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
>> +  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
>> +  bindings of MDSS are mentioned for QCS615 target.
>> +
>> +$ref: /schemas/display/msm/mdss-common.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: qcom,qcs615-mdss
>> +
>> +  clocks:
>> +    items:
>> +      - description: Display AHB clock from gcc
>> +      - description: Display hf axi clock
>> +      - description: Display sf axi clock
>> +      - description: Display core clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: iface
>> +      - const: bus
>> +      - const: nrt_bus
>> +      - const: core
>> +
>> +  iommus:
>> +    maxItems: 1
>> +
>> +  interconnects:
>> +    maxItems: 2
>> +
>> +  interconnect-names:
>> +    maxItems: 2
>> +
>> +patternProperties:
>> +  "^display-controller@[0-9a-f]+$":
>> +    type: object
>> +    additionalProperties: true
>> +
>> +    properties:
>> +      compatible:
>> +        const: qcom,qcs615-dpu
>> +
>> +  "^displayport-controller@[0-9a-f]+$":
>> +    type: object
>> +    additionalProperties: true
>> +
>> +    properties:
>> +      compatible:
>> +        contains:
>> +          const: qcom,qcs615-dp
> 
> It is not described anywhere, isn't it?
will remove this prop

> 
>> +
>> +  "^dsi@[0-9a-f]+$":
>> +    type: object
>> +    additionalProperties: true
>> +
> 
> No empty line
fixed in v2
> 
>> +    properties:
>> +      compatible:
>> +        items:
>> +          - const: qcom,qcs615-dsi-ctrl
>> +          - const: qcom,mdss-dsi-ctrl
>> +
>> +  "^phy@[0-9a-f]+$":
>> +    type: object
>> +    additionalProperties: true
>> +
> 
> No empty line
fixed in v2
> 
>> +    properties:
>> +      compatible:
>> +        const: qcom,qcs615-dsi-phy-14nm
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
>> +    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> 
> Same comment, use ephemeral nodes instead of listing the clocks exactly.
will remove
#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
and use ephemeral nodes instead
> 
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>> +    #include <dt-bindings/interconnect/qcom,icc.h>
>> +    #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> +    display-subsystem@ae00000 {
>> +        compatible = "qcom,qcs615-mdss";
>> +        reg = <0x0ae00000 0x1000>;
>> +        reg-names = "mdss";
>> +
>> +	interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
>> +			<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> +			&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> +	interconnect-names = "mdp0-mem", "cpu-cfg";
> 
> Wrong indentation. No tabs in yaml files. Did it even compile?
will fix them in next version
> 
>> +
>> +        power-domains = <&dispcc MDSS_CORE_GDSC>;
>> +
>> +        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +                 <&gcc GCC_DISP_HF_AXI_CLK>,
>> +                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> +
>> +        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-controller;
>> +        #interrupt-cells = <1>;
>> +
>> +        iommus = <&apps_smmu 0x800 0x0>;
>> +
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        ranges;
>> +
>> +        display-controller@ae01000 {
>> +            compatible = "qcom,qcs615-dpu";
>> +            reg = <0x0ae01000 0x8f000>,
>> +                  <0x0aeb0000 0x2008>;
>> +            reg-names = "mdp", "vbif";
>> +
>> +            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +                     <&gcc GCC_DISP_HF_AXI_CLK>,
>> +		     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> +            clock-names = "iface", "bus", "lut", "core", "vsync";
>> +
>> +            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> +            assigned-clock-rates = <19200000>;
>> +
>> +            operating-points-v2 = <&mdp_opp_table>;
>> +
>> +            interrupt-parent = <&mdss>;
>> +            interrupts = <0>;
>> +
>> +            ports {
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +
>> +                port@0 {
>> +                    reg = <0>;
>> +	            dpu_intf0_out: endpoint {
>> +		    };
>> +	        };
>> +
>> +                port@1 {
>> +		    reg = <1>;
>> +		    dpu_intf1_out: endpoint {
>> +		        remote-endpoint = <&mdss_dsi0_in>;
>> +		    };
>> +	        };
>> +
>> +            };
>> +
>> +            mdp_opp_table: opp-table {
>> +                compatible = "operating-points-v2";
>> +
>> +                opp-375000000 {
>> +                    opp-hz = /bits/ 64 <375000000>;
>> +                    required-opps = <&rpmhpd_opp_svs_l1>;
>> +                };
>> +
>> +                opp-500000000 {
>> +                    opp-hz = /bits/ 64 <500000000>;
>> +                    required-opps = <&rpmhpd_opp_nom>;
>> +                };
>> +
>> +                opp-575000000 {
>> +                    opp-hz = /bits/ 64 <575000000>;
>> +                    required-opps = <&rpmhpd_opp_turbo>;
>> +                };
>> +
>> +                opp-650000000 {
>> +                    opp-hz = /bits/ 64 <650000000>;
>> +                    required-opps = <&rpmhpd_opp_turbo_l1>;
>> +                };
>> +            };
>> +        };
>> +
>> +        dsi@ae94000 {
>> +            compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl";
>> +            reg = <0x0ae94000 0x400>;
>> +            reg-names = "dsi_ctrl";
>> +
>> +            interrupt-parent = <&mdss>;
>> +            interrupts = <4>;
>> +
>> +            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +                     <&gcc GCC_DISP_HF_AXI_CLK>;
>> +            clock-names = "byte",
>> +                          "byte_intf",
>> +                          "pixel",
>> +                          "core",
>> +                          "iface",
>> +                          "bus";
>> +
>> +            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> +                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
>> +            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
>> +
>> +            operating-points-v2 = <&dsi0_opp_table>;
>> +
>> +            phys = <&mdss_dsi0_phy>;
>> +
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +
>> +            ports {
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +
>> +                port@0 {
>> +                    reg = <0>;
>> +                    mdss_dsi0_in: endpoint {
>> +                        remote-endpoint = <&dpu_intf1_out>;
>> +                    };
>> +                };
>> +
>> +                port@1 {
>> +                    reg = <1>;
>> +                    mdss_dsi0_out: endpoint {
>> +                    };
>> +                };
>> +            };
>> +
>> +            dsi0_opp_table: opp-table {
>> +                compatible = "operating-points-v2";
>> +
>> +                opp-164000000 {
>> +                    opp-hz = /bits/ 64 <164000000>;
>> +                    required-opps = <&rpmhpd_opp_low_svs>;
>> +                };
>> +
>> +                opp-187500000 {
>> +                    opp-hz = /bits/ 64 <187500000>;
>> +                    required-opps = <&rpmhpd_opp_svs>;
>> +                };
>> +
>> +                opp-225000000 {
>> +                    opp-hz = /bits/ 64 <225000000>;
>> +                    required-opps = <&rpmhpd_opp_svs_l1>;
>> +                };
>> +
>> +                opp-262500000 {
>> +                    opp-hz = /bits/ 64 <262500000>;
>> +                    required-opps = <&rpmhpd_opp_nom>;
>> +                };
>> +            };
>> +        };
>> +
>> +        mdss_dsi0_phy: phy@ae94400 {
>> +            compatible = "qcom,qcs615-dsi-phy-14nm";
>> +            reg = <0x0ae94400 0x100>,
>> +                  <0x0ae94500 0x300>,
>> +                  <0x0ae94800 0x188>;
>> +            reg-names = "dsi_phy",
>> +                        "dsi_phy_lane",
>> +                        "dsi_pll";
>> +
>> +            #clock-cells = <1>;
>> +            #phy-cells = <0>;
>> +
>> +            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +                     <&rpmhcc RPMH_CXO_CLK>;
>> +            clock-names = "iface", "ref";
>> +            vdds-supply = <&vreg_dsi_phy>;
>> +        };
>> +    };
>> +...
>>
>> -- 
>> 2.25.1
>>
>>
> 

Re: [PATCH 5/6] dt-bindings: display/msm: Add QCS615 MDSS & DPU

[Krzysztof Kozlowski]

On 14/10/2024 11:47, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> Add bindings for the display hardware on QCS615.
> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>

I have no clue what this patchset is supposed to be. It seems you sent
something internally. At least it would explain some issues here.

Please drop public mailing lists when sending internal stuff.

Best regards,
Krzysztof

[PATCH 6/6] dt-bindings: display/msm: dsi-controller-main: Document QCS615

[fangez via B4 Relay]

From: lliu6 <quic_lliu6@quicinc.com>

Document general compatibility of the DSI controller on QCS615.

Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
---
 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..4142c753d1c4c4797e3a3f5317c02f8c863cdd12 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -39,6 +39,7 @@ properties:
               - qcom,sm8450-dsi-ctrl
               - qcom,sm8550-dsi-ctrl
               - qcom,sm8650-dsi-ctrl
+              - qcom,qcs615-dsi-ctrl
           - const: qcom,mdss-dsi-ctrl
       - enum:
           - qcom,dsi-ctrl-6g-qcm2290

-- 
2.25.1

Re: [PATCH 6/6] dt-bindings: display/msm: dsi-controller-main: Document QCS615

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:32PM +0800, fangez via B4 Relay wrote:
> From: lliu6 <quic_lliu6@quicinc.com>
> 
> Document general compatibility of the DSI controller on QCS615.
> 
> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
> ---
>  Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..4142c753d1c4c4797e3a3f5317c02f8c863cdd12 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> @@ -39,6 +39,7 @@ properties:
>                - qcom,sm8450-dsi-ctrl
>                - qcom,sm8550-dsi-ctrl
>                - qcom,sm8650-dsi-ctrl
> +              - qcom,qcs615-dsi-ctrl

Do you notice why the line you have added is not in the correct place?
Please look around next time before just adding a string.

>            - const: qcom,mdss-dsi-ctrl
>        - enum:
>            - qcom,dsi-ctrl-6g-qcm2290
> 
> -- 
> 2.25.1
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 6/6] dt-bindings: display/msm: dsi-controller-main: Document QCS615

[fange zhang]

On 2024/10/14 18:39, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:32PM +0800, fangez via B4 Relay wrote:
>> From: lliu6 <quic_lliu6@quicinc.com>
>>
>> Document general compatibility of the DSI controller on QCS615.
>>
>> Signed-off-by: lliu6 <quic_lliu6@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
>> index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..4142c753d1c4c4797e3a3f5317c02f8c863cdd12 100644
>> --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
>> @@ -39,6 +39,7 @@ properties:
>>                 - qcom,sm8450-dsi-ctrl
>>                 - qcom,sm8550-dsi-ctrl
>>                 - qcom,sm8650-dsi-ctrl
>> +              - qcom,qcs615-dsi-ctrl
> 
> Do you notice why the line you have added is not in the correct place?
> Please look around next time before just adding a string.
Sorry about that, will implement these actions in the next version
- change qcom,qcs615-dsi-ctrl to qcom,sm6150-dsi-ctrl
- move qcom,sm6150-dsi-ctrl behind qcom,sm6125-dsi-ctrl
> 
>>             - const: qcom,mdss-dsi-ctrl
>>         - enum:
>>             - qcom,dsi-ctrl-6g-qcm2290
>>
>> -- 
>> 2.25.1
>>
>>
> 

Re: [PATCH 0/6] add_display_support_for_QCS615

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 05:47:26PM +0800, fangez via B4 Relay wrote:
> Signed-off-by: fangez <quic_fangez@quicinc.com>

You didn't copy any of corresponding maintainers or mailing lists, so
most likely your patches will be ignored. Please use b4 tool for
preparing and sending patches.

> ---
> lliu6 (6):
>       arm64: defconfig: Enable SX150X
>       arm64: dts: qcom: qcs615: Add display mdss and dsi configuration
>       drm/msm/dpu: Add QCS615 support
>       dt-bindings: display/msm: Add QCS615 DSI phy
>       dt-bindings: display/msm: Add QCS615 MDSS & DPU
>       dt-bindings: display/msm: dsi-controller-main: Document QCS615
> 
>  .../bindings/display/msm/dsi-controller-main.yaml  |   1 +
>  .../bindings/display/msm/dsi-phy-14nm.yaml         |   1 +
>  .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
>  .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/qcs615-ride.dts           | 101 ++++++++
>  arch/arm64/boot/dts/qcom/qcs615.dtsi               | 195 +++++++++++++++
>  arch/arm64/configs/defconfig                       |   1 +
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
>  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
>  drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
>  17 files changed, 1014 insertions(+)
> ---
> base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a
> change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e
> 
> Best regards,
> -- 
> fangez <quic_fangez@quicinc.com>
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 0/6] add_display_support_for_QCS615

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 01:36:52PM +0300, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 05:47:26PM +0800, fangez via B4 Relay wrote:
> > Signed-off-by: fangez <quic_fangez@quicinc.com>
> 
> You didn't copy any of corresponding maintainers or mailing lists, so
> most likely your patches will be ignored. Please use b4 tool for
> preparing and sending patches.
> 

Ok, you are using b4, excuse me. Then it makes me wonder, how and why
you ignored all B4 recommendations and pleads to get required To/Cc
lists.

> > ---
> > lliu6 (6):
> >       arm64: defconfig: Enable SX150X
> >       arm64: dts: qcom: qcs615: Add display mdss and dsi configuration
> >       drm/msm/dpu: Add QCS615 support
> >       dt-bindings: display/msm: Add QCS615 DSI phy
> >       dt-bindings: display/msm: Add QCS615 MDSS & DPU
> >       dt-bindings: display/msm: dsi-controller-main: Document QCS615
> > 
> >  .../bindings/display/msm/dsi-controller-main.yaml  |   1 +
> >  .../bindings/display/msm/dsi-phy-14nm.yaml         |   1 +
> >  .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
> >  .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
> >  arch/arm64/boot/dts/qcom/qcs615-ride.dts           | 101 ++++++++
> >  arch/arm64/boot/dts/qcom/qcs615.dtsi               | 195 +++++++++++++++
> >  arch/arm64/configs/defconfig                       |   1 +
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
> >  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
> >  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
> >  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
> >  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
> >  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
> >  drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
> >  17 files changed, 1014 insertions(+)
> > ---
> > base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a
> > change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e
> > 
> > Best regards,
> > -- 
> > fangez <quic_fangez@quicinc.com>
> > 
> > 
> 
> -- 
> With best wishes
> Dmitry

-- 
With best wishes
Dmitry

Re: [PATCH 0/6] add_display_support_for_QCS615

[Dmitry Baryshkov]

On Mon, 14 Oct 2024 at 14:50, fange zhang (QUIC)
<quic_fangez@quicinc.com> wrote:
>
> Dear maintainers,
>
> Sorry, Please ignore this email thread. We will review it again and initiate a new one after internal review.

Dear fange. Please don't top-post and don't send HDMI emails. Looking
forward to reviewing v2 of these patches.

>
> Thanks for your comments.
>
> Best regards,
> fange
>
> ________________________________
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Monday, October 14, 2024 18:48
> To: fange zhang (QUIC) <quic_fangez@quicinc.com>
> Cc: kernel <kernel@quicinc.com>; Li Liu (QUIC) <quic_lliu6@quicinc.com>; Xiangxu Yin (QUIC) <quic_xiangxuy@quicinc.com>; linux-arm-msm@vger.kernel.org <linux-arm-msm@vger.kernel.org>
> Subject: Re: [PATCH 0/6] add_display_support_for_QCS615
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.
>
> On Mon, Oct 14, 2024 at 01:36:52PM +0300, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 05:47:26PM +0800, fangez via B4 Relay wrote:
> > > Signed-off-by: fangez <quic_fangez@quicinc.com>
> >
> > You didn't copy any of corresponding maintainers or mailing lists, so
> > most likely your patches will be ignored. Please use b4 tool for
> > preparing and sending patches.
> >
>
> Ok, you are using b4, excuse me. Then it makes me wonder, how and why
> you ignored all B4 recommendations and pleads to get required To/Cc
> lists.
>
> > > ---
> > > lliu6 (6):
> > >       arm64: defconfig: Enable SX150X
> > >       arm64: dts: qcom: qcs615: Add display mdss and dsi configuration
> > >       drm/msm/dpu: Add QCS615 support
> > >       dt-bindings: display/msm: Add QCS615 DSI phy
> > >       dt-bindings: display/msm: Add QCS615 MDSS & DPU
> > >       dt-bindings: display/msm: dsi-controller-main: Document QCS615
> > >
> > >  .../bindings/display/msm/dsi-controller-main.yaml  |   1 +
> > >  .../bindings/display/msm/dsi-phy-14nm.yaml         |   1 +
> > >  .../bindings/display/msm/qcom,qcs615-dpu.yaml      | 117 +++++++++
> > >  .../bindings/display/msm/qcom,qcs615-mdss.yaml     | 278 +++++++++++++++++++++
> > >  arch/arm64/boot/dts/qcom/qcs615-ride.dts           | 101 ++++++++
> > >  arch/arm64/boot/dts/qcom/qcs615.dtsi               | 195 +++++++++++++++
> > >  arch/arm64/configs/defconfig                       |   1 +
> > >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
> > >  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 ++
> > >  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
> > >  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
> > >  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
> > >  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c         |  21 ++
> > >  drivers/gpu/drm/msm/msm_mdss.c                     |   7 +
> > >  17 files changed, 1014 insertions(+)
> > > ---
> > > base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a
> > > change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e
> > >
> > > Best regards,
> > > --
> > > fangez <quic_fangez@quicinc.com>
> > >
> > >
> >
> > --
> > With best wishes
> > Dmitry
>
> --
> With best wishes
> Dmitry



-- 
With best wishes
Dmitry