[PATCH v7 0/6] qcom: Add support for IQ-9075-evk board

[PATCH v7 0/6] qcom: Add support for IQ-9075-evk board

[Wasim Nazir]

This series:

Add support for Qualcomm's iq9-evk board using QCS9075 SOC.

QCS9075 is compatible IoT-industrial grade variant of SA8775p SOC.
Unlike QCS9100, it doesn't have safety monitoring feature of
Safety-Island(SAIL) subsystem, which affects thermal management.

In QCS9100 SOC, the safety subsystem monitors all thermal sensors and
does corrective action for each subsystem based on sensor violation
to comply safety standards. But as QCS9075 is non-safe SOC it requires
conventional thermal mitigation for thermal management.
In this series thermal mitigation changes are not included as it needs
more discussion whether to include the change in DT or in drivers.

Below are detailed informations on IQ-9075-evk HW:
------------------------------------------------------
QCS9075 SOM is stacked on top of IQ-9075-evk board.
On top of IQ-9075-evk board additional mezzanine boards can be stacked
in future.
IQ-9075-evk is single board supporting these peripherals:
  - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
    eMMC on mezzanine card
  - Audio/Video, Camera & Display ports
  - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD
  - Sensors: IMU
  - PCIe ports
  - USB & UART ports

Currently basic features are enabled to support 'boot to shell'.

---
Changelog:

v7:
  - Add UFS support along with l4c regulator from [1]
  - Remove "qcom,qcs9075-som" compatible and keep only SOM dtsi file
  - Increase camera pil size
  - Update commit text as per new changes
  - v6-link: [2]

[1] https://lore.kernel.org/all/20250513084309.10275-1-quic_sayalil@quicinc.com/
[2] https://lore.kernel.org/all/20250429054906.113317-1-quic_wasimn@quicinc.com/

Pratyush Brahma (1):
  arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

Rakesh Kota (1):
  arm64: dts: qcom: Add support L4C LDO for qcs9075 IQ-9075-EVK

Sayali Lokhande (1):
  arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

Wasim Nazir (3):
  dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board
  arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM
  arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

 .../devicetree/bindings/arm/qcom.yaml         |   7 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 +++++++
 .../boot/dts/qcom/qcs9075-iq-9075-evk.dts     | 295 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi     |  10 +
 5 files changed, 426 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi


base-commit: 8566fc3b96539e3235909d6bdda198e1282beaed
--
2.49.0

[PATCH v7 1/6] dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board

[Wasim Nazir]

QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC.
Unlike QCS9100, it doesn't have safety monitoring feature of
Safety-Island(SAIL) subsystem, which affects thermal management.

qcs9075-iq-9075-evk board is based on QCS9075 SOC.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 56f78f0f3803..3b2c60af12cd 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -58,6 +58,7 @@ description: |
         qcs8550
         qcm2290
         qcm6490
+        qcs9075
         qcs9100
         qdu1000
         qrb2210
@@ -961,6 +962,12 @@ properties:
               - qcom,sa8775p-ride-r3
           - const: qcom,sa8775p

+      - items:
+          - enum:
+              - qcom,qcs9075-iq-9075-evk
+          - const: qcom,qcs9075
+          - const: qcom,sa8775p
+
       - items:
           - enum:
               - qcom,qcs9100-ride
--
2.49.0

Re: [PATCH v7 1/6] dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board

[Krzysztof Kozlowski]

On 21/05/2025 16:08, Wasim Nazir wrote:
> QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC.
> Unlike QCS9100, it doesn't have safety monitoring feature of
> Safety-Island(SAIL) subsystem, which affects thermal management.
> 
> qcs9075-iq-9075-evk board is based on QCS9075 SOC.
> 
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

This was already acked twice by two DT maintainers. Apparently we need
the third one.

Sorry folks, but I will wait for v20 and then review. Otherwise we are
just doing pointless job here.

Best regards,
Krzysztof

Re: [PATCH v7 1/6] dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board

[Wasim Nazir]

On Wed, May 21, 2025 at 04:20:53PM +0200, Krzysztof Kozlowski wrote:
> On 21/05/2025 16:08, Wasim Nazir wrote:
> > QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC.
> > Unlike QCS9100, it doesn't have safety monitoring feature of
> > Safety-Island(SAIL) subsystem, which affects thermal management.
> > 
> > qcs9075-iq-9075-evk board is based on QCS9075 SOC.
> > 
> > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > ---
> >  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> 
> This was already acked twice by two DT maintainers. Apparently we need
> the third one.

The previous acknowledgment has been removed due to changes in the code.
Since, here I have removed the som compatible so though of getting it
reviewed again. Som compatible is removed to make it align with other
sa8775p & its derivative targets which we are trying to refactor along with
Ride changes in other series.

> 
> Sorry folks, but I will wait for v20 and then review. Otherwise we are
> just doing pointless job here.
> 
> Best regards,
> Krzysztof

Regards,
Wasim

Re: [PATCH v7 1/6] dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board

[Krzysztof Kozlowski]

On 21/05/2025 17:35, Wasim Nazir wrote:
> On Wed, May 21, 2025 at 04:20:53PM +0200, Krzysztof Kozlowski wrote:
>> On 21/05/2025 16:08, Wasim Nazir wrote:
>>> QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC.
>>> Unlike QCS9100, it doesn't have safety monitoring feature of
>>> Safety-Island(SAIL) subsystem, which affects thermal management.
>>>
>>> qcs9075-iq-9075-evk board is based on QCS9075 SOC.
>>>
>>> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>>>  1 file changed, 7 insertions(+)
>>>
>>
>> This was already acked twice by two DT maintainers. Apparently we need
>> the third one.
> 
> The previous acknowledgment has been removed due to changes in the code.
> Since, here I have removed the som compatible so though of getting it
> reviewed again. Som compatible is removed to make it align with other
> sa8775p & its derivative targets which we are trying to refactor along with
> Ride changes in other series.

Nothing was explained in cover letter and dropping tags needs explicit
mentioning. Nothing explained about first tag being dropped, either!
Read really carefully submitting patches and your internal guideline
before sending patches.

But that was not about it. It was about us spending 1 or 5 minutes on
your patch every time, because you send something not ready which your
company decides to change thus we need to spend time again, and then you
change it again, which we need to spend time again... do you get the point?

That is not fair. Your marketing changes should not cause more effort on
us. And this is not the first time.

At least I do not agree on that. Anyway, I explained my point of view to
Bjorn and Konrad. I am not going to review this. Maybe you will be lucky
with the third DT maintainer.

Best regards,
Krzysztof

Re: [PATCH v7 1/6] dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board

[Wasim Nazir]

On Wed, May 21, 2025 at 06:26:40PM +0200, Krzysztof Kozlowski wrote:
> On 21/05/2025 17:35, Wasim Nazir wrote:
> > On Wed, May 21, 2025 at 04:20:53PM +0200, Krzysztof Kozlowski wrote:
> >> On 21/05/2025 16:08, Wasim Nazir wrote:
> >>> QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC.
> >>> Unlike QCS9100, it doesn't have safety monitoring feature of
> >>> Safety-Island(SAIL) subsystem, which affects thermal management.
> >>>
> >>> qcs9075-iq-9075-evk board is based on QCS9075 SOC.
> >>>
> >>> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> >>> ---
> >>>  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
> >>>  1 file changed, 7 insertions(+)
> >>>
> >>
> >> This was already acked twice by two DT maintainers. Apparently we need
> >> the third one.
> > 
> > The previous acknowledgment has been removed due to changes in the code.
> > Since, here I have removed the som compatible so though of getting it
> > reviewed again. Som compatible is removed to make it align with other
> > sa8775p & its derivative targets which we are trying to refactor along with
> > Ride changes in other series.
> 
> Nothing was explained in cover letter and dropping tags needs explicit
> mentioning. Nothing explained about first tag being dropped, either!
> Read really carefully submitting patches and your internal guideline
> before sending patches.

I'm sorry about that; it wasn't intentional. I'll make sure to take care
of it next time. I do try to mention changes in the changelog, but I
understand now that it's not sufficient.

> 
> But that was not about it. It was about us spending 1 or 5 minutes on
> your patch every time, because you send something not ready which your
> company decides to change thus we need to spend time again, and then you
> change it again, which we need to spend time again... do you get the point?
> 

I have made the code changes to align with our discussion in the other
series [1] of changes for Ride. Let me know if we need further
discussion on this to conclude on DT structure for sa8775p & IQ9 targets.

[1]
https://lore.kernel.org/all/aCdAuTS4pg7arxwC@hu-wasimn-hyd.qualcomm.com/

> That is not fair. Your marketing changes should not cause more effort on
> us. And this is not the first time.

I truly appreciate all your efforts. I understand there have been
mistakes on our end, but we are learning a lot from this process. We are
noting valuable points to make our internal processes more efficient and
reduce multiple iterations.

> 
> At least I do not agree on that. Anyway, I explained my point of view to
> Bjorn and Konrad. I am not going to review this. Maybe you will be lucky
> with the third DT maintainer.
> 
> Best regards,
> Krzysztof

Regards,
Wasim

[PATCH v7 2/6] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

From: Pratyush Brahma <quic_pbrahma@quicinc.com>

SA8775P has a memory map which caters to the auto specific requirements.
QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
inherit the memory map of SA8775P require a slightly different memory
map as compared to SA8775P auto parts.
This new memory map is applicable for all the IoT boards which inherit
the initial SA8775P memory map. This is not applicable for non-IoT
boards.

Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
introduced as part of firmware updates for IoT. The size and base address
have been updated for video PIL carveout compared to SA8775P since it is
being brought up for the first time on IoT boards. The base addresses
of the rest of the PIL carveouts have been updated to accommodate the
change in size of video since PIL regions are relocatable and their
functionality is not impacted due to this change. The size of camera
pil has also been increased without breaking any feature.

The size of trusted apps carveout has also been reduced since it is
sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
carveout and its corresponding scm reference has been removed as these
are not required for IoT parts.

Incorporate these changes in the updated memory map.

Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi

diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
new file mode 100644
index 000000000000..ff2600eb5e3d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/delete-node/ &pil_camera_mem;
+/delete-node/ &pil_adsp_mem;
+/delete-node/ &pil_gdsp0_mem;
+/delete-node/ &pil_gdsp1_mem;
+/delete-node/ &pil_cdsp0_mem;
+/delete-node/ &pil_gpu_mem;
+/delete-node/ &pil_cdsp1_mem;
+/delete-node/ &pil_cvp_mem;
+/delete-node/ &pil_video_mem;
+/delete-node/ &audio_mdf_mem;
+/delete-node/ &trusted_apps_mem;
+/delete-node/ &hyptz_reserved_mem;
+/delete-node/ &tz_ffi_mem;
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gunyah_md_mem: gunyah-md@91a80000 {
+			reg = <0x0 0x91a80000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_camera_mem: pil-camera@95200000 {
+			reg = <0x0 0x95200000 0x0 0x700000>;
+			no-map;
+		};
+
+		pil_adsp_mem: pil-adsp@95900000 {
+			reg = <0x0 0x95900000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {
+			reg = <0x0 0x97700000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {
+			reg = <0x0 0x97780000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_gdsp0_mem: pil-gdsp0@97800000 {
+			reg = <0x0 0x97800000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gdsp1_mem: pil-gdsp1@99600000 {
+			reg = <0x0 0x99600000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {
+			reg = <0x0 0x9b400000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {
+			reg = <0x0 0x9b480000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_cdsp0_mem: pil-cdsp0@9b500000 {
+			reg = <0x0 0x9b500000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gpu_mem: pil-gpu@9d300000 {
+			reg = <0x0 0x9d300000 0x0 0x2000>;
+			no-map;
+		};
+
+		q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {
+			reg = <0x0 0x9d380000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_cdsp1_mem: pil-cdsp1@9d400000 {
+			reg = <0x0 0x9d400000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_cvp_mem: pil-cvp@9f200000 {
+			reg = <0x0 0x9f200000 0x0 0x700000>;
+			no-map;
+		};
+
+		pil_video_mem: pil-video@9f900000 {
+			reg = <0x0 0x9f900000 0x0 0x1000000>;
+			no-map;
+		};
+
+		trusted_apps_mem: trusted-apps@d1900000 {
+			reg = <0x0 0xd1900000 0x0 0x1c00000>;
+			no-map;
+		};
+	};
+
+	firmware {
+		scm {
+			/delete-property/ memory-region;
+		};
+	};
+};
--
2.49.0

[PATCH v7 3/6] arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM

[Wasim Nazir]

QCS9075 is an IoT variant of SA8775P SOC, most notably without
safety monitoring feature of Safety Island(SAIL) subsystem.
Add qcs9075-som.dtsi to specifies QCS9075 based SOM having SOC,
PMICs, Memory-map updates.
Use this SOM for qcs9075-iq-9075-evk board.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi

diff --git a/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
new file mode 100644
index 000000000000..552e40c95e06
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sa8775p.dtsi"
+#include "iq9-reserved-memory.dtsi"
+#include "sa8775p-pmics.dtsi"
--
2.49.0

[PATCH v7 4/6] arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

[Wasim Nazir]

Add initial device tree support for IQ-9075-EVK board,
based on Qualcomm's QCS9075 SOC.

Implement basic changes to enable boot to shell.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/qcs9075-iq-9075-evk.dts     | 268 ++++++++++++++++++
 2 files changed, 269 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 669b888b27a1..77501a13d91e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-industrial-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-vision-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs9075-iq-9075-evk.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
new file mode 100644
index 000000000000..dbc64496759d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "qcs9075-som.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IQ 9075 EVK";
+	compatible = "qcom,qcs9075-iq-9075-evk", "qcom,qcs9075", "qcom,sa8775p";
+
+	aliases {
+		serial0 = &uart10;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1816000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a: smps5 {
+			regulator-name = "vreg_s5a";
+			regulator-min-microvolt = <1850000>;
+			regulator-max-microvolt = <1996000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9a: smps9 {
+			regulator-name = "vreg_s9a";
+			regulator-min-microvolt = <535000>;
+			regulator-max-microvolt = <1120000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4a: ldo4 {
+			regulator-name = "vreg_l4a";
+			regulator-min-microvolt = <788000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a: ldo6 {
+			regulator-name = "vreg_l6a";
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <970000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <720000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9a: ldo9 {
+			regulator-name = "vreg_l9a";
+			regulator-min-microvolt = <2970000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1140000>;
+			regulator-max-microvolt = <1260000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c: ldo3 {
+			regulator-name = "vreg_l3c";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5c: ldo5 {
+			regulator-name = "vreg_l5c";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <1980000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <2400000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <2700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vreg_s4e: smps4 {
+			regulator-name = "vreg_s4e";
+			regulator-min-microvolt = <970000>;
+			regulator-max-microvolt = <1520000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s7e: smps7 {
+			regulator-name = "vreg_s7e";
+			regulator-min-microvolt = <1010000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9e: smps9 {
+			regulator-name = "vreg_s9e";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <570000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6e: ldo6 {
+			regulator-name = "vreg_l6e";
+			regulator-min-microvolt = <1280000>;
+			regulator-max-microvolt = <1450000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8e: ldo8 {
+			regulator-name = "vreg_l8e";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32768>;
+};
+
+&tlmm {
+	qup_uart10_default: qup-uart10-state {
+		pins = "gpio46", "gpio47";
+		function = "qup1_se3";
+	};
+};
+
+&uart10 {
+	compatible = "qcom,geni-debug-uart";
+	pinctrl-0 = <&qup_uart10_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
--
2.49.0

Re: [PATCH v7 4/6] arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

[Konrad Dybcio]

On 5/21/25 4:08 PM, Wasim Nazir wrote:
> Add initial device tree support for IQ-9075-EVK board,
> based on Qualcomm's QCS9075 SOC.
> 
> Implement basic changes to enable boot to shell.
> 
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---

[...]

two nits:

> +&tlmm {
> +	qup_uart10_default: qup-uart10-state {
> +		pins = "gpio46", "gpio47";
> +		function = "qup1_se3";
> +	};

Feel free to move it over to sa8775p.dtsi

> +};
> +
> +&uart10 {
> +	compatible = "qcom,geni-debug-uart";
> +	pinctrl-0 = <&qup_uart10_default>;
> +	pinctrl-names = "default";
> +	status = "okay";

Please keep a newline before 'status'

Konrad

Re: [PATCH v7 4/6] arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

[Wasim Nazir]

On Wed, May 21, 2025 at 06:57:03PM +0200, Konrad Dybcio wrote:
> On 5/21/25 4:08 PM, Wasim Nazir wrote:
> > Add initial device tree support for IQ-9075-EVK board,
> > based on Qualcomm's QCS9075 SOC.
> > 
> > Implement basic changes to enable boot to shell.
> > 
> > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > ---
> 
> [...]
> 
> two nits:
> 
> > +&tlmm {
> > +	qup_uart10_default: qup-uart10-state {
> > +		pins = "gpio46", "gpio47";
> > +		function = "qup1_se3";
> > +	};
> 
> Feel free to move it over to sa8775p.dtsi

Thanks for pointing it out. Will move this to SOC file.

> 
> > +};
> > +
> > +&uart10 {
> > +	compatible = "qcom,geni-debug-uart";
> > +	pinctrl-0 = <&qup_uart10_default>;
> > +	pinctrl-names = "default";
> > +	status = "okay";
> 
> Please keep a newline before 'status'

Sure.

> 
> Konrad

Regards,
Wasim

[PATCH v7 5/6] arm64: dts: qcom: Add support L4C LDO for qcs9075 IQ-9075-EVK

[Wasim Nazir]

From: Rakesh Kota <quic_kotarake@quicinc.com>

Add support L4C LDO for qcs9075 IQ-9075-EVK.

Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
index dbc64496759d..30a36ffa40be 100644
--- a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
+++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
@@ -143,6 +143,16 @@ vreg_l3c: ldo3 {
 						   RPMH_REGULATOR_MODE_HPM>;
 		};

+		vreg_l4c: ldo4 {
+			regulator-name = "vreg_l4c";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
 		vreg_l5c: ldo5 {
 			regulator-name = "vreg_l5c";
 			regulator-min-microvolt = <1100000>;
--
2.49.0

Re: [PATCH v7 5/6] arm64: dts: qcom: Add support L4C LDO for qcs9075 IQ-9075-EVK

[Krzysztof Kozlowski]

On 21/05/2025 16:08, Wasim Nazir wrote:
> From: Rakesh Kota <quic_kotarake@quicinc.com>
> 
> Add support L4C LDO for qcs9075 IQ-9075-EVK.
> 
> Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts | 10 ++++++++++

You just added this file. What is the point of doing changes node by node?



Best regards,
Krzysztof

[PATCH v7 6/6] arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

[Wasim Nazir]

From: Sayali Lokhande <quic_sayalil@quicinc.com>

Add UFS support for qcs9075 IQ-9075-EVK board.

Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 .../arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
index 30a36ffa40be..ba8a359d8fee 100644
--- a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
+++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
@@ -276,3 +276,20 @@ &uart10 {
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l8a>;
+	vcc-max-microamp = <1100000>;
+	vccq-supply = <&vreg_l4c>;
+	vccq-max-microamp = <1200000>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l4a>;
+	vdda-pll-supply = <&vreg_l1c>;
+
+	status = "okay";
+};
--
2.49.0

Re: [PATCH v7 6/6] arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

[Krzysztof Kozlowski]

On 21/05/2025 16:08, Wasim Nazir wrote:
> From: Sayali Lokhande <quic_sayalil@quicinc.com>
> 
> Add UFS support for qcs9075 IQ-9075-EVK board.
> 
> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---
>  .../arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
> index 30a36ffa40be..ba8a359d8fee 100644
> --- a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
> @@ -276,3 +276,20 @@ &uart10 {
>  &xo_board_clk {
>  	clock-frequency = <38400000>;
>  };
> +
> +&ufs_mem_hc {

Please follow DTS coding style.

Best regards,
Krzysztof

Re: [PATCH v7 6/6] arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

[Krzysztof Kozlowski]

On 21/05/2025 16:21, Krzysztof Kozlowski wrote:
> On 21/05/2025 16:08, Wasim Nazir wrote:
>> From: Sayali Lokhande <quic_sayalil@quicinc.com>
>>
>> Add UFS support for qcs9075 IQ-9075-EVK board.
>>
>> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
>> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
>> ---
>>  .../arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts | 17 +++++++++++++++++
>>  1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
>> index 30a36ffa40be..ba8a359d8fee 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
>> @@ -276,3 +276,20 @@ &uart10 {
>>  &xo_board_clk {
>>  	clock-frequency = <38400000>;
>>  };
>> +
>> +&ufs_mem_hc {
> 
> Please follow DTS coding style.

And you just added this file. Squash the patches so you will see the
mishap in ordering.

Best regards,
Krzysztof

Re: [PATCH v7 6/6] arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

[Wasim Nazir]

On Wed, May 21, 2025 at 04:23:02PM +0200, Krzysztof Kozlowski wrote:
> On 21/05/2025 16:21, Krzysztof Kozlowski wrote:
> > On 21/05/2025 16:08, Wasim Nazir wrote:
> >> From: Sayali Lokhande <quic_sayalil@quicinc.com>
> >>
> >> Add UFS support for qcs9075 IQ-9075-EVK board.
> >>
> >> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> >> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> >> ---
> >>  .../arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts | 17 +++++++++++++++++
> >>  1 file changed, 17 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
> >> index 30a36ffa40be..ba8a359d8fee 100644
> >> --- a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
> >> +++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
> >> @@ -276,3 +276,20 @@ &uart10 {
> >>  &xo_board_clk {
> >>  	clock-frequency = <38400000>;
> >>  };
> >> +
> >> +&ufs_mem_hc {
> > 
> > Please follow DTS coding style.

Thanks for pointing it out. This will help other contributors to
understand the issue.

> 
> And you just added this file. Squash the patches so you will see the
> mishap in ordering.

Sure will do that in next series.

> 
> Best regards,
> Krzysztof

Regards,
Wasim

Re: [PATCH v7 6/6] arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

[Dmitry Baryshkov]

On 21/05/2025 17:08, Wasim Nazir wrote:
> From: Sayali Lokhande <quic_sayalil@quicinc.com>
> 
> Add UFS support for qcs9075 IQ-9075-EVK board.
> 
> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>

Squash two last patches into the previous one. Use Co-developed-by+SoB 
to denote all contributors.

-- 
With best wishes
Dmitry

Re: [PATCH v7 6/6] arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK

[Wasim Nazir]

On Wed, May 21, 2025 at 05:33:52PM +0300, Dmitry Baryshkov wrote:
> On 21/05/2025 17:08, Wasim Nazir wrote:
> > From: Sayali Lokhande <quic_sayalil@quicinc.com>
> > 
> > Add UFS support for qcs9075 IQ-9075-EVK board.
> > 
> > Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> 
> Squash two last patches into the previous one. Use Co-developed-by+SoB to
> denote all contributors.

Thanks Dmitry for the clarity, will push another series accordingly.

> 
> -- 
> With best wishes
> Dmitry

Regards,
Wasim

Re: [PATCH v7 0/6] qcom: Add support for IQ-9075-evk board

[Rob Herring (Arm)]

On Wed, 21 May 2025 19:37:59 +0530, Wasim Nazir wrote:
> This series:
> 
> Add support for Qualcomm's iq9-evk board using QCS9075 SOC.
> 
> QCS9075 is compatible IoT-industrial grade variant of SA8775p SOC.
> Unlike QCS9100, it doesn't have safety monitoring feature of
> Safety-Island(SAIL) subsystem, which affects thermal management.
> 
> In QCS9100 SOC, the safety subsystem monitors all thermal sensors and
> does corrective action for each subsystem based on sensor violation
> to comply safety standards. But as QCS9075 is non-safe SOC it requires
> conventional thermal mitigation for thermal management.
> In this series thermal mitigation changes are not included as it needs
> more discussion whether to include the change in DT or in drivers.
> 
> Below are detailed informations on IQ-9075-evk HW:
> ------------------------------------------------------
> QCS9075 SOM is stacked on top of IQ-9075-evk board.
> On top of IQ-9075-evk board additional mezzanine boards can be stacked
> in future.
> IQ-9075-evk is single board supporting these peripherals:
>   - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
>     eMMC on mezzanine card
>   - Audio/Video, Camera & Display ports
>   - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD
>   - Sensors: IMU
>   - PCIe ports
>   - USB & UART ports
> 
> Currently basic features are enabled to support 'boot to shell'.
> 
> ---
> Changelog:
> 
> v7:
>   - Add UFS support along with l4c regulator from [1]
>   - Remove "qcom,qcs9075-som" compatible and keep only SOM dtsi file
>   - Increase camera pil size
>   - Update commit text as per new changes
>   - v6-link: [2]
> 
> [1] https://lore.kernel.org/all/20250513084309.10275-1-quic_sayalil@quicinc.com/
> [2] https://lore.kernel.org/all/20250429054906.113317-1-quic_wasimn@quicinc.com/
> 
> Pratyush Brahma (1):
>   arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075
> 
> Rakesh Kota (1):
>   arm64: dts: qcom: Add support L4C LDO for qcs9075 IQ-9075-EVK
> 
> Sayali Lokhande (1):
>   arm64: dts: qcom: Add UFS support for qcs9075 IQ-9075-EVK
> 
> Wasim Nazir (3):
>   dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board
>   arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM
>   arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK
> 
>  .../devicetree/bindings/arm/qcom.yaml         |   7 +
>  arch/arm64/boot/dts/qcom/Makefile             |   1 +
>  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 +++++++
>  .../boot/dts/qcom/qcs9075-iq-9075-evk.dts     | 295 ++++++++++++++++++
>  arch/arm64/boot/dts/qcom/qcs9075-som.dtsi     |  10 +
>  5 files changed, 426 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> 
> 
> base-commit: 8566fc3b96539e3235909d6bdda198e1282beaed
> --
> 2.49.0
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 8566fc3b96539e3235909d6bdda198e1282beaed

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250521140807.3837019-1-quic_wasimn@quicinc.com:

arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dtb: display-controller@ae01000 (qcom,sa8775p-dpu): clock-names:0: 'nrt_bus' was expected
	from schema $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dtb: rsc@18200000 (qcom,rpmh-rsc): 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#