* [DPU PATCH 01/19] drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-2-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 02/19] drm/msm: dpu_crtc: " Sean Paul
` (17 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_encoder with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 290 ++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 329 ++++++++++++++++++++
2 files changed, 464 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 11a1045bf132..6aad40dccb05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -254,11 +254,9 @@ static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
{
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->intf_idx - INTF_0,
- phys_enc->hw_pp->idx - PINGPONG_0,
- intr_idx);
- DPU_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
+ DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
+ DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
+ phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(
@@ -284,25 +282,23 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
/* return EWOULDBLOCK since we know the wait isn't necessary */
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
- DPU_ERROR_PHYS(phys_enc, "encoder is disabled\n");
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, intr_idx, DPU_EVTLOG_ERROR);
+ DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx);
return -EWOULDBLOCK;
}
if (irq->irq_idx < 0) {
- DPU_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
- irq->name, irq->hw_idx);
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx);
+ DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->name);
return 0;
}
- DPU_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
- atomic_read(wait_info->atomic_cnt));
- DPU_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt), DPU_EVTLOG_FUNC_ENTRY);
+ DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
ret = dpu_encoder_helper_wait_event_timeout(
DRMID(phys_enc->parent),
@@ -315,36 +311,33 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
if (irq_status) {
unsigned long flags;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx,
- irq->hw_idx, irq->irq_idx,
- phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt));
- DPU_DEBUG_PHYS(phys_enc,
- "done but irq %d not triggered\n",
- irq->irq_idx);
+ DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
+ "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx,
+ irq->hw_idx, irq->irq_idx,
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
local_irq_save(flags);
irq->cb.func(phys_enc, irq->irq_idx);
local_irq_restore(flags);
ret = 0;
} else {
ret = -ETIMEDOUT;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx,
- irq->hw_idx, irq->irq_idx,
- phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt), irq_status,
- DPU_EVTLOG_ERROR);
+ DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
+ "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx,
+ irq->hw_idx, irq->irq_idx,
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
}
} else {
ret = 0;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
+ trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
+ intr_idx, irq->hw_idx, irq->irq_idx,
+ phys_enc->hw_pp->idx - PINGPONG_0,
atomic_read(wait_info->atomic_cnt));
}
- DPU_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt), DPU_EVTLOG_FUNC_EXIT);
-
return ret;
}
@@ -388,22 +381,17 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
if (ret) {
- DPU_ERROR_PHYS(phys_enc,
- "enable IRQ for intr:%s failed, irq_idx %d\n",
- irq->name, irq->irq_idx);
-
+ DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx);
dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
irq->irq_idx, &irq->cb);
-
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, DPU_EVTLOG_ERROR);
irq->irq_idx = -EINVAL;
return ret;
}
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
- DPU_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
- irq->name, irq->irq_idx);
+ trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
+ irq->hw_idx, irq->irq_idx);
return ret;
}
@@ -422,28 +410,29 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
/* silently skip irqs that weren't registered */
if (irq->irq_idx < 0) {
- DPU_ERROR(
- "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
- DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx);
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, DPU_EVTLOG_ERROR);
+ DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx);
return 0;
}
ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
- if (ret)
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, ret, DPU_EVTLOG_ERROR);
+ if (ret) {
+ DRM_ERROR("diable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, ret);
+ }
ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
&irq->cb);
- if (ret)
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, ret, DPU_EVTLOG_ERROR);
+ if (ret) {
+ DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, ret);
+ }
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
- DPU_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
+ trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
+ irq->hw_idx, irq->irq_idx);
irq->irq_idx = -EINVAL;
@@ -628,7 +617,7 @@ static int dpu_encoder_virt_atomic_check(
dpu_kms = to_dpu_kms(priv->kms);
mode = &crtc_state->mode;
adj_mode = &crtc_state->adjusted_mode;
- DPU_EVT32(DRMID(drm_enc));
+ trace_dpu_enc_atomic_check(DRMID(drm_enc));
/*
* display drivers may populate private fields of the drm display mode
@@ -676,7 +665,8 @@ static int dpu_encoder_virt_atomic_check(
if (!ret)
drm_mode_set_crtcinfo(adj_mode, 0);
- DPU_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
+ trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
+ adj_mode->private_flags);
return ret;
}
@@ -766,8 +756,7 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
- DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
- DPU_EVT32(DRMID(drm_enc), enable);
+ trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
if (!dpu_enc->cur_master) {
DPU_ERROR("encoder master not set\n");
@@ -825,10 +814,8 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
return 0;
- DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, idle_pc_supported:%d\n", sw_event,
- dpu_enc->idle_pc_supported);
- DPU_EVT32_VERBOSE(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
- dpu_enc->rc_state, DPU_EVTLOG_FUNC_ENTRY);
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
+ dpu_enc->rc_state, "begin");
switch (sw_event) {
case DPU_ENC_RC_EVENT_KICKOFF:
@@ -842,18 +829,15 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
/* return if the resource control is already in ON state */
if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
- DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, rc in ON state\n",
- sw_event);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_FUNC_CASE1);
+ DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
+ DRMID(drm_enc), sw_event);
mutex_unlock(&dpu_enc->rc_lock);
return 0;
} else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
- DPU_ERROR_ENC(dpu_enc, "sw_event:%d, rc in state %d\n",
- sw_event, dpu_enc->rc_state);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_ERROR);
+ DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
+ DRMID(drm_enc), sw_event,
+ dpu_enc->rc_state);
mutex_unlock(&dpu_enc->rc_lock);
return -EINVAL;
}
@@ -863,10 +847,12 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
else
_dpu_encoder_resource_control_helper(drm_enc, true);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_ENC_RC_STATE_ON, DPU_EVTLOG_FUNC_CASE1);
dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "kickoff");
+
mutex_unlock(&dpu_enc->rc_lock);
break;
@@ -878,10 +864,9 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
* the resource_control
*/
if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
- DPU_ERROR_ENC(dpu_enc, "sw_event:%d,rc:%d-unexpected\n",
- sw_event, dpu_enc->rc_state);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_ERROR);
+ DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
+ DRMID(drm_enc), sw_event,
+ dpu_enc->rc_state);
return -EINVAL;
}
@@ -890,9 +875,8 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
* frames pending
*/
if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
- DPU_DEBUG_ENC(dpu_enc, "skip schedule work");
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_FUNC_CASE2);
+ DRM_DEBUG_KMS("id:%d skip schedule work\n",
+ DRMID(drm_enc));
return 0;
}
@@ -901,10 +885,9 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
&dpu_enc->delayed_off_work,
msecs_to_jiffies(dpu_enc->idle_timeout));
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- dpu_enc->idle_timeout, DPU_EVTLOG_FUNC_CASE2);
- DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
- sw_event);
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "frame done");
break;
case DPU_ENC_RC_EVENT_PRE_STOP:
@@ -923,20 +906,19 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
/* skip if is already OFF or IDLE, resources are off already */
else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
- DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, rc in %d state\n",
- sw_event, dpu_enc->rc_state);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_FUNC_CASE3);
+ DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
+ DRMID(drm_enc), sw_event,
+ dpu_enc->rc_state);
mutex_unlock(&dpu_enc->rc_lock);
return 0;
}
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_ENC_RC_STATE_PRE_OFF,
- DPU_EVTLOG_FUNC_CASE3);
-
dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "pre stop");
+
mutex_unlock(&dpu_enc->rc_lock);
break;
@@ -945,17 +927,13 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
/* return if the resource control is already in OFF state */
if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
- DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, rc in OFF state\n",
- sw_event);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_FUNC_CASE4);
+ DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
+ DRMID(drm_enc), sw_event);
mutex_unlock(&dpu_enc->rc_lock);
return 0;
} else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
- DPU_ERROR_ENC(dpu_enc, "sw_event:%d, rc in state %d\n",
- sw_event, dpu_enc->rc_state);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_ERROR);
+ DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
+ DRMID(drm_enc), sw_event, dpu_enc->rc_state);
mutex_unlock(&dpu_enc->rc_lock);
return -EINVAL;
}
@@ -967,11 +945,12 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
_dpu_encoder_resource_control_helper(drm_enc, false);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_ENC_RC_STATE_OFF, DPU_EVTLOG_FUNC_CASE4);
-
dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "stop");
+
mutex_unlock(&dpu_enc->rc_lock);
break;
@@ -979,10 +958,8 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
mutex_lock(&dpu_enc->rc_lock);
if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
- DPU_ERROR_ENC(dpu_enc, "sw_event:%d, rc:%d !ON state\n",
- sw_event, dpu_enc->rc_state);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_ERROR);
+ DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
+ DRMID(drm_enc), sw_event, dpu_enc->rc_state);
mutex_unlock(&dpu_enc->rc_lock);
return 0;
}
@@ -992,11 +969,8 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
* ignore the IDLE event, it's probably a stale timer event
*/
if (dpu_enc->frame_busy_mask[0]) {
- DPU_ERROR_ENC(dpu_enc,
- "sw_event:%d, rc:%d frame pending\n",
- sw_event, dpu_enc->rc_state);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_EVTLOG_ERROR);
+ DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
+ DRMID(drm_enc), sw_event, dpu_enc->rc_state);
mutex_unlock(&dpu_enc->rc_lock);
return 0;
}
@@ -1006,21 +980,27 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
else
_dpu_encoder_resource_control_helper(drm_enc, false);
- DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
- DPU_ENC_RC_STATE_IDLE, DPU_EVTLOG_FUNC_CASE7);
dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "idle");
+
mutex_unlock(&dpu_enc->rc_lock);
break;
default:
- DPU_EVT32(DRMID(drm_enc), sw_event, DPU_EVTLOG_ERROR);
- DPU_ERROR("unexpected sw_event: %d\n", sw_event);
+ DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
+ sw_event);
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "error");
break;
}
- DPU_EVT32_VERBOSE(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
- dpu_enc->rc_state, DPU_EVTLOG_FUNC_EXIT);
+ trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
+ dpu_enc->idle_pc_supported, dpu_enc->rc_state,
+ "end");
return 0;
}
@@ -1050,7 +1030,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
dpu_kms = to_dpu_kms(priv->kms);
connector_list = &dpu_kms->dev->mode_config.connector_list;
- DPU_EVT32(DRMID(drm_enc));
+ trace_dpu_enc_mode_set(DRMID(drm_enc));
list_for_each_entry(conn_iter, connector_list, head)
if (conn_iter->encoder == drm_enc)
@@ -1180,8 +1160,8 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
dpu_enc = to_dpu_encoder_virt(drm_enc);
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
- DPU_DEBUG_ENC(dpu_enc, "\n");
- DPU_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
+ trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
+ cur_mode->vdisplay);
dpu_enc->cur_master = NULL;
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
@@ -1256,7 +1236,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
- DPU_EVT32(DRMID(drm_enc));
+ trace_dpu_enc_disable(DRMID(drm_enc));
/* wait for idle */
dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
@@ -1334,7 +1314,8 @@ static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
DPU_ATRACE_BEGIN("encoder_underrun_callback");
atomic_inc(&phy_enc->underrun_cnt);
- DPU_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
+ trace_dpu_enc_underrun_cb(DRMID(drm_enc),
+ atomic_read(&phy_enc->underrun_cnt));
DPU_ATRACE_END("encoder_underrun_callback");
}
@@ -1352,8 +1333,7 @@ void dpu_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
DPU_ERROR("invalid encoder\n");
return;
}
- DPU_DEBUG_ENC(dpu_enc, "\n");
- DPU_EVT32(DRMID(drm_enc), enable);
+ trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
dpu_enc->crtc_vblank_cb = vbl_cb;
@@ -1382,8 +1362,7 @@ void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
DPU_ERROR("invalid encoder\n");
return;
}
- DPU_DEBUG_ENC(dpu_enc, "\n");
- DPU_EVT32(DRMID(drm_enc), enable, 0);
+ trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
dpu_enc->crtc_frame_event_cb = frame_event_cb;
@@ -1407,7 +1386,8 @@ static void dpu_encoder_frame_done_callback(
* suppress frame_done without waiter,
* likely autorefresh
*/
- DPU_EVT32(DRMID(drm_enc), event, ready_phys->intf_idx);
+ trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
+ event, ready_phys->intf_idx);
return;
}
@@ -1415,8 +1395,8 @@ static void dpu_encoder_frame_done_callback(
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
if (dpu_enc->phys_encs[i] == ready_phys) {
clear_bit(i, dpu_enc->frame_busy_mask);
- DPU_EVT32_VERBOSE(DRMID(drm_enc), i,
- dpu_enc->frame_busy_mask[0]);
+ trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
+ dpu_enc->frame_busy_mask[0]);
}
}
@@ -1467,6 +1447,7 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
{
struct dpu_hw_ctl *ctl;
int pending_kickoff_cnt;
+ u32 ret = UINT_MAX;
if (!drm_enc || !phys) {
DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
@@ -1493,11 +1474,10 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
ctl->ops.trigger_flush(ctl);
if (ctl->ops.get_pending_flush)
- DPU_EVT32(DRMID(drm_enc), phys->intf_idx, pending_kickoff_cnt,
- ctl->idx, ctl->ops.get_pending_flush(ctl));
- else
- DPU_EVT32(DRMID(drm_enc), phys->intf_idx, ctl->idx,
- pending_kickoff_cnt);
+ ret = ctl->ops.get_pending_flush(ctl);
+
+ trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
+ pending_kickoff_cnt, ctl->idx, ret);
}
/**
@@ -1532,7 +1512,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
ctl = phys_enc->hw_ctl;
if (ctl && ctl->ops.trigger_start) {
ctl->ops.trigger_start(ctl);
- DPU_EVT32(DRMID(phys_enc->parent), ctl->idx);
+ trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
}
}
@@ -1551,8 +1531,9 @@ int dpu_encoder_helper_wait_event_timeout(
atomic_read(info->atomic_cnt) == 0, jiffies);
time = ktime_to_ms(ktime_get());
- DPU_EVT32_VERBOSE(drm_id, hw_id, rc, time, expected_time,
- atomic_read(info->atomic_cnt));
+ trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
+ expected_time,
+ atomic_read(info->atomic_cnt));
/* If we timed out, counter is valid and time is less, wait again */
} while (atomic_read(info->atomic_cnt) && (rc == 0) &&
(time < expected_time));
@@ -1576,8 +1557,8 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
if (!ctl || !ctl->ops.reset)
return;
- DPU_DEBUG_ENC(dpu_enc, "ctl %d reset\n", ctl->idx);
- DPU_EVT32(DRMID(phys_enc->parent), ctl->idx);
+ DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
+ ctl->idx);
rc = ctl->ops.reset(ctl);
if (rc) {
@@ -1832,7 +1813,7 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
if (_dpu_encoder_wakeup_time(&dpu_enc->base, &wakeup_time))
return;
- DPU_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
+ trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
mod_timer(&dpu_enc->vsync_event_timer,
nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
}
@@ -1851,8 +1832,7 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
}
dpu_enc = to_dpu_encoder_virt(drm_enc);
- DPU_DEBUG_ENC(dpu_enc, "\n");
- DPU_EVT32(DRMID(drm_enc));
+ trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
/* prepare for next kickoff, may include waiting on previous kickoff */
DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
@@ -1871,7 +1851,7 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
/* if any phys needs reset, reset all phys, in-order */
if (needs_hw_reset) {
- DPU_EVT32(DRMID(drm_enc), DPU_EVTLOG_FUNC_CASE1);
+ trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
phys = dpu_enc->phys_encs[i];
if (phys && phys->ops.hw_reset)
@@ -1894,7 +1874,7 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
DPU_ATRACE_BEGIN("encoder_kickoff");
dpu_enc = to_dpu_encoder_virt(drm_enc);
- DPU_DEBUG_ENC(dpu_enc, "\n");
+ trace_dpu_enc_kickoff(DRMID(drm_enc));
atomic_set(&dpu_enc->frame_done_timeout,
DPU_FRAME_DONE_TIMEOUT * 1000 /
@@ -1914,7 +1894,8 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
!_dpu_encoder_wakeup_time(drm_enc, &wakeup_time)) {
- DPU_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
+ trace_dpu_enc_early_kickoff(DRMID(drm_enc),
+ ktime_to_ms(wakeup_time));
mod_timer(&dpu_enc->vsync_event_timer,
nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
}
@@ -2415,19 +2396,18 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t)
priv = drm_enc->dev->dev_private;
if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
- DPU_DEBUG_ENC(dpu_enc, "invalid timeout\n");
- DPU_EVT32(DRMID(drm_enc), dpu_enc->frame_busy_mask[0], 0);
+ DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
+ DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
return;
} else if (!atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
- DPU_ERROR_ENC(dpu_enc, "invalid timeout\n");
- DPU_EVT32(DRMID(drm_enc), 0, 1);
+ DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
return;
}
DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
event = DPU_ENCODER_FRAME_EVENT_ERROR;
- DPU_EVT32(DRMID(drm_enc), event);
+ trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index bbc0fe65efac..b00bdcd0f4e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -17,6 +17,9 @@
#include <linux/types.h>
#include <linux/tracepoint.h>
+#include "dpu_encoder_phys.h"
+#include "dpu_hw_mdss.h"
+
#undef TRACE_SYSTEM
#define TRACE_SYSTEM dpu
#undef TRACE_INCLUDE_FILE
@@ -230,6 +233,332 @@ TRACE_EVENT(dpu_perf_crtc_update,
__entry->update_clk)
);
+DECLARE_EVENT_CLASS(dpu_enc_irq_template,
+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+ int irq_idx),
+ TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_intr_idx, intr_idx )
+ __field( int, hw_idx )
+ __field( int, irq_idx )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intr_idx = intr_idx;
+ __entry->hw_idx = hw_idx;
+ __entry->irq_idx = irq_idx;
+ ),
+ TP_printk("id=%u, intr=%d, hw=%d, irq=%d",
+ __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
+ __entry->irq_idx)
+);
+DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+ int irq_idx),
+ TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
+);
+DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+ int irq_idx),
+ TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
+);
+
+TRACE_EVENT(dpu_enc_irq_wait_success,
+ TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+ int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
+ TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_intr_idx, intr_idx )
+ __field( int, hw_idx )
+ __field( int, irq_idx )
+ __field( enum dpu_pingpong, pp_idx )
+ __field( int, atomic_cnt )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intr_idx = intr_idx;
+ __entry->hw_idx = hw_idx;
+ __entry->irq_idx = irq_idx;
+ __entry->pp_idx = pp_idx;
+ __entry->atomic_cnt = atomic_cnt;
+ ),
+ TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+ __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
+ __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
+);
+
+DECLARE_EVENT_CLASS(dpu_drm_obj_template,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ ),
+ TP_printk("id=%u", __entry->drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+
+TRACE_EVENT(dpu_enc_enable,
+ TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
+ TP_ARGS(drm_id, hdisplay, vdisplay),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( int, hdisplay )
+ __field( int, vdisplay )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->hdisplay = hdisplay;
+ __entry->vdisplay = vdisplay;
+ ),
+ TP_printk("id=%u, mode=%dx%d",
+ __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
+);
+
+DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
+ TP_PROTO(uint32_t drm_id, int val),
+ TP_ARGS(drm_id, val),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( int, val )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->val = val;
+ ),
+ TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
+);
+DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
+ TP_PROTO(uint32_t drm_id, int count),
+ TP_ARGS(drm_id, count)
+);
+DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
+ TP_PROTO(uint32_t drm_id, int ctl_idx),
+ TP_ARGS(drm_id, ctl_idx)
+);
+
+TRACE_EVENT(dpu_enc_atomic_check_flags,
+ TP_PROTO(uint32_t drm_id, unsigned int flags, int private_flags),
+ TP_ARGS(drm_id, flags, private_flags),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( unsigned int, flags )
+ __field( int, private_flags )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->flags = flags;
+ __entry->private_flags = private_flags;
+ ),
+ TP_printk("id=%u, flags=%u, private_flags=%d",
+ __entry->drm_id, __entry->flags, __entry->private_flags)
+);
+
+DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
+ TP_PROTO(uint32_t drm_id, bool enable),
+ TP_ARGS(drm_id, enable),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( bool, enable )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->enable = enable;
+ ),
+ TP_printk("id=%u, enable=%s",
+ __entry->drm_id, __entry->enable ? "true" : "false")
+);
+DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
+ TP_PROTO(uint32_t drm_id, bool enable),
+ TP_ARGS(drm_id, enable)
+);
+DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
+ TP_PROTO(uint32_t drm_id, bool enable),
+ TP_ARGS(drm_id, enable)
+);
+DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
+ TP_PROTO(uint32_t drm_id, bool enable),
+ TP_ARGS(drm_id, enable)
+);
+
+TRACE_EVENT(dpu_enc_rc,
+ TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
+ int rc_state, const char *stage),
+ TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( u32, sw_event )
+ __field( bool, idle_pc_supported )
+ __field( int, rc_state )
+ __string( stage_str, stage )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->sw_event = sw_event;
+ __entry->idle_pc_supported = idle_pc_supported;
+ __entry->rc_state = rc_state;
+ __assign_str(stage_str, stage);
+ ),
+ TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d\n",
+ __get_str(stage_str), __entry->drm_id, __entry->sw_event,
+ __entry->idle_pc_supported ? "true" : "false",
+ __entry->rc_state)
+);
+
+TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
+ TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx),
+ TP_ARGS(drm_id, event, intf_idx),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( u32, event )
+ __field( enum dpu_intf, intf_idx )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->event = event;
+ __entry->intf_idx = intf_idx;
+ ),
+ TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event,
+ __entry->intf_idx)
+);
+
+TRACE_EVENT(dpu_enc_frame_done_cb,
+ TP_PROTO(uint32_t drm_id, unsigned int idx,
+ unsigned long frame_busy_mask),
+ TP_ARGS(drm_id, idx, frame_busy_mask),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( unsigned int, idx )
+ __field( unsigned long, frame_busy_mask )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->idx = idx;
+ __entry->frame_busy_mask = frame_busy_mask;
+ ),
+ TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
+ __entry->idx, __entry->frame_busy_mask)
+);
+
+TRACE_EVENT(dpu_enc_trigger_flush,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
+ int pending_kickoff_cnt, int ctl_idx, u32 pending_flush_ret),
+ TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx,
+ pending_flush_ret),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_intf, intf_idx )
+ __field( int, pending_kickoff_cnt )
+ __field( int, ctl_idx )
+ __field( u32, pending_flush_ret )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intf_idx = intf_idx;
+ __entry->pending_kickoff_cnt = pending_kickoff_cnt;
+ __entry->ctl_idx = ctl_idx;
+ __entry->pending_flush_ret = pending_flush_ret;
+ ),
+ TP_printk("id=%u, intf_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
+ "pending_flush_ret=%u", __entry->drm_id,
+ __entry->intf_idx, __entry->pending_kickoff_cnt,
+ __entry->ctl_idx, __entry->pending_flush_ret)
+);
+
+DECLARE_EVENT_CLASS(dpu_enc_ktime_template,
+ TP_PROTO(uint32_t drm_id, ktime_t time),
+ TP_ARGS(drm_id, time),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( ktime_t, time )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->time = time;
+ ),
+ TP_printk("id=%u, time=%lld", __entry->drm_id,
+ ktime_to_ms(__entry->time))
+);
+DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work,
+ TP_PROTO(uint32_t drm_id, ktime_t time),
+ TP_ARGS(drm_id, time)
+);
+DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff,
+ TP_PROTO(uint32_t drm_id, ktime_t time),
+ TP_ARGS(drm_id, time)
+);
+
+DECLARE_EVENT_CLASS(dpu_id_event_template,
+ TP_PROTO(uint32_t drm_id, u32 event),
+ TP_ARGS(drm_id, event),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( u32, event )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->event = event;
+ ),
+ TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
+);
+DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
+ TP_PROTO(uint32_t drm_id, u32 event),
+ TP_ARGS(drm_id, event)
+);
+
+TRACE_EVENT(dpu_enc_wait_event_timeout,
+ TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
+ s64 expected_time, int atomic_cnt),
+ TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( int32_t, hw_id )
+ __field( int, rc )
+ __field( s64, time )
+ __field( s64, expected_time )
+ __field( int, atomic_cnt )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->hw_id = hw_id;
+ __entry->rc = rc;
+ __entry->time = time;
+ __entry->expected_time = expected_time;
+ __entry->atomic_cnt = atomic_cnt;
+ ),
+ TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
+ __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
+ __entry->expected_time, __entry->atomic_cnt)
+);
+
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 02/19] drm/msm: dpu_crtc: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 01/19] drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-3-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 03/19] drm/msm: dpu_plane: " Sean Paul
` (16 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_crtc with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 122 ++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 166 ++++++++++++++++++++++
2 files changed, 210 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9ca8325877a1..eefc1892ad47 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,18 +431,12 @@ static void *_dpu_crtc_rp_get(struct dpu_crtc_respool *rp, u32 type, u64 tag)
list_for_each_entry(res, &old_rp->res_list, list) {
if (res->type != type)
continue;
- DPU_DEBUG(
- "crtc%d.%u found res:0x%x//%pK/ in crtc%d.%d\n",
- crtc->base.id,
- rp->sequence_id,
- res->type, res->val,
- crtc->base.id,
- old_rp->sequence_id);
- DPU_EVT32_VERBOSE(crtc->base.id,
- rp->sequence_id,
- res->type, res->val,
- crtc->base.id,
- old_rp->sequence_id);
+ DRM_DEBUG_KMS("crtc%d.%u found res:0x%x//%pK/ "
+ "in crtc%d.%d\n",
+ crtc->base.id, rp->sequence_id,
+ res->type, res->val,
+ crtc->base.id,
+ old_rp->sequence_id);
if (res->ops.get)
res->ops.get(res->val, 0, -1);
val = res->val;
@@ -688,23 +682,17 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
- DPU_EVT32(DRMID(crtc), DRMID(plane),
- state->fb ? state->fb->base.id : -1,
- state->src_x >> 16, state->src_y >> 16,
- state->src_w >> 16, state->src_h >> 16,
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h);
-
stage_idx = zpos_cnt[pstate->stage]++;
stage_cfg->stage[pstate->stage][stage_idx] =
dpu_plane_pipe(plane);
stage_cfg->multirect_index[pstate->stage][stage_idx] =
pstate->multirect_index;
- DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
- dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- pstate->multirect_index, pstate->multirect_mode,
- format->base.pixel_format, fb ? fb->modifier : 0);
+ trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
+ state, pstate, stage_idx,
+ dpu_plane_pipe(plane) - SSPP_VIG0,
+ format->base.pixel_format,
+ fb ? fb->modifier : 0);
/* blend config update */
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
@@ -821,7 +809,7 @@ static void _dpu_crtc_complete_flip(struct drm_crtc *crtc,
dpu_crtc->event = NULL;
DRM_DEBUG_VBL("%s: send event: %pK\n",
dpu_crtc->name, event);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_complete_flip(DRMID(crtc));
drm_crtc_send_vblank_event(crtc, event);
}
}
@@ -856,8 +844,7 @@ static void dpu_crtc_vblank_cb(void *data)
dpu_crtc->vblank_cb_count++;
_dpu_crtc_complete_flip(crtc, NULL);
drm_crtc_handle_vblank(crtc);
- DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_vblank_cb(DRMID(crtc));
}
/* _dpu_crtc_idle_notify - signal idle timeout to client */
@@ -933,34 +920,28 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work)
priv = dpu_kms->dev->dev_private;
DPU_ATRACE_BEGIN("crtc_frame_event");
- DPU_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
+ DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
ktime_to_ns(fevent->ts));
- DPU_EVT32_VERBOSE(DRMID(crtc), fevent->event, DPU_EVTLOG_FUNC_ENTRY);
-
if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
| DPU_ENCODER_FRAME_EVENT_ERROR
| DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
if (atomic_read(&dpu_crtc->frame_pending) < 1) {
/* this should not happen */
- DPU_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
+ DRM_ERROR("crtc%d ev:%u ts:%lld frame_pending:%d\n",
crtc->base.id,
+ fevent->event,
ktime_to_ns(fevent->ts),
atomic_read(&dpu_crtc->frame_pending));
- DPU_EVT32(DRMID(crtc), fevent->event,
- DPU_EVTLOG_FUNC_CASE1);
} else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
/* release bandwidth and other resources */
- DPU_DEBUG("crtc%d ts:%lld last pending\n",
- crtc->base.id,
- ktime_to_ns(fevent->ts));
- DPU_EVT32(DRMID(crtc), fevent->event,
- DPU_EVTLOG_FUNC_CASE2);
+ trace_dpu_crtc_frame_event_done(DRMID(crtc),
+ fevent->event);
dpu_core_perf_crtc_release_bw(crtc);
} else {
- DPU_EVT32_VERBOSE(DRMID(crtc), fevent->event,
- DPU_EVTLOG_FUNC_CASE3);
+ trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
+ fevent->event);
}
if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE)
@@ -1011,8 +992,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event)
priv = crtc->dev->dev_private;
crtc_id = drm_crtc_index(crtc);
- DPU_DEBUG("crtc%d\n", crtc->base.id);
- DPU_EVT32_VERBOSE(DRMID(crtc), event);
+ trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
/* try to process the event in caller context */
event_processed = _dpu_crtc_handle_event(dpu_crtc, event);
@@ -1027,9 +1007,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event)
spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
if (!fevent) {
- DPU_ERROR("crtc%d event %d overflow\n",
- crtc->base.id, event);
- DPU_EVT32(DRMID(crtc), event);
+ DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event);
return;
}
@@ -1046,7 +1024,7 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
DPU_ERROR("invalid crtc\n");
return;
}
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_complete_commit(DRMID(crtc));
}
static void _dpu_crtc_setup_mixer_for_encoder(
@@ -1146,9 +1124,8 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
cstate->lm_bounds[i].w = crtc_split_width;
cstate->lm_bounds[i].h =
dpu_crtc_get_mixer_height(dpu_crtc, cstate, adj_mode);
- DPU_EVT32_VERBOSE(DRMID(crtc), i,
- cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
- cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
+ trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i,
+ &cstate->lm_bounds[i]);
}
drm_mode_debug_printmodeline(adj_mode);
@@ -1345,16 +1322,14 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
return 0;
}
- DPU_EVT32_VERBOSE(DRMID(crtc), DPU_EVTLOG_FUNC_ENTRY);
+ DPU_ATRACE_BEGIN("frame done completion wait");
ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
msecs_to_jiffies(DPU_FRAME_DONE_TIMEOUT));
if (!ret) {
- DPU_ERROR("frame done completion wait timed out, ret:%d\n",
- ret);
- DPU_EVT32(DRMID(crtc), DPU_EVTLOG_FATAL);
+ DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
rc = -ETIMEDOUT;
}
- DPU_EVT32_VERBOSE(DRMID(crtc), DPU_EVTLOG_FUNC_EXIT);
+ DPU_ATRACE_END("frame done completion wait");
return rc;
}
@@ -1477,10 +1452,9 @@ static int _dpu_crtc_vblank_enable_no_lock(
if (enc->crtc != crtc)
continue;
- DPU_EVT32(DRMID(&dpu_crtc->base), DRMID(enc), enable,
- dpu_crtc->enabled,
- dpu_crtc->suspend,
- dpu_crtc->vblank_requested);
+ trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base),
+ DRMID(enc), enable,
+ dpu_crtc);
dpu_encoder_register_vblank_callback(enc,
dpu_crtc_vblank_cb, (void *)crtc);
@@ -1490,10 +1464,9 @@ static int _dpu_crtc_vblank_enable_no_lock(
if (enc->crtc != crtc)
continue;
- DPU_EVT32(DRMID(&dpu_crtc->base), DRMID(enc), enable,
- dpu_crtc->enabled,
- dpu_crtc->suspend,
- dpu_crtc->vblank_requested);
+ trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base),
+ DRMID(enc), enable,
+ dpu_crtc);
dpu_encoder_register_vblank_callback(enc, NULL, NULL);
}
@@ -1532,8 +1505,7 @@ static void _dpu_crtc_set_suspend(struct drm_crtc *crtc, bool enable)
}
dpu_kms = to_dpu_kms(priv->kms);
- DPU_DEBUG("crtc%d suspend = %d\n", crtc->base.id, enable);
- DPU_EVT32_VERBOSE(DRMID(crtc), enable);
+ DRM_DEBUG_KMS("crtc%d suspend = %d\n", crtc->base.id, enable);
mutex_lock(&dpu_crtc->crtc_lock);
@@ -1541,8 +1513,7 @@ static void _dpu_crtc_set_suspend(struct drm_crtc *crtc, bool enable)
* If the vblank is enabled, release a power reference on suspend
* and take it back during resume (if it is still enabled).
*/
- DPU_EVT32(DRMID(&dpu_crtc->base), enable, dpu_crtc->enabled,
- dpu_crtc->suspend, dpu_crtc->vblank_requested);
+ trace_dpu_crtc_set_suspend(DRMID(&dpu_crtc->base), enable, dpu_crtc);
if (dpu_crtc->suspend == enable)
DPU_DEBUG("crtc%d suspend already set to %d, ignoring update\n",
crtc->base.id, enable);
@@ -1644,7 +1615,7 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
mutex_lock(&dpu_crtc->crtc_lock);
- DPU_EVT32(DRMID(crtc), event_type);
+ trace_dpu_crtc_handle_power_event(DRMID(crtc), event_type);
switch (event_type) {
case DPU_POWER_EVENT_POST_ENABLE:
@@ -1712,13 +1683,12 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
mode = &cstate->base.adjusted_mode;
priv = crtc->dev->dev_private;
- DPU_DEBUG("crtc%d\n", crtc->base.id);
+ DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
if (dpu_kms_is_suspend_state(crtc->dev))
_dpu_crtc_set_suspend(crtc, true);
mutex_lock(&dpu_crtc->crtc_lock);
- DPU_EVT32_VERBOSE(DRMID(crtc));
/* update color processing on suspend */
event.type = DRM_EVENT_CRTC_POWER;
@@ -1733,8 +1703,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
crtc->base.id,
atomic_read(&dpu_crtc->frame_pending));
- DPU_EVT32(DRMID(crtc), dpu_crtc->enabled, dpu_crtc->suspend,
- dpu_crtc->vblank_requested);
+ trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
if (dpu_crtc->enabled && !dpu_crtc->suspend &&
dpu_crtc->vblank_requested) {
ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, false);
@@ -1745,8 +1714,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
dpu_crtc->enabled = false;
if (atomic_read(&dpu_crtc->frame_pending)) {
- DPU_EVT32(DRMID(crtc), atomic_read(&dpu_crtc->frame_pending),
- DPU_EVTLOG_FUNC_CASE2);
+ trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
+ atomic_read(&dpu_crtc->frame_pending));
dpu_core_perf_crtc_release_bw(crtc);
atomic_set(&dpu_crtc->frame_pending, 0);
}
@@ -1791,8 +1760,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
}
priv = crtc->dev->dev_private;
- DPU_DEBUG("crtc%d\n", crtc->base.id);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
dpu_crtc = to_dpu_crtc(crtc);
drm_for_each_encoder(encoder, crtc->dev) {
@@ -1803,8 +1771,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
}
mutex_lock(&dpu_crtc->crtc_lock);
- DPU_EVT32(DRMID(crtc), dpu_crtc->enabled, dpu_crtc->suspend,
- dpu_crtc->vblank_requested);
+ trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
if (!dpu_crtc->enabled && !dpu_crtc->suspend &&
dpu_crtc->vblank_requested) {
ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, true);
@@ -2078,8 +2045,7 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
dpu_crtc = to_dpu_crtc(crtc);
mutex_lock(&dpu_crtc->crtc_lock);
- DPU_EVT32(DRMID(&dpu_crtc->base), en, dpu_crtc->enabled,
- dpu_crtc->suspend, dpu_crtc->vblank_requested);
+ trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
if (dpu_crtc->enabled && !dpu_crtc->suspend) {
ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, en);
if (ret)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index b00bdcd0f4e8..877621184782 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -17,8 +17,10 @@
#include <linux/types.h>
#include <linux/tracepoint.h>
+#include "dpu_crtc.h"
#include "dpu_encoder_phys.h"
#include "dpu_hw_mdss.h"
+#include "dpu_plane.h"
#undef TRACE_SYSTEM
#define TRACE_SYSTEM dpu
@@ -324,6 +326,18 @@ DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
TRACE_EVENT(dpu_enc_enable,
TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
@@ -532,6 +546,22 @@ DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
TP_PROTO(uint32_t drm_id, u32 event),
TP_ARGS(drm_id, event)
);
+DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
+ TP_PROTO(uint32_t drm_id, u32 event),
+ TP_ARGS(drm_id, event)
+);
+DEFINE_EVENT(dpu_id_event_template, dpu_crtc_handle_power_event,
+ TP_PROTO(uint32_t drm_id, u32 event),
+ TP_ARGS(drm_id, event)
+);
+DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
+ TP_PROTO(uint32_t drm_id, u32 event),
+ TP_ARGS(drm_id, event)
+);
+DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
+ TP_PROTO(uint32_t drm_id, u32 event),
+ TP_ARGS(drm_id, event)
+);
TRACE_EVENT(dpu_enc_wait_event_timeout,
TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
@@ -558,6 +588,142 @@ TRACE_EVENT(dpu_enc_wait_event_timeout,
__entry->expected_time, __entry->atomic_cnt)
);
+TRACE_EVENT(dpu_crtc_setup_mixer,
+ TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
+ struct drm_plane_state *state, struct dpu_plane_state *pstate,
+ uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format,
+ uint64_t modifier),
+ TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
+ pixel_format, modifier),
+ TP_STRUCT__entry(
+ __field( uint32_t, crtc_id )
+ __field( uint32_t, plane_id )
+ __field( struct drm_plane_state*,state )
+ __field( struct dpu_plane_state*,pstate )
+ __field( uint32_t, stage_idx )
+ __field( enum dpu_sspp, sspp )
+ __field( uint32_t, pixel_format )
+ __field( uint64_t, modifier )
+ ),
+ TP_fast_assign(
+ __entry->crtc_id = crtc_id;
+ __entry->plane_id = plane_id;
+ __entry->state = state;
+ __entry->pstate = pstate;
+ __entry->stage_idx = stage_idx;
+ __entry->sspp = sspp;
+ __entry->pixel_format = pixel_format;
+ __entry->modifier = modifier;
+ ),
+ TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:{%ux%u+%ux%u} "
+ "dst:{%ux%u+%ux%u} stage_idx:%u stage:%d, sspp:%d "
+ "multirect_index:%d multirect_mode:%u pix_format:%u "
+ "modifier:%llu",
+ __entry->crtc_id, __entry->plane_id,
+ __entry->state->fb ? __entry->state->fb->base.id : -1,
+ __entry->state->src_w >> 16, __entry->state->src_h >> 16,
+ __entry->state->src_x >> 16, __entry->state->src_y >> 16,
+ __entry->state->crtc_w, __entry->state->crtc_h,
+ __entry->state->crtc_x, __entry->state->crtc_y,
+ __entry->stage_idx, __entry->pstate->stage, __entry->sspp,
+ __entry->pstate->multirect_index,
+ __entry->pstate->multirect_mode, __entry->pixel_format,
+ __entry->modifier)
+);
+
+TRACE_EVENT(dpu_crtc_setup_lm_bounds,
+ TP_PROTO(uint32_t drm_id, int mixer, struct dpu_rect *bounds),
+ TP_ARGS(drm_id, mixer, bounds),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( int, mixer )
+ __field( struct dpu_rect *, bounds )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->mixer = mixer;
+ __entry->bounds = bounds;
+ ),
+ TP_printk("id:%u mixer:%d bounds:{%ux%u/%ux%u}", __entry->drm_id,
+ __entry->mixer, __entry->bounds->x, __entry->bounds->y,
+ __entry->bounds->w, __entry->bounds->h)
+);
+
+TRACE_EVENT(dpu_crtc_vblank_enable,
+ TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
+ struct dpu_crtc *crtc),
+ TP_ARGS(drm_id, enc_id, enable, crtc),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( uint32_t, enc_id )
+ __field( bool, enable )
+ __field( struct dpu_crtc *, crtc )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->enc_id = enc_id;
+ __entry->enable = enable;
+ __entry->crtc = crtc;
+ ),
+ TP_printk("id:%u encoder:%u enable:%s state{enabled:%s suspend:%s "
+ "vblank_req:%s}",
+ __entry->drm_id, __entry->enc_id,
+ __entry->enable ? "true" : "false",
+ __entry->crtc->enabled ? "true" : "false",
+ __entry->crtc->suspend ? "true" : "false",
+ __entry->crtc->vblank_requested ? "true" : "false")
+);
+
+DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
+ TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
+ TP_ARGS(drm_id, enable, crtc),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( bool, enable )
+ __field( struct dpu_crtc *, crtc )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->enable = enable;
+ __entry->crtc = crtc;
+ ),
+ TP_printk("id:%u enable:%s state{enabled:%s suspend:%s vblank_req:%s}",
+ __entry->drm_id, __entry->enable ? "true" : "false",
+ __entry->crtc->enabled ? "true" : "false",
+ __entry->crtc->suspend ? "true" : "false",
+ __entry->crtc->vblank_requested ? "true" : "false")
+);
+DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_set_suspend,
+ TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
+ TP_ARGS(drm_id, enable, crtc)
+);
+DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
+ TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
+ TP_ARGS(drm_id, enable, crtc)
+);
+DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
+ TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
+ TP_ARGS(drm_id, enable, crtc)
+);
+DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
+ TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
+ TP_ARGS(drm_id, enable, crtc)
+);
+
+TRACE_EVENT(dpu_crtc_disable_frame_pending,
+ TP_PROTO(uint32_t drm_id, int frame_pending),
+ TP_ARGS(drm_id, frame_pending),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( int, frame_pending )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->frame_pending = frame_pending;
+ ),
+ TP_printk("id:%u frame_pending:%d", __entry->drm_id,
+ __entry->frame_pending)
+);
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 03/19] drm/msm: dpu_plane: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 01/19] drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints Sean Paul
2018-06-20 20:48 ` [DPU PATCH 02/19] drm/msm: dpu_crtc: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-4-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 04/19] drm/msm: dpu_rm: " Sean Paul
` (15 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_plane with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 19 +++-------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 44 +++++++++++++++++++++++
2 files changed, 49 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 6090ace6012a..2c3dc00477b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -609,18 +609,9 @@ static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
else if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
- DPU_EVT32_VERBOSE(pdpu->pipe_hw->idx,
- pipe_cfg->layout.width,
- pipe_cfg->layout.height,
- pipe_cfg->layout.plane_addr[0],
- pipe_cfg->layout.plane_size[0],
- pipe_cfg->layout.plane_addr[1],
- pipe_cfg->layout.plane_size[1],
- pipe_cfg->layout.plane_addr[2],
- pipe_cfg->layout.plane_size[2],
- pipe_cfg->layout.plane_addr[3],
- pipe_cfg->layout.plane_size[3],
- pstate->multirect_index);
+ trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
+ &pipe_cfg->layout,
+ pstate->multirect_index);
pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
pstate->multirect_index);
}
@@ -1420,8 +1411,8 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane,
state = plane->state;
pstate = to_dpu_plane_state(state);
- DPU_EVT32(DRMID(plane), is_dpu_plane_virtual(plane),
- pstate->multirect_mode);
+ trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
+ pstate->multirect_mode);
pstate->pending = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 877621184782..5d3aa5a994be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -725,6 +725,50 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending,
__entry->frame_pending)
);
+TRACE_EVENT(dpu_plane_set_scanout,
+ TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
+ enum dpu_sspp_multirect_index multirect_index),
+ TP_ARGS(index, layout, multirect_index),
+ TP_STRUCT__entry(
+ __field( enum dpu_sspp, index )
+ __field( struct dpu_hw_fmt_layout*, layout )
+ __field( enum dpu_sspp_multirect_index, multirect_index)
+ ),
+ TP_fast_assign(
+ __entry->index = index;
+ __entry->layout = layout;
+ __entry->multirect_index = multirect_index;
+ ),
+ TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
+ "multirect_index:%d", __entry->index, __entry->layout->width,
+ __entry->layout->height, __entry->layout->plane_addr[0],
+ __entry->layout->plane_size[0],
+ __entry->layout->plane_addr[1],
+ __entry->layout->plane_size[1],
+ __entry->layout->plane_addr[2],
+ __entry->layout->plane_size[2],
+ __entry->layout->plane_addr[3],
+ __entry->layout->plane_size[3], __entry->multirect_index)
+);
+
+TRACE_EVENT(dpu_plane_disable,
+ TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
+ TP_ARGS(drm_id, is_virtual, multirect_mode),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( bool, is_virtual )
+ __field( uint32_t, multirect_mode )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->is_virtual = is_virtual;
+ __entry->multirect_mode = multirect_mode;
+ ),
+ TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
+ __entry->is_virtual ? "true" : "false",
+ __entry->multirect_mode)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 04/19] drm/msm: dpu_rm: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (2 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 03/19] drm/msm: dpu_plane: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-5-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 05/19] drm/msm: dpu_kms: " Sean Paul
` (14 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_rm with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 65 ++++++++++-------------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 49 +++++++++++++++++
2 files changed, 78 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index eff316bb2134..13c0a36d4ef9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -20,6 +20,7 @@
#include "dpu_hw_pingpong.h"
#include "dpu_hw_intf.h"
#include "dpu_encoder.h"
+#include "dpu_trace.h"
#define RESERVED_BY_OTHER(h, r) \
((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
@@ -121,9 +122,8 @@ static void _dpu_rm_print_rsvps(
DPU_DEBUG("%d\n", stage);
list_for_each_entry(rsvp, &rm->rsvps, list) {
- DPU_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
- rsvp->enc_id, rsvp->topology);
- DPU_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
+ DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
+ rsvp->enc_id, rsvp->topology);
}
for (type = 0; type < DPU_HW_BLK_MAX; type++) {
@@ -131,14 +131,7 @@ static void _dpu_rm_print_rsvps(
if (!blk->rsvp && !blk->rsvp_nxt)
continue;
- DPU_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
- (blk->rsvp) ? blk->rsvp->seq : 0,
- (blk->rsvp) ? blk->rsvp->enc_id : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
- blk->type, blk->id);
-
- DPU_EVT32(stage,
+ DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
(blk->rsvp) ? blk->rsvp->seq : 0,
(blk->rsvp) ? blk->rsvp->enc_id : 0,
(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
@@ -597,7 +590,8 @@ static int _dpu_rm_reserve_lms(
lm[i]->rsvp_nxt = rsvp;
pp[i]->rsvp_nxt = rsvp;
- DPU_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id);
+ trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, rsvp->enc_id,
+ pp[i]->id);
}
return rc;
@@ -642,7 +636,8 @@ static int _dpu_rm_reserve_ctls(
for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
ctls[i]->rsvp_nxt = rsvp;
- DPU_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
+ trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
+ rsvp->enc_id);
}
return 0;
@@ -656,6 +651,8 @@ static int _dpu_rm_reserve_cdm(
{
struct dpu_rm_hw_iter iter;
+ DRM_DEBUG_KMS("type %d id %d\n", type, id);
+
dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CDM);
while (_dpu_rm_get_hw_locked(rm, &iter)) {
const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw);
@@ -668,14 +665,16 @@ static int _dpu_rm_reserve_cdm(
if (type == DPU_HW_BLK_INTF && id != INTF_MAX)
match = test_bit(id, &caps->intf_connect);
- DPU_DEBUG("type %d id %d, cdm intfs %lu match %d\n",
- type, id, caps->intf_connect, match);
+ DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n",
+ iter.blk->type, iter.blk->id, rsvp->enc_id,
+ caps->intf_connect, match);
if (!match)
continue;
+ trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type,
+ rsvp->enc_id);
iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
break;
}
@@ -709,7 +708,8 @@ static int _dpu_rm_reserve_intf(
}
iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
+ trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
+ rsvp->enc_id);
break;
}
@@ -801,7 +801,6 @@ static int _dpu_rm_populate_requirements(
struct dpu_rm_requirements *reqs,
struct msm_display_topology req_topology)
{
- const struct drm_display_mode *mode = &crtc_state->mode;
int i;
memset(reqs, 0, sizeof(*reqs));
@@ -830,15 +829,12 @@ static int _dpu_rm_populate_requirements(
conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)
reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS);
- DPU_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
- reqs->hw_res.display_num_of_h_tiles);
- DPU_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
- reqs->topology->num_lm, reqs->topology->num_ctl,
- reqs->topology->top_name,
- reqs->topology->needs_split_display);
- DPU_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
- reqs->top_ctrl, reqs->topology->top_name,
- reqs->topology->num_ctl);
+ DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
+ reqs->hw_res.display_num_of_h_tiles);
+ DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
+ reqs->topology->num_lm, reqs->topology->num_ctl,
+ reqs->topology->top_name,
+ reqs->topology->needs_split_display);
return 0;
}
@@ -972,11 +968,9 @@ static int _dpu_rm_commit_rsvp(
}
}
- if (!ret) {
- DPU_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id,
- rsvp->topology);
- DPU_EVT32(rsvp->enc_id, rsvp->topology);
- }
+ if (!ret)
+ DRM_DEBUG_KMS("rsrv enc %d topology %d\n", rsvp->enc_id,
+ rsvp->topology);
return ret;
}
@@ -1002,10 +996,9 @@ int dpu_rm_reserve(
if (!drm_atomic_crtc_needs_modeset(crtc_state))
return 0;
- DPU_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
- conn_state->connector->base.id, enc->base.id,
- crtc_state->crtc->base.id, test_only);
- DPU_EVT32(enc->base.id, conn_state->connector->base.id);
+ DRM_DEBUG_KMS("reserving hw for conn %d enc %d crtc %d test_only %d\n",
+ conn_state->connector->base.id, enc->base.id,
+ crtc_state->crtc->base.id, test_only);
mutex_lock(&rm->rm_lock);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 5d3aa5a994be..99c45b8d84c0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -769,6 +769,55 @@ TRACE_EVENT(dpu_plane_disable,
__entry->multirect_mode)
);
+DECLARE_EVENT_CLASS(dpu_rm_iter_template,
+ TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
+ TP_ARGS(id, type, enc_id),
+ TP_STRUCT__entry(
+ __field( uint32_t, id )
+ __field( enum dpu_hw_blk_type, type )
+ __field( uint32_t, enc_id )
+ ),
+ TP_fast_assign(
+ __entry->id = id;
+ __entry->type = type;
+ __entry->enc_id = enc_id;
+ ),
+ TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
+ __entry->enc_id)
+);
+DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_cdm,
+ TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
+ TP_ARGS(id, type, enc_id)
+);
+DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
+ TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
+ TP_ARGS(id, type, enc_id)
+);
+DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
+ TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
+ TP_ARGS(id, type, enc_id)
+);
+
+TRACE_EVENT(dpu_rm_reserve_lms,
+ TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id,
+ uint32_t pp_id),
+ TP_ARGS(id, type, enc_id, pp_id),
+ TP_STRUCT__entry(
+ __field( uint32_t, id )
+ __field( enum dpu_hw_blk_type, type )
+ __field( uint32_t, enc_id )
+ __field( uint32_t, pp_id )
+ ),
+ TP_fast_assign(
+ __entry->id = id;
+ __entry->type = type;
+ __entry->enc_id = enc_id;
+ __entry->pp_id = pp_id;
+ ),
+ TP_printk("id:%d type:%d enc_id:%u pp_id:%u", __entry->id,
+ __entry->type, __entry->enc_id, __entry->pp_id)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 05/19] drm/msm: dpu_kms: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (3 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 04/19] drm/msm: dpu_rm: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-6-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 06/19] drm/msm: dpu_encoder_phys_cmd: " Sean Paul
` (13 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_kms with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ++++++++++++-------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 16 ++++++++++++++++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe614c06bb7b..6ae5bba21074 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -362,7 +362,7 @@ static void dpu_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
* Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
* complete
*/
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_kms_wait_for_frame_transfer(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR(
@@ -410,7 +410,7 @@ void dpu_kms_encoder_enable(struct drm_encoder *encoder)
funcs->commit(encoder);
if (crtc && crtc->state->active) {
- DPU_EVT32(DRMID(crtc));
+ trace_dpu_kms_enc_enable(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
}
}
@@ -427,7 +427,7 @@ static void dpu_kms_commit(struct msm_kms *kms, struct drm_atomic_state *state)
continue;
if (crtc->state->active) {
- DPU_EVT32(DRMID(crtc));
+ trace_dpu_kms_commit(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
}
}
@@ -450,12 +450,14 @@ static void dpu_kms_complete_commit(struct msm_kms *kms,
return;
priv = dpu_kms->dev->dev_private;
+ DPU_ATRACE_BEGIN("kms_complete_commit");
+
for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
dpu_crtc_complete_commit(crtc, old_crtc_state);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
- DPU_EVT32_VERBOSE(DPU_EVTLOG_FUNC_EXIT);
+ DPU_ATRACE_END("kms_complete_commit");
}
static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
@@ -490,7 +492,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
* plane_cleanup. For example, wait for vsync in case of video
* mode panels. This may be a no-op for command mode panels.
*/
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR("wait for commit done returned %d\n", ret);
@@ -1137,7 +1139,6 @@ static int dpu_kms_pm_suspend(struct device *dev)
return -EINVAL;
dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev));
- DPU_EVT32(0);
/* disable hot-plug polling */
drm_kms_helper_poll_disable(ddev);
@@ -1146,6 +1147,8 @@ static int dpu_kms_pm_suspend(struct device *dev)
drm_modeset_acquire_init(&ctx, 0);
retry:
+ DPU_ATRACE_BEGIN("kms_pm_suspend");
+
ret = drm_modeset_lock_all_ctx(ddev, &ctx);
if (ret)
goto unlock;
@@ -1195,6 +1198,7 @@ static int dpu_kms_pm_suspend(struct device *dev)
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
+ DPU_ATRACE_END("kms_pm_suspend");
return 0;
}
@@ -1213,7 +1217,7 @@ static int dpu_kms_pm_resume(struct device *dev)
dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev));
- DPU_EVT32(dpu_kms->suspend_state != NULL);
+ DPU_ATRACE_BEGIN("kms_pm_resume");
drm_mode_config_reset(ddev);
@@ -1236,6 +1240,7 @@ static int dpu_kms_pm_resume(struct device *dev)
/* enable hot-plug polling */
drm_kms_helper_poll_enable(ddev);
+ DPU_ATRACE_END("kms_pm_resume");
return 0;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 99c45b8d84c0..7169ff3a9805 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -338,6 +338,22 @@ DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_frame_transfer,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
TRACE_EVENT(dpu_enc_enable,
TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 06/19] drm/msm: dpu_encoder_phys_cmd: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (4 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 05/19] drm/msm: dpu_kms: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-7-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 07/19] drm/msm: dpu_encoder_phys_vid: " Sean Paul
` (12 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_encoder_phys_cmd with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 79 +++++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 68 ++++++++++++++++
2 files changed, 104 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 388de384e2cf..eb9314aaa85f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -108,8 +108,9 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
- DPU_EVT32_IRQ(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0, new_cnt, event);
+ trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ new_cnt, event);
/* Signal any waiting atomic commit thread */
wake_up_all(&phys_enc->pending_kickoff_wq);
@@ -245,21 +246,20 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
do_log = true;
}
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- cmd_enc->pp_timeout_report_cnt,
- atomic_read(&phys_enc->pending_kickoff_cnt),
- frame_event);
+ trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ cmd_enc->pp_timeout_report_cnt,
+ atomic_read(&phys_enc->pending_kickoff_cnt),
+ frame_event);
/* to avoid flooding, only log first time, and "dead" time */
if (do_log) {
- DPU_ERROR_CMDENC(cmd_enc,
- "pp:%d kickoff timed out ctl %d cnt %d koff_cnt %d\n",
- phys_enc->hw_pp->idx - PINGPONG_0,
- phys_enc->hw_ctl->idx - CTL_0,
- cmd_enc->pp_timeout_report_cnt,
- atomic_read(&phys_enc->pending_kickoff_cnt));
-
- DPU_EVT32(DRMID(phys_enc->parent), DPU_EVTLOG_FATAL);
+ DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ phys_enc->hw_ctl->idx - CTL_0,
+ cmd_enc->pp_timeout_report_cnt,
+ atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
@@ -308,8 +308,6 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
struct dpu_encoder_phys *phys_enc,
bool enable)
{
- struct dpu_encoder_phys_cmd *cmd_enc =
- to_dpu_encoder_phys_cmd(phys_enc);
int ret = 0;
int refcount;
@@ -330,10 +328,9 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
goto end;
}
- DPU_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0), enable, refcount);
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- enable, refcount);
+ DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ enable ? "true" : "false", refcount);
if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR);
@@ -343,12 +340,10 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
end:
if (ret) {
- DPU_ERROR_CMDENC(cmd_enc,
- "control vblank irq error %d, enable %d, refcount %d\n",
- ret, enable, refcount);
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0,
- enable, refcount, DPU_EVTLOG_ERROR);
+ DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0, ret,
+ enable ? "true" : "false", refcount);
}
return ret;
@@ -364,7 +359,8 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
+ trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
enable, atomic_read(&phys_enc->vblank_refcount));
if (enable) {
@@ -557,7 +553,7 @@ static void _dpu_encoder_phys_cmd_connect_te(
!phys_enc->hw_pp->ops.connect_external_te)
return;
- DPU_EVT32(DRMID(phys_enc->parent), enable);
+ trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable);
phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable);
}
@@ -594,11 +590,9 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
DPU_ERROR("invalid encoder\n");
return;
}
- DPU_DEBUG_CMDENC(cmd_enc, "pp %d state %d\n",
- phys_enc->hw_pp->idx - PINGPONG_0,
- phys_enc->enable_state);
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- phys_enc->enable_state);
+ DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ phys_enc->enable_state);
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
DPU_ERROR_CMDENC(cmd_enc, "already disabled\n");
@@ -656,10 +650,9 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff(
DPU_ERROR("invalid encoder\n");
return;
}
- DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
-
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(&phys_enc->pending_kickoff_cnt));
+ DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(&phys_enc->pending_kickoff_cnt));
/*
* Mark kickoff request as outstanding. If there are more than one,
@@ -669,9 +662,9 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff(
if (ret) {
/* force pending_kickoff_cnt 0 to discard failed kickoff */
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0);
- DPU_ERROR("failed wait_for_idle: %d\n", ret);
+ DRM_ERROR("failed wait_for_idle: id:%u ret:%d pp:%d\n",
+ DRMID(phys_enc->parent), ret,
+ phys_enc->hw_pp->idx - PINGPONG_0);
}
DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n",
@@ -720,9 +713,9 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete(
rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
if (rc) {
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->intf_idx - INTF_0);
- DPU_ERROR("failed wait_for_idle: %d\n", rc);
+ DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n",
+ DRMID(phys_enc->parent), rc,
+ phys_enc->intf_idx - INTF_0);
}
return rc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 7169ff3a9805..a6313c4343c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -437,6 +437,10 @@ DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
TP_PROTO(uint32_t drm_id, bool enable),
TP_ARGS(drm_id, enable)
);
+DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
+ TP_PROTO(uint32_t drm_id, bool enable),
+ TP_ARGS(drm_id, enable)
+);
TRACE_EVENT(dpu_enc_rc,
TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
@@ -604,6 +608,70 @@ TRACE_EVENT(dpu_enc_wait_event_timeout,
__entry->expected_time, __entry->atomic_cnt)
);
+TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
+ TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
+ int refcnt),
+ TP_ARGS(drm_id, pp, enable, refcnt),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_pingpong, pp )
+ __field( bool, enable )
+ __field( int, refcnt )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->pp = pp;
+ __entry->enable = enable;
+ __entry->refcnt = refcnt;
+ ),
+ TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
+ __entry->pp, __entry->enable ? "true" : "false",
+ __entry->refcnt)
+);
+
+TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
+ TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
+ u32 event),
+ TP_ARGS(drm_id, pp, new_count, event),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_pingpong, pp )
+ __field( int, new_count )
+ __field( u32, event )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->pp = pp;
+ __entry->new_count = new_count;
+ __entry->event = event;
+ ),
+ TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
+ __entry->pp, __entry->new_count, __entry->event)
+);
+
+TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
+ TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
+ int kickoff_count, u32 event),
+ TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_pingpong, pp )
+ __field( int, timeout_count )
+ __field( int, kickoff_count )
+ __field( u32, event )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->pp = pp;
+ __entry->timeout_count = timeout_count;
+ __entry->kickoff_count = kickoff_count;
+ __entry->event = event;
+ ),
+ TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
+ __entry->drm_id, __entry->pp, __entry->timeout_count,
+ __entry->kickoff_count, __entry->event)
+);
+
TRACE_EVENT(dpu_crtc_setup_mixer,
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
struct drm_plane_state *state, struct dpu_plane_state *pstate,
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 07/19] drm/msm: dpu_encoder_phys_vid: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (5 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 06/19] drm/msm: dpu_encoder_phys_cmd: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-8-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 08/19] drm/msm: dpu_vbif: " Sean Paul
` (11 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_encoder_phys_vid with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 36 ++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 35 ++++++++++++++++++
2 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 73e59382eeac..fc83745b48fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -458,12 +458,8 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
goto end;
}
- DPU_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0),
- enable, atomic_read(&phys_enc->vblank_refcount));
-
- DPU_EVT32(DRMID(phys_enc->parent), enable,
- atomic_read(&phys_enc->vblank_refcount));
+ DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
+ atomic_read(&phys_enc->vblank_refcount));
if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
@@ -473,12 +469,10 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
end:
if (ret) {
- DPU_ERROR_VIDENC(vid_enc,
- "control vblank irq error %d, enable %d\n",
- ret, enable);
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0,
- enable, refcount, DPU_EVTLOG_ERROR);
+ DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
+ DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0, ret, enable,
+ refcount);
}
return ret;
}
@@ -697,11 +691,9 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false);
if (ret) {
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
- DPU_ERROR_VIDENC(vid_enc,
- "failure waiting for disable: %d\n",
- ret);
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0, ret);
+ DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
+ DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0, ret);
}
}
@@ -727,8 +719,8 @@ static void dpu_encoder_phys_vid_handle_post_kickoff(
* Video encoders need to turn on their interfaces now
*/
if (phys_enc->enable_state == DPU_ENC_ENABLING) {
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0);
+ trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0);
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 1);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
@@ -747,8 +739,10 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- DPU_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0,
- enable, atomic_read(&phys_enc->vblank_refcount));
+ trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0,
+ enable,
+ atomic_read(&phys_enc->vblank_refcount));
if (enable) {
ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index a6313c4343c8..c9041e2a7aa1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -672,6 +672,41 @@ TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
__entry->kickoff_count, __entry->event)
);
+TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
+ TP_ARGS(drm_id, intf_idx),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_intf, intf_idx )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intf_idx = intf_idx;
+ ),
+ TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
+);
+
+TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
+ int refcnt),
+ TP_ARGS(drm_id, intf_idx, enable, refcnt),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_intf, intf_idx )
+ __field( bool, enable )
+ __field( int, refcnt )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intf_idx = intf_idx;
+ __entry->enable = enable;
+ __entry->refcnt = refcnt;
+ ),
+ TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
+ __entry->intf_idx, __entry->enable ? "true" : "false",
+ __entry->drm_id)
+);
+
TRACE_EVENT(dpu_crtc_setup_mixer,
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
struct drm_plane_state *state, struct dpu_plane_state *pstate,
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 08/19] drm/msm: dpu_vbif: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (6 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 07/19] drm/msm: dpu_encoder_phys_vid: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-9-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 09/19] drm/msm: dpu_pingpong: " Sean Paul
` (10 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_vbif with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 15 +++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 7 +++----
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index c9041e2a7aa1..73f76387803f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -20,6 +20,7 @@
#include "dpu_crtc.h"
#include "dpu_encoder_phys.h"
#include "dpu_hw_mdss.h"
+#include "dpu_hw_vbif.h"
#include "dpu_plane.h"
#undef TRACE_SYSTEM
@@ -937,6 +938,20 @@ TRACE_EVENT(dpu_rm_reserve_lms,
__entry->type, __entry->enc_id, __entry->pp_id)
);
+TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
+ TP_PROTO(enum dpu_vbif index, u32 xin_id),
+ TP_ARGS(index, xin_id),
+ TP_STRUCT__entry(
+ __field( enum dpu_vbif, index )
+ __field( u32, xin_id )
+ ),
+ TP_fast_assign(
+ __entry->index = index;
+ __entry->xin_id = xin_id;
+ ),
+ TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
index 801155fe0989..295528292296 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
@@ -204,7 +204,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
ret = _dpu_vbif_wait_for_xin_halt(vbif, params->xin_id);
if (ret)
- DPU_EVT32(vbif->idx, params->xin_id);
+ trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id);
vbif->ops.set_halt_ctrl(vbif, params->xin_id, false);
@@ -284,9 +284,8 @@ void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms)
if (vbif && vbif->ops.clear_errors) {
vbif->ops.clear_errors(vbif, &pnd, &src);
if (pnd || src) {
- DPU_EVT32(i, pnd, src);
- DPU_DEBUG("VBIF %d: pnd 0x%X, src 0x%X\n",
- vbif->idx - VBIF_0, pnd, src);
+ DRM_DEBUG_KMS("VBIF %d: pnd 0x%X, src 0x%X\n",
+ vbif->idx - VBIF_0, pnd, src);
}
}
}
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 09/19] drm/msm: dpu_pingpong: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (7 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 08/19] drm/msm: dpu_vbif: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-10-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 10/19] drm/msm: dpu_core_irq: " Sean Paul
` (9 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_pingpong with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 14 ++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 84d2176ecafb..12e90b8e5466 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -18,6 +18,7 @@
#include "dpu_hw_pingpong.h"
#include "dpu_dbg.h"
#include "dpu_kms.h"
+#include "dpu_trace.h"
#define PP_TEAR_CHECK_EN 0x000
#define PP_SYNC_CONFIG_VSYNC 0x004
@@ -134,7 +135,7 @@ static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
else
cfg &= ~BIT(20);
DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
- DPU_EVT32(pp->idx - PINGPONG_0, cfg);
+ trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
return orig;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 73f76387803f..9d044f5ce26e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -952,6 +952,20 @@ TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
);
+TRACE_EVENT(dpu_pp_connect_ext_te,
+ TP_PROTO(enum dpu_pingpong pp, u32 cfg),
+ TP_ARGS(pp, cfg),
+ TP_STRUCT__entry(
+ __field( enum dpu_pingpong, pp )
+ __field( u32, cfg )
+ ),
+ TP_fast_assign(
+ __entry->pp = pp;
+ __entry->cfg = cfg;
+ ),
+ TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 10/19] drm/msm: dpu_core_irq: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (8 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 09/19] drm/msm: dpu_pingpong: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-11-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 11/19] drm/msm: dpu_core_perf: " Sean Paul
` (8 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_core_irq with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 52 ++++++++------------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 50 +++++++++++++++++++
2 files changed, 71 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 33ab2ac46833..530c24dec017 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -18,6 +18,7 @@
#include <linux/kthread.h>
#include "dpu_core_irq.h"
+#include "dpu_trace.h"
/**
* dpu_core_irq_callback_handler - dispatch core interrupts
@@ -34,10 +35,8 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
pr_debug("irq_idx=%d\n", irq_idx);
if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
- DPU_ERROR("irq_idx=%d has no registered callback\n", irq_idx);
- DPU_EVT32_IRQ(irq_idx, atomic_read(
- &dpu_kms->irq_obj.enable_counts[irq_idx]),
- DPU_EVTLOG_ERROR);
+ DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
+ atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
}
atomic_inc(&irq_obj->irq_counts[irq_idx]);
@@ -80,7 +79,7 @@ int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
{
unsigned long irq_flags;
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr ||
!dpu_kms->irq_obj.enable_counts ||
@@ -94,11 +93,10 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
ret = dpu_kms->hw_intr->ops.enable_irq(
dpu_kms->hw_intr,
@@ -130,11 +128,8 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
}
counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
- if (counts) {
- DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n",
- __builtin_return_address(0), irq_idxs[0], counts);
- DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR);
- }
+ if (counts)
+ DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
for (i = 0; (i < irq_count) && !ret; i++)
ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
@@ -149,7 +144,7 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
*/
static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
{
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
DPU_ERROR("invalid params\n");
@@ -161,11 +156,10 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
ret = dpu_kms->hw_intr->ops.disable_irq(
dpu_kms->hw_intr,
@@ -189,11 +183,8 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
}
counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
- if (counts == 2) {
- DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n",
- __builtin_return_address(0), irq_idxs[0], counts);
- DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR);
- }
+ if (counts == 2)
+ DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
for (i = 0; (i < irq_count) && !ret; i++)
ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
@@ -209,7 +200,7 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
*/
int dpu_core_irq_disable_nolock(struct dpu_kms *dpu_kms, int irq_idx)
{
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
DPU_ERROR("invalid params\n");
@@ -221,11 +212,10 @@ int dpu_core_irq_disable_nolock(struct dpu_kms *dpu_kms, int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_disable_nolock(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
ret = dpu_kms->hw_intr->ops.disable_irq_nolock(
dpu_kms->hw_intr,
@@ -297,7 +287,7 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx,
DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
- DPU_EVT32(irq_idx, register_irq_cb);
+ trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb);
list_del_init(®ister_irq_cb->list);
list_add_tail(®ister_irq_cb->list,
&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
@@ -332,7 +322,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx,
DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
- DPU_EVT32(irq_idx, register_irq_cb);
+ trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
list_del_init(®ister_irq_cb->list);
/* empty callback list but interrupt is still enabled */
if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) &&
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 9d044f5ce26e..ee41db86a2e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -966,6 +966,56 @@ TRACE_EVENT(dpu_pp_connect_ext_te,
TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
);
+DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
+ TP_PROTO(int irq_idx, int enable_count),
+ TP_ARGS(irq_idx, enable_count),
+ TP_STRUCT__entry(
+ __field( int, irq_idx )
+ __field( int, enable_count )
+ ),
+ TP_fast_assign(
+ __entry->irq_idx = irq_idx;
+ __entry->enable_count = enable_count;
+ ),
+ TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
+ __entry->enable_count)
+);
+DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
+ TP_PROTO(int irq_idx, int enable_count),
+ TP_ARGS(irq_idx, enable_count)
+);
+DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
+ TP_PROTO(int irq_idx, int enable_count),
+ TP_ARGS(irq_idx, enable_count)
+);
+DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_nolock,
+ TP_PROTO(int irq_idx, int enable_count),
+ TP_ARGS(irq_idx, enable_count)
+);
+
+DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
+ TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
+ TP_ARGS(irq_idx, callback),
+ TP_STRUCT__entry(
+ __field( int, irq_idx )
+ __field( struct dpu_irq_callback *, callback)
+ ),
+ TP_fast_assign(
+ __entry->irq_idx = irq_idx;
+ __entry->callback = callback;
+ ),
+ TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx,
+ __entry->callback)
+);
+DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback,
+ TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
+ TP_ARGS(irq_idx, callback)
+);
+DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback,
+ TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
+ TP_ARGS(irq_idx, callback)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 11/19] drm/msm: dpu_core_perf: Replace DPU_EVT with tracepoints
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (9 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 10/19] drm/msm: dpu_core_irq: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-12-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 12/19] drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR Sean Paul
` (7 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This patch converts all DPU_EVTs in dpu_core_perf with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 17 +++++++++++++++++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 6c0f66cc177f..1019ce7594ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -474,7 +474,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
if (update_clk) {
clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
- DPU_EVT32(kms->dev, stop_req, clk_rate);
+ trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);
ret = _dpu_core_perf_set_core_clk_rate(kms, clk_rate);
if (ret) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index ee41db86a2e9..d6f117bdad24 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -1016,6 +1016,23 @@ DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback,
TP_ARGS(irq_idx, callback)
);
+TRACE_EVENT(dpu_core_perf_update_clk,
+ TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
+ TP_ARGS(dev, stop_req, clk_rate),
+ TP_STRUCT__entry(
+ __field( struct drm_device *, dev )
+ __field( bool, stop_req )
+ __field( u64, clk_rate )
+ ),
+ TP_fast_assign(
+ __entry->dev = dev;
+ __entry->stop_req = stop_req;
+ __entry->clk_rate = clk_rate;
+ ),
+ TP_printk("dev:%s stop_req:%s clk_rate:%llu", __entry->dev->unique,
+ __entry->stop_req ? "true" : "false", __entry->clk_rate)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 12/19] drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (10 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 11/19] drm/msm: dpu_core_perf: " Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-13-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 13/19] drm/msm: dpu: Remove dpu evtlog Sean Paul
` (6 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
The events are only issued in error cases, so use DRM_ERROR instead.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 04accdf483c0..5c69c2cc5d10 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -33,13 +33,14 @@ static irqreturn_t dpu_mdss_irq(int irq, void *arg)
mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
hwirq);
if (mapping == 0) {
- DPU_EVT32(hwirq, DPU_EVTLOG_ERROR);
+ DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
return IRQ_NONE;
}
rc = generic_handle_irq(mapping);
if (rc < 0) {
- DPU_EVT32(hwirq, mapping, rc, DPU_EVTLOG_ERROR);
+ DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
+ hwirq, mapping, rc);
return IRQ_NONE;
}
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 13/19] drm/msm: dpu: Remove dpu evtlog
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (11 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 12/19] drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
[not found] ` <20180620204841.56354-14-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-06-20 20:48 ` [DPU PATCH 14/19] drm/msm: dpu_dbg: Remove dump_all option for dumping registers Sean Paul
` (5 subsequent siblings)
18 siblings, 1 reply; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
Now that everything has been converted to tracepoints, remove the dpu
evtlog.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 33 ---
drivers/gpu/drm/msm/dpu_dbg.c | 147 +----------
drivers/gpu/drm/msm/dpu_dbg.h | 224 +---------------
drivers/gpu/drm/msm/dpu_dbg_evtlog.c | 306 ----------------------
6 files changed, 11 insertions(+), 705 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg_evtlog.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index dc56904367d8..9c182a9dab2b 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -75,7 +75,6 @@ msm-y := \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
- dpu_dbg_evtlog.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 6ae5bba21074..4fd5e1d7261e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -43,11 +43,6 @@ static const char * const iommu_ports[] = {
"mdp_0",
};
-/**
- * Controls size of event log buffer. Specified as a power of 2.
- */
-#define DPU_EVTLOG_SIZE 1024
-
/*
* To enable overall DRM driver logging
* # echo 0x2 > /sys/module/drm/parameters/debug
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index d6f117bdad24..41fd6a227d8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -165,39 +165,6 @@ TRACE_EVENT(dpu_trace_counter,
__get_str(counter_name), __entry->value)
)
-#define DPU_TRACE_EVTLOG_SIZE 15
-TRACE_EVENT(dpu_evtlog,
- TP_PROTO(const char *tag, u32 tag_id, u32 cnt, u32 data[]),
- TP_ARGS(tag, tag_id, cnt, data),
- TP_STRUCT__entry(
- __field(int, pid)
- __string(evtlog_tag, tag)
- __field(u32, tag_id)
- __array(u32, data, DPU_TRACE_EVTLOG_SIZE)
- ),
- TP_fast_assign(
- __entry->pid = current->tgid;
- __assign_str(evtlog_tag, tag);
- __entry->tag_id = tag_id;
- if (cnt > DPU_TRACE_EVTLOG_SIZE)
- cnt = DPU_TRACE_EVTLOG_SIZE;
- memcpy(__entry->data, data, cnt * sizeof(u32));
- memset(&__entry->data[cnt], 0,
- (DPU_TRACE_EVTLOG_SIZE - cnt) * sizeof(u32));
- ),
- TP_printk("%d|%s:%d|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x",
- __entry->pid, __get_str(evtlog_tag),
- __entry->tag_id,
- __entry->data[0], __entry->data[1],
- __entry->data[2], __entry->data[3],
- __entry->data[4], __entry->data[5],
- __entry->data[6], __entry->data[7],
- __entry->data[8], __entry->data[9],
- __entry->data[10], __entry->data[11],
- __entry->data[12], __entry->data[13],
- __entry->data[14])
-)
-
TRACE_EVENT(dpu_perf_crtc_update,
TP_PROTO(u32 crtc, u64 bw_ctl_mnoc, u64 bw_ctl_llcc,
u64 bw_ctl_ebi, u32 core_clk_rate,
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 27538bc6c290..9495a0f17f1b 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -165,7 +165,6 @@ struct dpu_dbg_vbif_debug_bus {
/**
* struct dpu_dbg_base - global dpu debug base structure
- * @evtlog: event log instance
* @reg_base_list: list of register dumping regions
* @dev: device pointer
* @req_dump_blks: list of blocks requested for dumping
@@ -179,7 +178,6 @@ struct dpu_dbg_vbif_debug_bus {
* @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
- struct dpu_dbg_evtlog *evtlog;
struct list_head reg_base_list;
struct device *dev;
@@ -196,9 +194,6 @@ static struct dpu_dbg_base {
bool dsi_dbg_bus;
} dpu_dbg_base;
-/* dpu_dbg_base_evtlog - global pointer to main dpu event log for macro use */
-struct dpu_dbg_evtlog *dpu_dbg_base_evtlog;
-
static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
struct dpu_debug_bus_entry *entry, u32 val)
{
@@ -2526,8 +2521,6 @@ static void _dpu_dump_array(struct dpu_dbg_reg_base *blk_arr[],
{
int i;
- dpu_evtlog_dump_all(dpu_dbg_base.evtlog);
-
if (dump_all || !blk_arr || !len) {
_dpu_dump_reg_all();
} else {
@@ -2556,7 +2549,7 @@ static void _dpu_dump_work(struct work_struct *work)
{
_dpu_dump_array(dpu_dbg_base.req_dump_blks,
ARRAY_SIZE(dpu_dbg_base.req_dump_blks),
- dpu_dbg_base.work_panic, "evtlog_workitem",
+ dpu_dbg_base.work_panic, "dpudump_workitem",
dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work,
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work,
dpu_dbg_base.dump_all);
@@ -2564,7 +2557,7 @@ static void _dpu_dump_work(struct work_struct *work)
void dpu_dbg_dump(bool queue_work, const char *name, ...)
{
- int i, index = 0;
+ int index = 0;
bool do_panic = false;
bool dump_dbgbus_dpu = false;
bool dump_dbgbus_vbif_rt = false;
@@ -2575,9 +2568,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
struct dpu_dbg_reg_base **blk_arr;
u32 blk_len;
- if (!dpu_evtlog_is_enabled(dpu_dbg_base.evtlog, DPU_EVTLOG_ALWAYS))
- return;
-
if (queue_work && work_pending(&dpu_dbg_base.dump_work))
return;
@@ -2589,12 +2579,7 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
dpu_dbg_base.dump_all = false;
va_start(args, name);
- i = 0;
while ((blk_name = va_arg(args, char*))) {
- if (i++ >= DPU_EVTLOG_MAX_DATA) {
- pr_err("could not parse all dump arguments\n");
- break;
- }
if (IS_ERR_OR_NULL(blk_name))
break;
@@ -2641,7 +2626,7 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
}
/*
- * dpu_dbg_debugfs_open - debugfs open handler for evtlog dump
+ * dpu_dbg_debugfs_open - debugfs open handler for debug dump
* @inode: debugfs inode
* @file: file handle
*/
@@ -2654,35 +2639,13 @@ static int dpu_dbg_debugfs_open(struct inode *inode, struct file *file)
}
/**
- * dpu_evtlog_dump_read - debugfs read handler for evtlog dump
- * @file: file handler
- * @buff: user buffer content for debugfs
- * @count: size of user buffer
- * @ppos: position offset of user buffer
- */
-static ssize_t dpu_evtlog_dump_read(struct file *file, char __user *buff,
- size_t count, loff_t *ppos)
-{
- ssize_t len = 0;
- char evtlog_buf[DPU_EVTLOG_BUF_MAX];
-
- len = dpu_evtlog_dump_to_buffer(dpu_dbg_base.evtlog, evtlog_buf,
- DPU_EVTLOG_BUF_MAX);
- if (copy_to_user(buff, evtlog_buf, len))
- return -EFAULT;
- *ppos += len;
-
- return len;
-}
-
-/**
- * dpu_evtlog_dump_write - debugfs write handler for evtlog dump
+ * dpu_dbg_dump_write - debugfs write handler for debug dump
* @file: file handler
* @user_buf: user buffer content from debugfs
* @count: size of user buffer
* @ppos: position offset of user buffer
*/
-static ssize_t dpu_evtlog_dump_write(struct file *file,
+static ssize_t dpu_dbg_dump_write(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
{
_dpu_dump_array(NULL, 0, dpu_dbg_base.panic_on_err, "dump_debugfs",
@@ -2691,86 +2654,9 @@ static ssize_t dpu_evtlog_dump_write(struct file *file,
return count;
}
-static const struct file_operations dpu_evtlog_fops = {
+static const struct file_operations dpu_dbg_dump_fops = {
.open = dpu_dbg_debugfs_open,
- .read = dpu_evtlog_dump_read,
- .write = dpu_evtlog_dump_write,
-};
-
-/*
- * dpu_evtlog_filter_show - read callback for evtlog filter
- * @s: pointer to seq_file object
- * @data: pointer to private data
- */
-static int dpu_evtlog_filter_show(struct seq_file *s, void *data)
-{
- struct dpu_dbg_evtlog *evtlog;
- char buffer[64];
- int i;
-
- if (!s || !s->private)
- return -EINVAL;
-
- evtlog = s->private;
-
- for (i = 0; !dpu_evtlog_get_filter(
- evtlog, i, buffer, ARRAY_SIZE(buffer)); ++i)
- seq_printf(s, "*%s*\n", buffer);
- return 0;
-}
-
-/*
- * dpu_evtlog_filter_open - debugfs open handler for evtlog filter
- * @inode: debugfs inode
- * @file: file handle
- * Returns: zero on success
- */
-static int dpu_evtlog_filter_open(struct inode *inode, struct file *file)
-{
- if (!file)
- return -EINVAL;
-
- return single_open(file, dpu_evtlog_filter_show, inode->i_private);
-}
-
-/*
- * dpu_evtlog_filter_write - write callback for evtlog filter
- * @file: pointer to file structure
- * @user_buf: pointer to incoming user data
- * @count: size of incoming user buffer
- * @ppos: pointer to file offset
- */
-static ssize_t dpu_evtlog_filter_write(struct file *file,
- const char __user *user_buf, size_t count, loff_t *ppos)
-{
- char *tmp_filter = NULL;
- ssize_t rc = 0;
-
- if (count > 0) {
- /* copy user provided string and null terminate it */
- tmp_filter = kzalloc(count + 1, GFP_KERNEL);
- if (!tmp_filter)
- rc = -ENOMEM;
- else if (copy_from_user(tmp_filter, user_buf, count))
- rc = -EFAULT;
- }
-
- /* update actual filter configuration on success */
- if (!rc) {
- dpu_evtlog_set_filter(dpu_dbg_base.evtlog, tmp_filter);
- rc = count;
- }
- kfree(tmp_filter);
-
- return rc;
-}
-
-static const struct file_operations dpu_evtlog_filter_fops = {
- .open = dpu_evtlog_filter_open,
- .write = dpu_evtlog_filter_write,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release
+ .write = dpu_dbg_dump_write,
};
/**
@@ -3018,12 +2904,7 @@ int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
return -EINVAL;
debugfs_create_file("dump", 0600, debugfs_root, NULL,
- &dpu_evtlog_fops);
- debugfs_create_u32("enable", 0600, debugfs_root,
- &(dpu_dbg_base.evtlog->enable));
- debugfs_create_file("filter", 0600, debugfs_root,
- dpu_dbg_base.evtlog,
- &dpu_evtlog_filter_fops);
+ &dpu_dbg_dump_fops);
debugfs_create_u32("panic", 0600, debugfs_root,
&dpu_dbg_base.panic_on_err);
debugfs_create_u32("reg_dump", 0600, debugfs_root,
@@ -3106,19 +2987,12 @@ int dpu_dbg_init(struct device *dev)
INIT_LIST_HEAD(&dpu_dbg_base.reg_base_list);
dpu_dbg_base.dev = dev;
- dpu_dbg_base.evtlog = dpu_evtlog_init();
- if (IS_ERR_OR_NULL(dpu_dbg_base.evtlog))
- return PTR_ERR(dpu_dbg_base.evtlog);
-
- dpu_dbg_base_evtlog = dpu_dbg_base.evtlog;
-
INIT_WORK(&dpu_dbg_base.dump_work, _dpu_dump_work);
dpu_dbg_base.work_panic = false;
dpu_dbg_base.panic_on_err = DEFAULT_PANIC;
dpu_dbg_base.enable_reg_dump = DEFAULT_REGDUMP;
- pr_info("evtlog_status: enable:%d, panic:%d, dump:%d\n",
- dpu_dbg_base.evtlog->enable, dpu_dbg_base.panic_on_err,
+ pr_info("debug_status: panic:%d, dump:%d\n", dpu_dbg_base.panic_on_err,
dpu_dbg_base.enable_reg_dump);
return 0;
@@ -3150,9 +3024,6 @@ static void dpu_dbg_reg_base_destroy(void)
void dpu_dbg_destroy(void)
{
_dpu_dbg_debugfs_destroy();
- dpu_dbg_base_evtlog = NULL;
- dpu_evtlog_destroy(dpu_dbg_base.evtlog);
- dpu_dbg_base.evtlog = NULL;
dpu_dbg_reg_base_destroy();
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h
index 283dbbc00690..052c78d5b4f5 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/dpu_dbg.h
@@ -17,109 +17,11 @@
#include <linux/debugfs.h>
#include <linux/list.h>
-#define DPU_EVTLOG_DATA_LIMITER (-1)
-#define DPU_EVTLOG_FUNC_ENTRY 0x1111
-#define DPU_EVTLOG_FUNC_EXIT 0x2222
-#define DPU_EVTLOG_FUNC_CASE1 0x3333
-#define DPU_EVTLOG_FUNC_CASE2 0x4444
-#define DPU_EVTLOG_FUNC_CASE3 0x5555
-#define DPU_EVTLOG_FUNC_CASE4 0x6666
-#define DPU_EVTLOG_FUNC_CASE5 0x7777
-#define DPU_EVTLOG_FUNC_CASE6 0x8888
-#define DPU_EVTLOG_FUNC_CASE7 0x9999
-#define DPU_EVTLOG_FUNC_CASE8 0xaaaa
-#define DPU_EVTLOG_FUNC_CASE9 0xbbbb
-#define DPU_EVTLOG_FUNC_CASE10 0xcccc
-#define DPU_EVTLOG_PANIC 0xdead
-#define DPU_EVTLOG_FATAL 0xbad
-#define DPU_EVTLOG_ERROR 0xebad
-
-#define DPU_DBG_DUMP_DATA_LIMITER (NULL)
-
-enum dpu_dbg_evtlog_flag {
- DPU_EVTLOG_CRITICAL = BIT(0),
- DPU_EVTLOG_IRQ = BIT(1),
- DPU_EVTLOG_VERBOSE = BIT(2),
- DPU_EVTLOG_ALWAYS = -1
-};
-
enum dpu_dbg_dump_flag {
DPU_DBG_DUMP_IN_LOG = BIT(0),
DPU_DBG_DUMP_IN_MEM = BIT(1),
};
-#ifdef CONFIG_DRM_DPU_EVTLOG_DEBUG
-#define DPU_EVTLOG_DEFAULT_ENABLE (DPU_EVTLOG_CRITICAL | DPU_EVTLOG_IRQ)
-#else
-#define DPU_EVTLOG_DEFAULT_ENABLE 0
-#endif
-
-/*
- * evtlog will print this number of entries when it is called through
- * sysfs node or panic. This prevents kernel log from evtlog message
- * flood.
- */
-#define DPU_EVTLOG_PRINT_ENTRY 256
-
-/*
- * evtlog keeps this number of entries in memory for debug purpose. This
- * number must be greater than print entry to prevent out of bound evtlog
- * entry array access.
- */
-#define DPU_EVTLOG_ENTRY (DPU_EVTLOG_PRINT_ENTRY * 4)
-#define DPU_EVTLOG_MAX_DATA 15
-#define DPU_EVTLOG_BUF_MAX 512
-#define DPU_EVTLOG_BUF_ALIGN 32
-
-struct dpu_dbg_evtlog_log {
- s64 time;
- const char *name;
- int line;
- u32 data[DPU_EVTLOG_MAX_DATA];
- u32 data_cnt;
- int pid;
-};
-
-/**
- * @filter_list: Linked list of currently active filter strings
- */
-struct dpu_dbg_evtlog {
- struct dpu_dbg_evtlog_log logs[DPU_EVTLOG_ENTRY];
- u32 first;
- u32 last;
- u32 curr;
- u32 next;
- u32 enable;
- spinlock_t spin_lock;
- struct list_head filter_list;
-};
-
-extern struct dpu_dbg_evtlog *dpu_dbg_base_evtlog;
-
-/**
- * DPU_EVT32 - Write a list of 32bit values to the event log, default area
- * ... - variable arguments
- */
-#define DPU_EVT32(...) dpu_evtlog_log(dpu_dbg_base_evtlog, __func__, \
- __LINE__, DPU_EVTLOG_ALWAYS, ##__VA_ARGS__, \
- DPU_EVTLOG_DATA_LIMITER)
-
-/**
- * DPU_EVT32_VERBOSE - Write a list of 32bit values for verbose event logging
- * ... - variable arguments
- */
-#define DPU_EVT32_VERBOSE(...) dpu_evtlog_log(dpu_dbg_base_evtlog, __func__, \
- __LINE__, DPU_EVTLOG_VERBOSE, ##__VA_ARGS__, \
- DPU_EVTLOG_DATA_LIMITER)
-
-/**
- * DPU_EVT32_IRQ - Write a list of 32bit values to the event log, IRQ area
- * ... - variable arguments
- */
-#define DPU_EVT32_IRQ(...) dpu_evtlog_log(dpu_dbg_base_evtlog, __func__, \
- __LINE__, DPU_EVTLOG_IRQ, ##__VA_ARGS__, \
- DPU_EVTLOG_DATA_LIMITER)
-
/**
* DPU_DBG_DUMP - trigger dumping of all dpu_dbg facilities
* @va_args: list of named register dump ranges and regions to dump, as
@@ -128,74 +30,10 @@ extern struct dpu_dbg_evtlog *dpu_dbg_base_evtlog;
* Including the special name "panic" will trigger a panic after
* the dumping work has completed.
*/
-#define DPU_DBG_DUMP(...) dpu_dbg_dump(false, __func__, ##__VA_ARGS__, \
- DPU_DBG_DUMP_DATA_LIMITER)
-
-/**
- * DPU_DBG_DUMP_WQ - trigger dumping of all dpu_dbg facilities, queuing the work
- * @va_args: list of named register dump ranges and regions to dump, as
- * registered previously through dpu_dbg_reg_register_base and
- * dpu_dbg_reg_register_dump_range.
- * Including the special name "panic" will trigger a panic after
- * the dumping work has completed.
- */
-#define DPU_DBG_DUMP_WQ(...) dpu_dbg_dump(true, __func__, ##__VA_ARGS__, \
- DPU_DBG_DUMP_DATA_LIMITER)
+#define DPU_DBG_DUMP(...) dpu_dbg_dump(false, __func__, ##__VA_ARGS__, NULL)
#if defined(CONFIG_DEBUG_FS)
-/**
- * dpu_evtlog_init - allocate a new event log object
- * Returns: evtlog or -ERROR
- */
-struct dpu_dbg_evtlog *dpu_evtlog_init(void);
-
-/**
- * dpu_evtlog_destroy - destroy previously allocated event log
- * @evtlog: pointer to evtlog
- * Returns: none
- */
-void dpu_evtlog_destroy(struct dpu_dbg_evtlog *evtlog);
-
-/**
- * dpu_evtlog_log - log an entry into the event log.
- * log collection may be enabled/disabled entirely via debugfs
- * log area collection may be filtered by user provided flags via debugfs.
- * @evtlog: pointer to evtlog
- * @name: function name of call site
- * @line: line number of call site
- * @flag: log area filter flag checked against user's debugfs request
- * Returns: none
- */
-void dpu_evtlog_log(struct dpu_dbg_evtlog *evtlog, const char *name, int line,
- int flag, ...);
-
-/**
- * dpu_evtlog_dump_all - print all entries in event log to kernel log
- * @evtlog: pointer to evtlog
- * Returns: none
- */
-void dpu_evtlog_dump_all(struct dpu_dbg_evtlog *evtlog);
-
-/**
- * dpu_evtlog_is_enabled - check whether log collection is enabled for given
- * event log and log area flag
- * @evtlog: pointer to evtlog
- * @flag: log area filter flag
- * Returns: none
- */
-bool dpu_evtlog_is_enabled(struct dpu_dbg_evtlog *evtlog, u32 flag);
-
-/**
- * dpu_evtlog_dump_to_buffer - print content of event log to the given buffer
- * @evtlog: pointer to evtlog
- * @evtlog_buf: target buffer to print into
- * @evtlog_buf_size: size of target buffer
- * Returns: number of bytes written to buffer
- */
-ssize_t dpu_evtlog_dump_to_buffer(struct dpu_dbg_evtlog *evtlog,
- char *evtlog_buf, ssize_t evtlog_buf_size);
-
/**
* dpu_dbg_init_dbg_buses - initialize debug bus dumping support for the chipset
* @hwversion: Chipset revision
@@ -203,7 +41,7 @@ ssize_t dpu_evtlog_dump_to_buffer(struct dpu_dbg_evtlog *evtlog,
void dpu_dbg_init_dbg_buses(u32 hwversion);
/**
- * dpu_dbg_init - initialize global dpu debug facilities: evtlog, regdump
+ * dpu_dbg_init - initialize global dpu debug facilities: regdump
* @dev: device handle
* Returns: 0 or -ERROR
*/
@@ -289,24 +127,6 @@ void dpu_dbg_reg_register_dump_range(const char *base_name,
*/
void dpu_dbg_set_dpu_top_offset(u32 blk_off);
-/**
- * dpu_evtlog_set_filter - update evtlog filtering
- * @evtlog: pointer to evtlog
- * @filter: pointer to optional function name filter, set to NULL to disable
- */
-void dpu_evtlog_set_filter(struct dpu_dbg_evtlog *evtlog, char *filter);
-
-/**
- * dpu_evtlog_get_filter - query configured evtlog filters
- * @evtlog: pointer to evtlog
- * @index: filter index to retrieve
- * @buf: pointer to output filter buffer
- * @bufsz: size of output filter buffer
- * Returns: zero if a filter string was returned
- */
-int dpu_evtlog_get_filter(struct dpu_dbg_evtlog *evtlog, int index,
- char *buf, size_t bufsz);
-
/**
* dsi_ctrl_debug_dump - dump dsi debug dump status
*/
@@ -317,35 +137,6 @@ static inline void dsi_ctrl_debug_dump(void) {}
#endif
#else
-static inline struct dpu_dbg_evtlog *dpu_evtlog_init(void)
-{
- return NULL;
-}
-
-static inline void dpu_evtlog_destroy(struct dpu_dbg_evtlog *evtlog)
-{
-}
-
-static inline void dpu_evtlog_log(struct dpu_dbg_evtlog *evtlog,
- const char *name, int line, int flag, ...)
-{
-}
-
-static inline void dpu_evtlog_dump_all(struct dpu_dbg_evtlog *evtlog)
-{
-}
-
-static inline bool dpu_evtlog_is_enabled(struct dpu_dbg_evtlog *evtlog,
- u32 flag)
-{
- return false;
-}
-
-static inline ssize_t dpu_evtlog_dump_to_buffer(struct dpu_dbg_evtlog *evtlog,
- char *evtlog_buf, ssize_t evtlog_buf_size)
-{
- return 0;
-}
static inline void dpu_dbg_init_dbg_buses(u32 hwversion)
{
@@ -385,17 +176,6 @@ void dpu_dbg_set_dpu_top_offset(u32 blk_off)
{
}
-static inline void dpu_evtlog_set_filter(
- struct dpu_dbg_evtlog *evtlog, char *filter)
-{
-}
-
-static inline int dpu_evtlog_get_filter(struct dpu_dbg_evtlog *evtlog,
- int index, char *buf, size_t bufsz)
-{
- return -EINVAL;
-}
-
static inline void dsi_ctrl_debug_dump(void)
{
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg_evtlog.c b/drivers/gpu/drm/msm/dpu_dbg_evtlog.c
deleted file mode 100644
index ef132c015a7e..000000000000
--- a/drivers/gpu/drm/msm/dpu_dbg_evtlog.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt) "dpu_dbg:[%s] " fmt, __func__
-
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/ktime.h>
-#include <linux/debugfs.h>
-#include <linux/uaccess.h>
-#include <linux/dma-buf.h>
-#include <linux/slab.h>
-
-#include "dpu_dbg.h"
-#include "dpu_trace.h"
-
-#define DPU_EVTLOG_FILTER_STRSIZE 64
-
-struct dpu_evtlog_filter {
- struct list_head list;
- char filter[DPU_EVTLOG_FILTER_STRSIZE];
-};
-
-static bool _dpu_evtlog_is_filtered_no_lock(
- struct dpu_dbg_evtlog *evtlog, const char *str)
-{
- struct dpu_evtlog_filter *filter_node;
- bool rc;
-
- if (!str)
- return true;
-
- /*
- * Filter the incoming string IFF the list is not empty AND
- * a matching entry is not in the list.
- */
- rc = !list_empty(&evtlog->filter_list);
- list_for_each_entry(filter_node, &evtlog->filter_list, list)
- if (strnstr(str, filter_node->filter,
- DPU_EVTLOG_FILTER_STRSIZE - 1)) {
- rc = false;
- break;
- }
-
- return rc;
-}
-
-bool dpu_evtlog_is_enabled(struct dpu_dbg_evtlog *evtlog, u32 flag)
-{
- return evtlog && (evtlog->enable & flag);
-}
-
-void dpu_evtlog_log(struct dpu_dbg_evtlog *evtlog, const char *name, int line,
- int flag, ...)
-{
- unsigned long flags;
- int i, val = 0;
- va_list args;
- struct dpu_dbg_evtlog_log *log;
-
- if (!evtlog)
- return;
-
- if (!dpu_evtlog_is_enabled(evtlog, flag))
- return;
-
- spin_lock_irqsave(&evtlog->spin_lock, flags);
-
- if (_dpu_evtlog_is_filtered_no_lock(evtlog, name))
- goto exit;
-
- log = &evtlog->logs[evtlog->curr];
- log->time = ktime_to_us(ktime_get());
- log->name = name;
- log->line = line;
- log->data_cnt = 0;
- log->pid = current->pid;
-
- va_start(args, flag);
- for (i = 0; i < DPU_EVTLOG_MAX_DATA; i++) {
-
- val = va_arg(args, int);
- if (val == DPU_EVTLOG_DATA_LIMITER)
- break;
-
- log->data[i] = val;
- }
- va_end(args);
- log->data_cnt = i;
- evtlog->curr = (evtlog->curr + 1) % DPU_EVTLOG_ENTRY;
- evtlog->last++;
-
- trace_dpu_evtlog(name, line, log->data_cnt, log->data);
-exit:
- spin_unlock_irqrestore(&evtlog->spin_lock, flags);
-}
-
-/* always dump the last entries which are not dumped yet */
-static bool _dpu_evtlog_dump_calc_range(struct dpu_dbg_evtlog *evtlog)
-{
- if (!evtlog)
- return false;
-
- evtlog->first = evtlog->next;
-
- if (evtlog->last == evtlog->first)
- return false;
-
- if (evtlog->last < evtlog->first) {
- evtlog->first %= DPU_EVTLOG_ENTRY;
- if (evtlog->last < evtlog->first)
- evtlog->last += DPU_EVTLOG_ENTRY;
- }
-
- if ((evtlog->last - evtlog->first) > DPU_EVTLOG_PRINT_ENTRY) {
- pr_info("evtlog skipping %d entries, last=%d\n",
- evtlog->last - evtlog->first - DPU_EVTLOG_PRINT_ENTRY,
- evtlog->last - 1);
- evtlog->first = evtlog->last - DPU_EVTLOG_PRINT_ENTRY;
- }
- evtlog->next = evtlog->first + 1;
-
- return true;
-}
-
-ssize_t dpu_evtlog_dump_to_buffer(struct dpu_dbg_evtlog *evtlog,
- char *evtlog_buf, ssize_t evtlog_buf_size)
-{
- int i;
- ssize_t off = 0;
- struct dpu_dbg_evtlog_log *log, *prev_log;
- unsigned long flags;
-
- if (!evtlog || !evtlog_buf)
- return 0;
-
- spin_lock_irqsave(&evtlog->spin_lock, flags);
-
- /* update markers, exit if nothing to print */
- if (!_dpu_evtlog_dump_calc_range(evtlog))
- goto exit;
-
- log = &evtlog->logs[evtlog->first % DPU_EVTLOG_ENTRY];
-
- prev_log = &evtlog->logs[(evtlog->first - 1) % DPU_EVTLOG_ENTRY];
-
- off = snprintf((evtlog_buf + off), (evtlog_buf_size - off), "%s:%-4d",
- log->name, log->line);
-
- if (off < DPU_EVTLOG_BUF_ALIGN) {
- memset((evtlog_buf + off), 0x20, (DPU_EVTLOG_BUF_ALIGN - off));
- off = DPU_EVTLOG_BUF_ALIGN;
- }
-
- off += snprintf((evtlog_buf + off), (evtlog_buf_size - off),
- "=>[%-8d:%-11llu:%9llu][%-4d]:", evtlog->first,
- log->time, (log->time - prev_log->time), log->pid);
-
- for (i = 0; i < log->data_cnt; i++)
- off += snprintf((evtlog_buf + off), (evtlog_buf_size - off),
- "%x ", log->data[i]);
-
- off += snprintf((evtlog_buf + off), (evtlog_buf_size - off), "\n");
-exit:
- spin_unlock_irqrestore(&evtlog->spin_lock, flags);
-
- return off;
-}
-
-void dpu_evtlog_dump_all(struct dpu_dbg_evtlog *evtlog)
-{
- char buf[DPU_EVTLOG_BUF_MAX];
-
- if (!evtlog)
- return;
-
- while (dpu_evtlog_dump_to_buffer(evtlog, buf, sizeof(buf)))
- pr_info("%s", buf);
-}
-
-struct dpu_dbg_evtlog *dpu_evtlog_init(void)
-{
- struct dpu_dbg_evtlog *evtlog;
-
- evtlog = kzalloc(sizeof(*evtlog), GFP_KERNEL);
- if (!evtlog)
- return ERR_PTR(-ENOMEM);
-
- spin_lock_init(&evtlog->spin_lock);
- evtlog->enable = DPU_EVTLOG_DEFAULT_ENABLE;
-
- INIT_LIST_HEAD(&evtlog->filter_list);
-
- return evtlog;
-}
-
-int dpu_evtlog_get_filter(struct dpu_dbg_evtlog *evtlog, int index,
- char *buf, size_t bufsz)
-{
- struct dpu_evtlog_filter *filter_node;
- unsigned long flags;
- int rc = -EFAULT;
-
- if (!evtlog || !buf || !bufsz || index < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&evtlog->spin_lock, flags);
- list_for_each_entry(filter_node, &evtlog->filter_list, list) {
- if (index--)
- continue;
-
- /* don't care about return value */
- (void)strlcpy(buf, filter_node->filter, bufsz);
- rc = 0;
- break;
- }
- spin_unlock_irqrestore(&evtlog->spin_lock, flags);
-
- return rc;
-}
-
-void dpu_evtlog_set_filter(struct dpu_dbg_evtlog *evtlog, char *filter)
-{
- struct dpu_evtlog_filter *filter_node, *tmp;
- struct list_head free_list;
- unsigned long flags;
- char *flt;
-
- if (!evtlog)
- return;
-
- INIT_LIST_HEAD(&free_list);
-
- /*
- * Clear active filter list and cache filter_nodes locally
- * to reduce memory fragmentation.
- */
- spin_lock_irqsave(&evtlog->spin_lock, flags);
- list_for_each_entry_safe(filter_node, tmp, &evtlog->filter_list, list) {
- list_del_init(&filter_node->list);
- list_add_tail(&filter_node->list, &free_list);
- }
- spin_unlock_irqrestore(&evtlog->spin_lock, flags);
-
- /*
- * Parse incoming filter request string and build up a new
- * filter list. New filter nodes are taken from the local
- * free list, if available, and allocated from the system
- * heap once the free list is empty.
- */
- while (filter && (flt = strsep(&filter, "|\r\n\t ")) != NULL) {
- if (!*flt)
- continue;
-
- if (list_empty(&free_list)) {
- filter_node = kzalloc(sizeof(*filter_node), GFP_KERNEL);
- if (!filter_node)
- break;
-
- INIT_LIST_HEAD(&filter_node->list);
- } else {
- filter_node = list_first_entry(&free_list,
- struct dpu_evtlog_filter, list);
- list_del_init(&filter_node->list);
- }
-
- /* don't care if copy truncated */
- (void)strlcpy(filter_node->filter, flt,
- DPU_EVTLOG_FILTER_STRSIZE);
-
- spin_lock_irqsave(&evtlog->spin_lock, flags);
- list_add_tail(&filter_node->list, &evtlog->filter_list);
- spin_unlock_irqrestore(&evtlog->spin_lock, flags);
- }
-
- /*
- * Free any unused filter_nodes back to the system.
- */
- list_for_each_entry_safe(filter_node, tmp, &free_list, list) {
- list_del(&filter_node->list);
- kfree(filter_node);
- }
-}
-
-void dpu_evtlog_destroy(struct dpu_dbg_evtlog *evtlog)
-{
- struct dpu_evtlog_filter *filter_node, *tmp;
-
- if (!evtlog)
- return;
-
- list_for_each_entry_safe(filter_node, tmp, &evtlog->filter_list, list) {
- list_del(&filter_node->list);
- kfree(filter_node);
- }
- kfree(evtlog);
-}
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 14/19] drm/msm: dpu_dbg: Remove dump_all option for dumping registers
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (12 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 13/19] drm/msm: dpu: Remove dpu evtlog Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
2018-06-20 20:48 ` [DPU PATCH 15/19] drm/msm: dpu: Remove arbitrary register dumps Sean Paul
` (4 subsequent siblings)
18 siblings, 0 replies; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This can be accomplished via /dev/mem
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 34 +++----------------
4 files changed, 7 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6aad40dccb05..5ff627827be9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index eb9314aaa85f..5589d1289da9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index fc83745b48fa..8ac7f0537c05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 9495a0f17f1b..813f6f3ff773 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -174,7 +174,6 @@ struct dpu_dbg_vbif_debug_bus {
* @enable_reg_dump: whether to dump registers into memory, kernel log, or both
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
- * @dump_all: dump all entries in register dump
* @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
@@ -190,7 +189,6 @@ static struct dpu_dbg_base {
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
- bool dump_all;
bool dsi_dbg_bus;
} dpu_dbg_base;
@@ -2207,22 +2205,6 @@ static void _dpu_dump_reg_by_blk(const char *blk_name)
}
}
-/**
- * _dpu_dump_reg_all - dump all register regions
- */
-static void _dpu_dump_reg_all(void)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *blk_base;
-
- if (!dbg_base)
- return;
-
- list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head)
- if (strlen(blk_base->name))
- _dpu_dump_reg_by_blk(blk_base->name);
-}
-
/**
* _dpu_dump_get_blk_addr - retrieve register block address by name
* @blk_name: register blk name
@@ -2517,13 +2499,11 @@ static void _dpu_dbg_dump_vbif_dbg_bus(struct dpu_dbg_vbif_debug_bus *bus)
*/
static void _dpu_dump_array(struct dpu_dbg_reg_base *blk_arr[],
u32 len, bool do_panic, const char *name, bool dump_dbgbus_dpu,
- bool dump_dbgbus_vbif_rt, bool dump_all)
+ bool dump_dbgbus_vbif_rt)
{
int i;
- if (dump_all || !blk_arr || !len) {
- _dpu_dump_reg_all();
- } else {
+ if (!blk_arr || !len) {
for (i = 0; i < len; i++) {
if (blk_arr[i] != NULL)
_dpu_dump_reg_by_ranges(blk_arr[i],
@@ -2551,8 +2531,7 @@ static void _dpu_dump_work(struct work_struct *work)
ARRAY_SIZE(dpu_dbg_base.req_dump_blks),
dpu_dbg_base.work_panic, "dpudump_workitem",
dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work,
- dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work,
- dpu_dbg_base.dump_all);
+ dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
void dpu_dbg_dump(bool queue_work, const char *name, ...)
@@ -2561,7 +2540,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
bool do_panic = false;
bool dump_dbgbus_dpu = false;
bool dump_dbgbus_vbif_rt = false;
- bool dump_all = false;
va_list args;
char *blk_name = NULL;
struct dpu_dbg_reg_base *blk_base = NULL;
@@ -2576,7 +2554,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
memset(dpu_dbg_base.req_dump_blks, 0,
sizeof(dpu_dbg_base.req_dump_blks));
- dpu_dbg_base.dump_all = false;
va_start(args, name);
while ((blk_name = va_arg(args, char*))) {
@@ -2594,9 +2571,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
}
}
- if (!strcmp(blk_name, "all"))
- dump_all = true;
-
if (!strcmp(blk_name, "dbg_bus"))
dump_dbgbus_dpu = true;
@@ -2621,7 +2595,7 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
schedule_work(&dpu_dbg_base.dump_work);
} else {
_dpu_dump_array(blk_arr, blk_len, do_panic, name,
- dump_dbgbus_dpu, dump_dbgbus_vbif_rt, dump_all);
+ dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
}
}
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 15/19] drm/msm: dpu: Remove arbitrary register dumps
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (13 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 14/19] drm/msm: dpu_dbg: Remove dump_all option for dumping registers Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
2018-06-20 20:48 ` [DPU PATCH 16/19] drm/msm: dpu: Remove panic from dpu debug dump Sean Paul
` (3 subsequent siblings)
18 siblings, 0 replies; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
This can be achieved via /dev/mem.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 -
drivers/gpu/drm/msm/dpu_dbg.c | 716 +-----------------
drivers/gpu/drm/msm/dpu_dbg.h | 59 --
10 files changed, 7 insertions(+), 822 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
index 24b0dbc76f3a..da6f0609be5f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
@@ -301,9 +301,6 @@ struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
goto blk_init_error;
}
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
/*
* Perform any default initialization for the chroma down module
* @setup default csc coefficients
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index ad02316fafce..06be7cf7ce50 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -524,9 +524,6 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
goto blk_init_error;
}
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
return c;
blk_init_error:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 7386d4643115..d280df5613c9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -332,9 +332,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
goto blk_init_error;
}
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
return c;
blk_init_error:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 5b4d529a1a89..4ab72b0f07a5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -245,9 +245,6 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
goto blk_init_error;
}
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
return c;
blk_init_error:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 12e90b8e5466..cc3a623903f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -234,9 +234,6 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
goto blk_init_error;
}
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
return c;
blk_init_error:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 6640906e4f03..2b3f5e88af98 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -734,20 +734,6 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
goto blk_init_error;
}
- if (!is_virtual_pipe)
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name,
- hw_pipe->hw.blk_off,
- hw_pipe->hw.blk_off + hw_pipe->hw.length,
- hw_pipe->hw.xin_id);
-
- if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME,
- cfg->sblk->scaler_blk.name,
- hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base,
- hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base +
- cfg->sblk->scaler_blk.len,
- hw_pipe->hw.xin_id);
-
return hw_pipe;
blk_init_error:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 115eeedd90e8..42fc72cf48dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -379,9 +379,6 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
goto blk_init_error;
}
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name,
- mdp->hw.blk_off, mdp->hw.blk_off + mdp->hw.length,
- mdp->hw.xin_id);
dpu_dbg_set_dpu_top_offset(mdp->hw.blk_off);
return mdp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 4fd5e1d7261e..3003176e731d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1417,11 +1417,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
dpu_kms->mmio_len = msm_iomap_size(dpu_kms->pdev, "mdp_phys");
- rc = dpu_dbg_reg_register_base(DPU_DBG_NAME, dpu_kms->mmio,
- dpu_kms->mmio_len);
- if (rc)
- DPU_ERROR("dbg base register kms failed: %d\n", rc);
-
dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif_phys",
"vbif_phys");
if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
@@ -1432,11 +1427,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
}
dpu_kms->vbif_len[VBIF_RT] = msm_iomap_size(dpu_kms->pdev,
"vbif_phys");
- rc = dpu_dbg_reg_register_base("vbif_rt", dpu_kms->vbif[VBIF_RT],
- dpu_kms->vbif_len[VBIF_RT]);
- if (rc)
- DPU_ERROR("dbg base register vbif_rt failed: %d\n", rc);
-
dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt_phys",
"vbif_nrt_phys");
if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
@@ -1445,12 +1435,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
} else {
dpu_kms->vbif_len[VBIF_NRT] = msm_iomap_size(dpu_kms->pdev,
"vbif_nrt_phys");
- rc = dpu_dbg_reg_register_base("vbif_nrt",
- dpu_kms->vbif[VBIF_NRT],
- dpu_kms->vbif_len[VBIF_NRT]);
- if (rc)
- DPU_ERROR("dbg base register vbif_nrt failed: %d\n",
- rc);
}
dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma_phys",
@@ -1461,12 +1445,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
} else {
dpu_kms->reg_dma_len = msm_iomap_size(dpu_kms->pdev,
"regdma_phys");
- rc = dpu_dbg_reg_register_base("reg_dma",
- dpu_kms->reg_dma,
- dpu_kms->reg_dma_len);
- if (rc)
- DPU_ERROR("dbg base register reg_dma failed: %d\n",
- rc);
}
dpu_kms->core_client = dpu_power_client_create(&dpu_kms->phandle,
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 813f6f3ff773..3572e3cbec6c 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -25,16 +25,10 @@
#include "dpu_dbg.h"
#include "disp/dpu1/dpu_hw_catalog.h"
-#define DPU_DBG_BASE_MAX 10
#define DEFAULT_PANIC 1
-#define DEFAULT_REGDUMP DPU_DBG_DUMP_IN_MEM
#define DEFAULT_DBGBUS_DPU DPU_DBG_DUMP_IN_MEM
#define DEFAULT_DBGBUS_VBIFRT DPU_DBG_DUMP_IN_MEM
-#define DEFAULT_BASE_REG_CNT 0x100
-#define GROUP_BYTES 4
-#define ROW_BYTES 16
-#define RANGE_NAME_LEN 40
#define REG_BASE_NAME_LEN 80
#define DBGBUS_FLAGS_DSPP BIT(0)
@@ -65,41 +59,11 @@
#define MMSS_VBIF_ERR_INFO_1 0x1a4
#define MMSS_VBIF_CLIENT_NUM 14
-/* print debug ranges in groups of 4 u32s */
-#define REG_DUMP_ALIGN 16
-
-/**
- * struct dpu_dbg_reg_offset - tracking for start and end of region
- * @start: start offset
- * @start: end offset
- */
-struct dpu_dbg_reg_offset {
- u32 start;
- u32 end;
-};
-
-/**
- * struct dpu_dbg_reg_range - register dumping named sub-range
- * @head: head of this node
- * @reg_dump: address for the mem dump
- * @range_name: name of this range
- * @offset: offsets for range to dump
- * @xin_id: client xin id
- */
-struct dpu_dbg_reg_range {
- struct list_head head;
- u32 *reg_dump;
- char range_name[RANGE_NAME_LEN];
- struct dpu_dbg_reg_offset offset;
- uint32_t xin_id;
-};
-
/**
* struct dpu_dbg_reg_base - register region base.
* may sub-ranges: sub-ranges are used for dumping
* or may not have sub-ranges: dumping is base -> max_offset
* @reg_base_head: head of this node
- * @sub_range_list: head to the list with dump ranges
* @name: register base name
* @base: base pointer
* @off: cached offset of region for manual register dumping
@@ -107,13 +71,11 @@ struct dpu_dbg_reg_range {
* @max_offset: length of region
* @buf: buffer used for manual register dumping
* @buf_len: buffer length used for manual register dumping
- * @reg_dump: address for the mem dump if no ranges used
* @cb: callback for external dump function, null if not defined
* @cb_ptr: private pointer to callback function
*/
struct dpu_dbg_reg_base {
struct list_head reg_base_head;
- struct list_head sub_range_list;
char name[REG_BASE_NAME_LEN];
void __iomem *base;
size_t off;
@@ -121,7 +83,6 @@ struct dpu_dbg_reg_base {
size_t max_offset;
char *buf;
size_t buf_len;
- u32 *reg_dump;
void (*cb)(void *ptr);
void *cb_ptr;
};
@@ -167,11 +128,9 @@ struct dpu_dbg_vbif_debug_bus {
* struct dpu_dbg_base - global dpu debug base structure
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @req_dump_blks: list of blocks requested for dumping
* @panic_on_err: whether to kernel panic after triggering dump via debugfs
* @dump_work: work struct for deferring register dump work to separate thread
* @work_panic: panic after dump if internal user passed "panic" special region
- * @enable_reg_dump: whether to dump registers into memory, kernel log, or both
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
* @dsi_dbg_bus: dump dsi debug bus register
@@ -180,12 +139,9 @@ static struct dpu_dbg_base {
struct list_head reg_base_list;
struct device *dev;
- struct dpu_dbg_reg_base *req_dump_blks[DPU_DBG_BASE_MAX];
-
u32 panic_on_err;
struct work_struct dump_work;
bool work_panic;
- u32 enable_reg_dump;
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
@@ -2006,222 +1962,6 @@ static inline void _dpu_dbg_enable_power(int enable)
pm_runtime_put_sync(dpu_dbg_base.dev);
}
-/**
- * _dpu_dump_reg - helper function for dumping rotator register set content
- * @dump_name: register set name
- * @reg_dump_flag: dumping flag controlling in-log/memory dump location
- * @base_addr: starting address of io region for calculating offsets to print
- * @addr: starting address offset for dumping
- * @len_bytes: range of the register set
- * @dump_mem: output buffer for memory dump location option
- * @from_isr: whether being called from isr context
- */
-static void _dpu_dump_reg(const char *dump_name, u32 reg_dump_flag,
- char *base_addr, char *addr, size_t len_bytes, u32 **dump_mem,
- bool from_isr)
-{
- u32 in_log, in_mem, len_align, len_padded;
- u32 *dump_addr = NULL;
- char *end_addr;
- int i;
-
- if (!len_bytes)
- return;
-
- in_log = (reg_dump_flag & DPU_DBG_DUMP_IN_LOG);
- in_mem = (reg_dump_flag & DPU_DBG_DUMP_IN_MEM);
-
- pr_debug("%s: reg_dump_flag=%d in_log=%d in_mem=%d\n",
- dump_name, reg_dump_flag, in_log, in_mem);
-
- if (!in_log && !in_mem)
- return;
-
- if (in_log)
- dev_info(dpu_dbg_base.dev, "%s: start_offset %p len 0x%zx\n",
- dump_name, (void*)(addr - base_addr),
- len_bytes);
-
- len_align = (len_bytes + REG_DUMP_ALIGN - 1) / REG_DUMP_ALIGN;
- len_padded = len_align * REG_DUMP_ALIGN;
- end_addr = addr + len_bytes;
-
- if (in_mem) {
- if (dump_mem && !(*dump_mem)) {
- phys_addr_t phys = 0;
- *dump_mem = dma_alloc_coherent(dpu_dbg_base.dev,
- len_padded, &phys, GFP_KERNEL);
- }
-
- if (dump_mem && *dump_mem) {
- dump_addr = *dump_mem;
- dev_info(dpu_dbg_base.dev,
- "%s: start_addr:0x%pK len:0x%x reg_offset=%p\n",
- dump_name, dump_addr, len_padded,
- (void*)(addr - base_addr));
- } else {
- in_mem = 0;
- pr_err("dump_mem: kzalloc fails!\n");
- }
- }
-
- if (!from_isr)
- _dpu_dbg_enable_power(true);
-
- for (i = 0; i < len_align; i++) {
- u32 x0, x4, x8, xc;
-
- x0 = (addr < end_addr) ? readl_relaxed(addr + 0x0) : 0;
- x4 = (addr + 0x4 < end_addr) ? readl_relaxed(addr + 0x4) : 0;
- x8 = (addr + 0x8 < end_addr) ? readl_relaxed(addr + 0x8) : 0;
- xc = (addr + 0xc < end_addr) ? readl_relaxed(addr + 0xc) : 0;
-
- if (in_log)
- dev_info(dpu_dbg_base.dev,
- "%p : %08x %08x %08x %08x\n",
- (void*)(addr - base_addr), x0, x4, x8,
- xc);
-
- if (dump_addr) {
- dump_addr[i * 4] = x0;
- dump_addr[i * 4 + 1] = x4;
- dump_addr[i * 4 + 2] = x8;
- dump_addr[i * 4 + 3] = xc;
- }
-
- addr += REG_DUMP_ALIGN;
- }
-
- if (!from_isr)
- _dpu_dbg_enable_power(false);
-}
-
-/**
- * _dpu_dbg_get_dump_range - helper to retrieve dump length for a range node
- * @range_node: range node to dump
- * @max_offset: max offset of the register base
- * @Return: length
- */
-static u32 _dpu_dbg_get_dump_range(struct dpu_dbg_reg_offset *range_node,
- size_t max_offset)
-{
- u32 length = 0;
-
- if ((range_node->start > range_node->end) ||
- (range_node->end > max_offset) || (range_node->start == 0
- && range_node->end == 0)) {
- length = max_offset;
- } else {
- length = range_node->end - range_node->start;
- }
-
- return length;
-}
-
-static int _dpu_dump_reg_range_cmp(void *priv, struct list_head *a,
- struct list_head *b)
-{
- struct dpu_dbg_reg_range *ar, *br;
-
- if (!a || !b)
- return 0;
-
- ar = container_of(a, struct dpu_dbg_reg_range, head);
- br = container_of(b, struct dpu_dbg_reg_range, head);
-
- return ar->offset.start - br->offset.start;
-}
-
-/**
- * _dpu_dump_reg_by_ranges - dump ranges or full range of the register blk base
- * @dbg: register blk base structure
- * @reg_dump_flag: dump target, memory, kernel log, or both
- */
-static void _dpu_dump_reg_by_ranges(struct dpu_dbg_reg_base *dbg,
- u32 reg_dump_flag)
-{
- char *addr;
- size_t len;
- struct dpu_dbg_reg_range *range_node;
-
- if (!dbg || !(dbg->base || dbg->cb)) {
- pr_err("dbg base is null!\n");
- return;
- }
-
- dev_info(dpu_dbg_base.dev, "%s:=========%s DUMP=========\n", __func__,
- dbg->name);
- if (dbg->cb) {
- dbg->cb(dbg->cb_ptr);
- /* If there is a list to dump the registers by ranges, use the ranges */
- } else if (!list_empty(&dbg->sub_range_list)) {
- /* sort the list by start address first */
- list_sort(NULL, &dbg->sub_range_list, _dpu_dump_reg_range_cmp);
- list_for_each_entry(range_node, &dbg->sub_range_list, head) {
- len = _dpu_dbg_get_dump_range(&range_node->offset,
- dbg->max_offset);
- addr = dbg->base + range_node->offset.start;
- pr_debug("%s: range_base=0x%pK start=0x%x end=0x%x\n",
- range_node->range_name,
- addr, range_node->offset.start,
- range_node->offset.end);
-
- _dpu_dump_reg(range_node->range_name, reg_dump_flag,
- dbg->base, addr, len,
- &range_node->reg_dump, false);
- }
- } else {
- /* If there is no list to dump ranges, dump all registers */
- dev_info(dpu_dbg_base.dev,
- "Ranges not found, will dump full registers\n");
- dev_info(dpu_dbg_base.dev, "base:0x%pK len:0x%zx\n", dbg->base,
- dbg->max_offset);
- addr = dbg->base;
- len = dbg->max_offset;
- _dpu_dump_reg(dbg->name, reg_dump_flag, dbg->base, addr, len,
- &dbg->reg_dump, false);
- }
-}
-
-/**
- * _dpu_dump_reg_by_blk - dump a named register base region
- * @blk_name: register blk name
- */
-static void _dpu_dump_reg_by_blk(const char *blk_name)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *blk_base;
-
- if (!dbg_base)
- return;
-
- list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head) {
- if (strlen(blk_base->name) &&
- !strcmp(blk_base->name, blk_name)) {
- _dpu_dump_reg_by_ranges(blk_base,
- dbg_base->enable_reg_dump);
- break;
- }
- }
-}
-
-/**
- * _dpu_dump_get_blk_addr - retrieve register block address by name
- * @blk_name: register blk name
- * @Return: register blk base, or NULL
- */
-static struct dpu_dbg_reg_base *_dpu_dump_get_blk_addr(const char *blk_name)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *blk_base;
-
- list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head)
- if (strlen(blk_base->name) && !strcmp(blk_base->name, blk_name))
- return blk_base;
-
- return NULL;
-}
-
static void _dpu_dbg_dump_dpu_dbg_bus(struct dpu_dbg_dpu_debug_bus *bus)
{
bool in_log, in_mem;
@@ -2490,27 +2230,14 @@ static void _dpu_dbg_dump_vbif_dbg_bus(struct dpu_dbg_vbif_debug_bus *bus)
/**
* _dpu_dump_array - dump array of register bases
- * @blk_arr: array of register base pointers
- * @len: length of blk_arr
* @do_panic: whether to trigger a panic after dumping
* @name: string indicating origin of dump
* @dump_dbgbus_dpu: whether to dump the dpu debug bus
* @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus
*/
-static void _dpu_dump_array(struct dpu_dbg_reg_base *blk_arr[],
- u32 len, bool do_panic, const char *name, bool dump_dbgbus_dpu,
- bool dump_dbgbus_vbif_rt)
+static void _dpu_dump_array(bool do_panic, const char *name,
+ bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt)
{
- int i;
-
- if (!blk_arr || !len) {
- for (i = 0; i < len; i++) {
- if (blk_arr[i] != NULL)
- _dpu_dump_reg_by_ranges(blk_arr[i],
- dpu_dbg_base.enable_reg_dump);
- }
- }
-
if (dump_dbgbus_dpu)
_dpu_dbg_dump_dpu_dbg_bus(&dpu_dbg_base.dbgbus_dpu);
@@ -2527,50 +2254,27 @@ static void _dpu_dump_array(struct dpu_dbg_reg_base *blk_arr[],
*/
static void _dpu_dump_work(struct work_struct *work)
{
- _dpu_dump_array(dpu_dbg_base.req_dump_blks,
- ARRAY_SIZE(dpu_dbg_base.req_dump_blks),
- dpu_dbg_base.work_panic, "dpudump_workitem",
+ _dpu_dump_array(dpu_dbg_base.work_panic, "dpudump_workitem",
dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work,
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
void dpu_dbg_dump(bool queue_work, const char *name, ...)
{
- int index = 0;
bool do_panic = false;
bool dump_dbgbus_dpu = false;
bool dump_dbgbus_vbif_rt = false;
va_list args;
char *blk_name = NULL;
- struct dpu_dbg_reg_base *blk_base = NULL;
- struct dpu_dbg_reg_base **blk_arr;
- u32 blk_len;
if (queue_work && work_pending(&dpu_dbg_base.dump_work))
return;
- blk_arr = &dpu_dbg_base.req_dump_blks[0];
- blk_len = ARRAY_SIZE(dpu_dbg_base.req_dump_blks);
-
- memset(dpu_dbg_base.req_dump_blks, 0,
- sizeof(dpu_dbg_base.req_dump_blks));
-
va_start(args, name);
while ((blk_name = va_arg(args, char*))) {
if (IS_ERR_OR_NULL(blk_name))
break;
- blk_base = _dpu_dump_get_blk_addr(blk_name);
- if (blk_base) {
- if (index < blk_len) {
- blk_arr[index] = blk_base;
- index++;
- } else {
- pr_err("insufficient space to to dump %s\n",
- blk_name);
- }
- }
-
if (!strcmp(blk_name, "dbg_bus"))
dump_dbgbus_dpu = true;
@@ -2594,8 +2298,8 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
dump_dbgbus_vbif_rt;
schedule_work(&dpu_dbg_base.dump_work);
} else {
- _dpu_dump_array(blk_arr, blk_len, do_panic, name,
- dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
+ _dpu_dump_array(do_panic, name, dump_dbgbus_dpu,
+ dump_dbgbus_vbif_rt);
}
}
@@ -2622,9 +2326,7 @@ static int dpu_dbg_debugfs_open(struct inode *inode, struct file *file)
static ssize_t dpu_dbg_dump_write(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
{
- _dpu_dump_array(NULL, 0, dpu_dbg_base.panic_on_err, "dump_debugfs",
- true, true, true);
-
+ _dpu_dump_array(dpu_dbg_base.panic_on_err, "dump_debugfs", true, true);
return count;
}
@@ -2633,245 +2335,9 @@ static const struct file_operations dpu_dbg_dump_fops = {
.write = dpu_dbg_dump_write,
};
-/**
- * dpu_dbg_reg_base_release - release allocated reg dump file private data
- * @inode: debugfs inode
- * @file: file handle
- * @Return: 0 on success
- */
-static int dpu_dbg_reg_base_release(struct inode *inode, struct file *file)
-{
- struct dpu_dbg_reg_base *dbg = file->private_data;
-
- if (dbg && dbg->buf) {
- kfree(dbg->buf);
- dbg->buf_len = 0;
- dbg->buf = NULL;
- }
- return 0;
-}
-
-
-/**
- * dpu_dbg_reg_base_offset_write - set new offset and len to debugfs reg base
- * @file: file handler
- * @user_buf: user buffer content from debugfs
- * @count: size of user buffer
- * @ppos: position offset of user buffer
- */
-static ssize_t dpu_dbg_reg_base_offset_write(struct file *file,
- const char __user *user_buf, size_t count, loff_t *ppos)
-{
- struct dpu_dbg_reg_base *dbg = file->private_data;
- u32 off = 0;
- u32 cnt = DEFAULT_BASE_REG_CNT;
- char buf[24];
-
- if (!dbg)
- return -ENODEV;
-
- if (count >= sizeof(buf))
- return -EFAULT;
-
- if (copy_from_user(buf, user_buf, count))
- return -EFAULT;
-
- buf[count] = 0; /* end of string */
-
- if (sscanf(buf, "%5x %x", &off, &cnt) != 2)
- return -EFAULT;
-
- if (off > dbg->max_offset)
- return -EINVAL;
-
- if (off % sizeof(u32))
- return -EINVAL;
-
- if (cnt > (dbg->max_offset - off))
- cnt = dbg->max_offset - off;
-
- dbg->off = off;
- dbg->cnt = cnt;
-
- pr_debug("offset=%x cnt=%x\n", off, cnt);
-
- return count;
-}
-
-/**
- * dpu_dbg_reg_base_offset_read - read current offset and len of register base
- * @file: file handler
- * @user_buf: user buffer content from debugfs
- * @count: size of user buffer
- * @ppos: position offset of user buffer
- */
-static ssize_t dpu_dbg_reg_base_offset_read(struct file *file,
- char __user *buff, size_t count, loff_t *ppos)
-{
- struct dpu_dbg_reg_base *dbg = file->private_data;
- int len = 0;
- char buf[24] = {'\0'};
-
- if (!dbg)
- return -ENODEV;
-
- if (*ppos)
- return 0; /* the end */
-
- if (dbg->off % sizeof(u32))
- return -EFAULT;
-
- len = snprintf(buf, sizeof(buf), "0x%08zx %zx\n", dbg->off, dbg->cnt);
- if (len < 0 || len >= sizeof(buf))
- return 0;
-
- if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
- return -EFAULT;
-
- *ppos += len; /* increase offset */
-
- return len;
-}
-
-/**
- * dpu_dbg_reg_base_reg_write - write to reg base hw at offset a given value
- * @file: file handler
- * @user_buf: user buffer content from debugfs
- * @count: size of user buffer
- * @ppos: position offset of user buffer
- */
-static ssize_t dpu_dbg_reg_base_reg_write(struct file *file,
- const char __user *user_buf, size_t count, loff_t *ppos)
-{
- struct dpu_dbg_reg_base *dbg = file->private_data;
- size_t off;
- u32 data, cnt;
- char buf[24];
-
- if (!dbg)
- return -ENODEV;
-
- if (count >= sizeof(buf))
- return -EFAULT;
-
- if (copy_from_user(buf, user_buf, count))
- return -EFAULT;
-
- buf[count] = 0; /* end of string */
-
- cnt = sscanf(buf, "%zx %x", &off, &data);
-
- if (cnt < 2)
- return -EFAULT;
-
- if (off % sizeof(u32))
- return -EFAULT;
-
- if (off >= dbg->max_offset)
- return -EFAULT;
-
- _dpu_dbg_enable_power(true);
-
- writel_relaxed(data, dbg->base + off);
-
- _dpu_dbg_enable_power(false);
-
- pr_debug("addr=%zx data=%x\n", off, data);
-
- return count;
-}
-
-/**
- * dpu_dbg_reg_base_reg_read - read len from reg base hw at current offset
- * @file: file handler
- * @user_buf: user buffer content from debugfs
- * @count: size of user buffer
- * @ppos: position offset of user buffer
- */
-static ssize_t dpu_dbg_reg_base_reg_read(struct file *file,
- char __user *user_buf, size_t count, loff_t *ppos)
-{
- struct dpu_dbg_reg_base *dbg = file->private_data;
- size_t len;
-
- if (!dbg) {
- pr_err("invalid handle\n");
- return -ENODEV;
- }
-
- if (!dbg->buf) {
- char dump_buf[64];
- char *ptr;
- int cnt, tot;
-
- dbg->buf_len = sizeof(dump_buf) *
- DIV_ROUND_UP(dbg->cnt, ROW_BYTES);
- dbg->buf = kzalloc(dbg->buf_len, GFP_KERNEL);
-
- if (!dbg->buf)
- return -ENOMEM;
-
- if (dbg->off % sizeof(u32))
- return -EFAULT;
-
- ptr = dbg->base + dbg->off;
- tot = 0;
-
- _dpu_dbg_enable_power(true);
-
- for (cnt = dbg->cnt; cnt > 0; cnt -= ROW_BYTES) {
- hex_dump_to_buffer(ptr, min(cnt, ROW_BYTES),
- ROW_BYTES, GROUP_BYTES, dump_buf,
- sizeof(dump_buf), false);
- len = scnprintf(dbg->buf + tot, dbg->buf_len - tot,
- "0x%08x: %s\n",
- ((int) (unsigned long) ptr) -
- ((int) (unsigned long) dbg->base),
- dump_buf);
-
- ptr += ROW_BYTES;
- tot += len;
- if (tot >= dbg->buf_len)
- break;
- }
-
- _dpu_dbg_enable_power(false);
-
- dbg->buf_len = tot;
- }
-
- if (*ppos >= dbg->buf_len)
- return 0; /* done reading */
-
- len = min(count, dbg->buf_len - (size_t) *ppos);
- if (copy_to_user(user_buf, dbg->buf + *ppos, len)) {
- pr_err("failed to copy to user\n");
- return -EFAULT;
- }
-
- *ppos += len; /* increase offset */
-
- return len;
-}
-
-static const struct file_operations dpu_off_fops = {
- .open = dpu_dbg_debugfs_open,
- .release = dpu_dbg_reg_base_release,
- .read = dpu_dbg_reg_base_offset_read,
- .write = dpu_dbg_reg_base_offset_write,
-};
-
-static const struct file_operations dpu_reg_fops = {
- .open = dpu_dbg_debugfs_open,
- .release = dpu_dbg_reg_base_release,
- .read = dpu_dbg_reg_base_reg_read,
- .write = dpu_dbg_reg_base_reg_write,
-};
-
int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
{
static struct dpu_dbg_base *dbg = &dpu_dbg_base;
- struct dpu_dbg_reg_base *blk_base;
char debug_name[80] = "";
if (!debugfs_root)
@@ -2881,8 +2347,6 @@ int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
&dpu_dbg_dump_fops);
debugfs_create_u32("panic", 0600, debugfs_root,
&dpu_dbg_base.panic_on_err);
- debugfs_create_u32("reg_dump", 0600, debugfs_root,
- &dpu_dbg_base.enable_reg_dump);
if (dbg->dbgbus_dpu.entries) {
dbg->dbgbus_dpu.cmn.name = DBGBUS_NAME_DPU;
@@ -2902,18 +2366,6 @@ int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
&dbg->dbgbus_vbif_rt.cmn.enable_mask);
}
- list_for_each_entry(blk_base, &dbg->reg_base_list, reg_base_head) {
- snprintf(debug_name, sizeof(debug_name), "%s_off",
- blk_base->name);
- debugfs_create_file(debug_name, 0600, debugfs_root, blk_base,
- &dpu_off_fops);
-
- snprintf(debug_name, sizeof(debug_name), "%s_reg",
- blk_base->name);
- debugfs_create_file(debug_name, 0600, debugfs_root, blk_base,
- &dpu_reg_fops);
- }
-
return 0;
}
@@ -2964,172 +2416,18 @@ int dpu_dbg_init(struct device *dev)
INIT_WORK(&dpu_dbg_base.dump_work, _dpu_dump_work);
dpu_dbg_base.work_panic = false;
dpu_dbg_base.panic_on_err = DEFAULT_PANIC;
- dpu_dbg_base.enable_reg_dump = DEFAULT_REGDUMP;
- pr_info("debug_status: panic:%d, dump:%d\n", dpu_dbg_base.panic_on_err,
- dpu_dbg_base.enable_reg_dump);
+ pr_info("debug_status: panic:%d\n", dpu_dbg_base.panic_on_err);
return 0;
}
-static void dpu_dbg_reg_base_destroy(void)
-{
- struct dpu_dbg_reg_range *range_node, *range_tmp;
- struct dpu_dbg_reg_base *blk_base, *blk_tmp;
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
-
- if (!dbg_base)
- return;
-
- list_for_each_entry_safe(blk_base, blk_tmp, &dbg_base->reg_base_list,
- reg_base_head) {
- list_for_each_entry_safe(range_node, range_tmp,
- &blk_base->sub_range_list, head) {
- list_del(&range_node->head);
- kfree(range_node);
- }
- list_del(&blk_base->reg_base_head);
- kfree(blk_base);
- }
-}
/**
* dpu_dbg_destroy - destroy dpu debug facilities
*/
void dpu_dbg_destroy(void)
{
_dpu_dbg_debugfs_destroy();
- dpu_dbg_reg_base_destroy();
-}
-
-int dpu_dbg_reg_register_base(const char *name, void __iomem *base,
- size_t max_offset)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *reg_base;
-
- if (!name || !strlen(name)) {
- pr_err("no debug name provided\n");
- return -EINVAL;
- }
-
- reg_base = kzalloc(sizeof(*reg_base), GFP_KERNEL);
- if (!reg_base)
- return -ENOMEM;
-
- strlcpy(reg_base->name, name, sizeof(reg_base->name));
- reg_base->base = base;
- reg_base->max_offset = max_offset;
- reg_base->off = 0;
- reg_base->cnt = DEFAULT_BASE_REG_CNT;
- reg_base->reg_dump = NULL;
-
- /* Initialize list to make sure check for null list will be valid */
- INIT_LIST_HEAD(®_base->sub_range_list);
-
- pr_debug("%s base: %pK max_offset 0x%zX\n", reg_base->name,
- reg_base->base, reg_base->max_offset);
-
- list_add(®_base->reg_base_head, &dbg_base->reg_base_list);
-
- return 0;
-}
-
-int dpu_dbg_reg_register_cb(const char *name, void (*cb)(void *), void *ptr)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *reg_base;
-
- if (!name || !strlen(name)) {
- pr_err("no debug name provided\n");
- return -EINVAL;
- }
-
- reg_base = kzalloc(sizeof(*reg_base), GFP_KERNEL);
- if (!reg_base)
- return -ENOMEM;
-
- strlcpy(reg_base->name, name, sizeof(reg_base->name));
- reg_base->base = NULL;
- reg_base->max_offset = 0;
- reg_base->off = 0;
- reg_base->cnt = DEFAULT_BASE_REG_CNT;
- reg_base->reg_dump = NULL;
- reg_base->cb = cb;
- reg_base->cb_ptr = ptr;
-
- /* Initialize list to make sure check for null list will be valid */
- INIT_LIST_HEAD(®_base->sub_range_list);
-
- pr_debug("%s cb: %pK cb_ptr: %pK\n", reg_base->name,
- reg_base->cb, reg_base->cb_ptr);
-
- list_add(®_base->reg_base_head, &dbg_base->reg_base_list);
-
- return 0;
-}
-
-void dpu_dbg_reg_unregister_cb(const char *name, void (*cb)(void *), void *ptr)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *reg_base;
-
- if (!dbg_base)
- return;
-
- list_for_each_entry(reg_base, &dbg_base->reg_base_list, reg_base_head) {
- if (strlen(reg_base->name) &&
- !strcmp(reg_base->name, name)) {
- pr_debug("%s cb: %pK cb_ptr: %pK\n", reg_base->name,
- reg_base->cb, reg_base->cb_ptr);
- list_del(®_base->reg_base_head);
- kfree(reg_base);
- break;
- }
- }
-}
-
-void dpu_dbg_reg_register_dump_range(const char *base_name,
- const char *range_name, u32 offset_start, u32 offset_end,
- uint32_t xin_id)
-{
- struct dpu_dbg_reg_base *reg_base;
- struct dpu_dbg_reg_range *range;
-
- reg_base = _dpu_dump_get_blk_addr(base_name);
- if (!reg_base) {
- pr_err("error: for range %s unable to locate base %s\n",
- range_name, base_name);
- return;
- }
-
- if (!range_name || strlen(range_name) == 0) {
- pr_err("%pS: bad range name, base_name %s, offset_start 0x%X, end 0x%X\n",
- __builtin_return_address(0), base_name,
- offset_start, offset_end);
- return;
- }
-
- if (offset_end - offset_start < REG_DUMP_ALIGN ||
- offset_start > offset_end) {
- pr_err("%pS: bad range, base_name %s, range_name %s, offset_start 0x%X, end 0x%X\n",
- __builtin_return_address(0), base_name,
- range_name, offset_start, offset_end);
- return;
- }
-
- range = kzalloc(sizeof(*range), GFP_KERNEL);
- if (!range)
- return;
-
- strlcpy(range->range_name, range_name, sizeof(range->range_name));
- range->offset.start = offset_start;
- range->offset.end = offset_end;
- range->xin_id = xin_id;
- list_add_tail(&range->head, ®_base->sub_range_list);
-
- pr_debug("base %s, range %s, start 0x%X, end 0x%X\n",
- base_name, range->range_name,
- range->offset.start, range->offset.end);
}
void dpu_dbg_set_dpu_top_offset(u32 blk_off)
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h
index 052c78d5b4f5..dd36c30cf7c0 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/dpu_dbg.h
@@ -73,53 +73,6 @@ void dpu_dbg_destroy(void);
*/
void dpu_dbg_dump(bool queue_work, const char *name, ...);
-/**
- * dpu_dbg_reg_register_base - register a hw register address section for later
- * dumping. call this before calling dpu_dbg_reg_register_dump_range
- * to be able to specify sub-ranges within the base hw range.
- * @name: name of base region
- * @base: base pointer of region
- * @max_offset: length of region
- * Returns: 0 or -ERROR
- */
-int dpu_dbg_reg_register_base(const char *name, void __iomem *base,
- size_t max_offset);
-
-/**
- * dpu_dbg_reg_register_cb - register a hw register callback for later
- * dumping.
- * @name: name of base region
- * @cb: callback of external region
- * @cb_ptr: private pointer of external region
- * Returns: 0 or -ERROR
- */
-int dpu_dbg_reg_register_cb(const char *name, void (*cb)(void *), void *ptr);
-
-/**
- * dpu_dbg_reg_unregister_cb - register a hw unregister callback for later
- * dumping.
- * @name: name of base region
- * @cb: callback of external region
- * @cb_ptr: private pointer of external region
- * Returns: None
- */
-void dpu_dbg_reg_unregister_cb(const char *name, void (*cb)(void *), void *ptr);
-
-/**
- * dpu_dbg_reg_register_dump_range - register a hw register sub-region for
- * later register dumping associated with base specified by
- * dpu_dbg_reg_register_base
- * @base_name: name of base region
- * @range_name: name of sub-range within base region
- * @offset_start: sub-range's start offset from base's base pointer
- * @offset_end: sub-range's end offset from base's base pointer
- * @xin_id: xin id
- * Returns: none
- */
-void dpu_dbg_reg_register_dump_range(const char *base_name,
- const char *range_name, u32 offset_start, u32 offset_end,
- uint32_t xin_id);
-
/**
* dpu_dbg_set_dpu_top_offset - set the target specific offset from mdss base
* address of the top registers. Used for accessing debug bus controls.
@@ -160,18 +113,6 @@ static inline void dpu_dbg_dump(bool queue_work, const char *name, ...)
{
}
-static inline int dpu_dbg_reg_register_base(const char *name,
- void __iomem *base, size_t max_offset)
-{
- return 0;
-}
-
-static inline void dpu_dbg_reg_register_dump_range(const char *base_name,
- const char *range_name, u32 offset_start, u32 offset_end,
- uint32_t xin_id)
-{
-}
-
void dpu_dbg_set_dpu_top_offset(u32 blk_off)
{
}
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 16/19] drm/msm: dpu: Remove panic from dpu debug dump
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (14 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 15/19] drm/msm: dpu: Remove arbitrary register dumps Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
2018-06-20 20:48 ` [DPU PATCH 17/19] drm/msm: dpu: Remove dsi debug block name Sean Paul
` (2 subsequent siblings)
18 siblings, 0 replies; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
Better not to allow arbitrary panics of the kernel when poking debugfs
files.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 31 +++----------------
drivers/gpu/drm/msm/dpu_dbg.h | 4 ---
5 files changed, 8 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5ff627827be9..3519f7e84f0f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 5589d1289da9..19f5b5064ed8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 8ac7f0537c05..54f4e78cf1fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 3572e3cbec6c..2a9b8c732e33 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -26,7 +26,6 @@
#include "disp/dpu1/dpu_hw_catalog.h"
-#define DEFAULT_PANIC 1
#define DEFAULT_DBGBUS_DPU DPU_DBG_DUMP_IN_MEM
#define DEFAULT_DBGBUS_VBIFRT DPU_DBG_DUMP_IN_MEM
#define REG_BASE_NAME_LEN 80
@@ -128,9 +127,7 @@ struct dpu_dbg_vbif_debug_bus {
* struct dpu_dbg_base - global dpu debug base structure
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @panic_on_err: whether to kernel panic after triggering dump via debugfs
* @dump_work: work struct for deferring register dump work to separate thread
- * @work_panic: panic after dump if internal user passed "panic" special region
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
* @dsi_dbg_bus: dump dsi debug bus register
@@ -139,9 +136,7 @@ static struct dpu_dbg_base {
struct list_head reg_base_list;
struct device *dev;
- u32 panic_on_err;
struct work_struct dump_work;
- bool work_panic;
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
@@ -2230,22 +2225,18 @@ static void _dpu_dbg_dump_vbif_dbg_bus(struct dpu_dbg_vbif_debug_bus *bus)
/**
* _dpu_dump_array - dump array of register bases
- * @do_panic: whether to trigger a panic after dumping
* @name: string indicating origin of dump
* @dump_dbgbus_dpu: whether to dump the dpu debug bus
* @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus
*/
-static void _dpu_dump_array(bool do_panic, const char *name,
- bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt)
+static void _dpu_dump_array(const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt)
{
if (dump_dbgbus_dpu)
_dpu_dbg_dump_dpu_dbg_bus(&dpu_dbg_base.dbgbus_dpu);
if (dump_dbgbus_vbif_rt)
_dpu_dbg_dump_vbif_dbg_bus(&dpu_dbg_base.dbgbus_vbif_rt);
-
- if (do_panic && dpu_dbg_base.panic_on_err)
- panic(name);
}
/**
@@ -2254,14 +2245,13 @@ static void _dpu_dump_array(bool do_panic, const char *name,
*/
static void _dpu_dump_work(struct work_struct *work)
{
- _dpu_dump_array(dpu_dbg_base.work_panic, "dpudump_workitem",
+ _dpu_dump_array("dpudump_workitem",
dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work,
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
void dpu_dbg_dump(bool queue_work, const char *name, ...)
{
- bool do_panic = false;
bool dump_dbgbus_dpu = false;
bool dump_dbgbus_vbif_rt = false;
va_list args;
@@ -2283,23 +2273,18 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
if (!strcmp(blk_name, "dsi_dbg_bus"))
dpu_dbg_base.dsi_dbg_bus = true;
-
- if (!strcmp(blk_name, "panic"))
- do_panic = true;
}
va_end(args);
if (queue_work) {
/* schedule work to dump later */
- dpu_dbg_base.work_panic = do_panic;
dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work =
dump_dbgbus_dpu;
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
dump_dbgbus_vbif_rt;
schedule_work(&dpu_dbg_base.dump_work);
} else {
- _dpu_dump_array(do_panic, name, dump_dbgbus_dpu,
- dump_dbgbus_vbif_rt);
+ _dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
}
}
@@ -2326,7 +2311,7 @@ static int dpu_dbg_debugfs_open(struct inode *inode, struct file *file)
static ssize_t dpu_dbg_dump_write(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
{
- _dpu_dump_array(dpu_dbg_base.panic_on_err, "dump_debugfs", true, true);
+ _dpu_dump_array("dump_debugfs", true, true);
return count;
}
@@ -2345,8 +2330,6 @@ int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
debugfs_create_file("dump", 0600, debugfs_root, NULL,
&dpu_dbg_dump_fops);
- debugfs_create_u32("panic", 0600, debugfs_root,
- &dpu_dbg_base.panic_on_err);
if (dbg->dbgbus_dpu.entries) {
dbg->dbgbus_dpu.cmn.name = DBGBUS_NAME_DPU;
@@ -2414,10 +2397,6 @@ int dpu_dbg_init(struct device *dev)
dpu_dbg_base.dev = dev;
INIT_WORK(&dpu_dbg_base.dump_work, _dpu_dump_work);
- dpu_dbg_base.work_panic = false;
- dpu_dbg_base.panic_on_err = DEFAULT_PANIC;
-
- pr_info("debug_status: panic:%d\n", dpu_dbg_base.panic_on_err);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h
index dd36c30cf7c0..6a247ce39997 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/dpu_dbg.h
@@ -27,8 +27,6 @@ enum dpu_dbg_dump_flag {
* @va_args: list of named register dump ranges and regions to dump, as
* registered previously through dpu_dbg_reg_register_base and
* dpu_dbg_reg_register_dump_range.
- * Including the special name "panic" will trigger a panic after
- * the dumping work has completed.
*/
#define DPU_DBG_DUMP(...) dpu_dbg_dump(false, __func__, ##__VA_ARGS__, NULL)
@@ -67,8 +65,6 @@ void dpu_dbg_destroy(void);
* @va_args: list of named register dump ranges and regions to dump, as
* registered previously through dpu_dbg_reg_register_base and
* dpu_dbg_reg_register_dump_range.
- * Including the special name "panic" will trigger a panic after
- * the dumping work has completed.
* Returns: none
*/
void dpu_dbg_dump(bool queue_work, const char *name, ...);
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 17/19] drm/msm: dpu: Remove dsi debug block name
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (15 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 16/19] drm/msm: dpu: Remove panic from dpu debug dump Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
2018-06-20 20:48 ` [DPU PATCH 18/19] drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP Sean Paul
2018-06-20 20:48 ` [DPU PATCH 19/19] drm/msm: dpu: Move dpu_dbg into dpu1 directory Sean Paul
18 siblings, 0 replies; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
Leftover from dsi-staging, it looks like.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/dpu_dbg.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 2a9b8c732e33..51d46975cc27 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -130,7 +130,6 @@ struct dpu_dbg_vbif_debug_bus {
* @dump_work: work struct for deferring register dump work to separate thread
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
- * @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
struct list_head reg_base_list;
@@ -140,7 +139,6 @@ static struct dpu_dbg_base {
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
- bool dsi_dbg_bus;
} dpu_dbg_base;
static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
@@ -2270,9 +2268,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
if (!strcmp(blk_name, "vbif_dbg_bus"))
dump_dbgbus_vbif_rt = true;
-
- if (!strcmp(blk_name, "dsi_dbg_bus"))
- dpu_dbg_base.dsi_dbg_bus = true;
}
va_end(args);
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 18/19] drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (16 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 17/19] drm/msm: dpu: Remove dsi debug block name Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
2018-06-20 20:48 ` [DPU PATCH 19/19] drm/msm: dpu: Move dpu_dbg into dpu1 directory Sean Paul
18 siblings, 0 replies; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
Now that we don't have arbitrary register dumping, remove the macro and
just call dpu_dbg_dump directly.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 37 +++++--------------
drivers/gpu/drm/msm/dpu_dbg.h | 23 ++++--------
5 files changed, 21 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 3519f7e84f0f..ce4faee12adc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 19f5b5064ed8..9519dbc24266 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 54f4e78cf1fd..110c463077ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 51d46975cc27..ae2aee7ed9e1 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -2248,39 +2248,22 @@ static void _dpu_dump_work(struct work_struct *work)
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
-void dpu_dbg_dump(bool queue_work, const char *name, ...)
+void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt)
{
- bool dump_dbgbus_dpu = false;
- bool dump_dbgbus_vbif_rt = false;
- va_list args;
- char *blk_name = NULL;
-
if (queue_work && work_pending(&dpu_dbg_base.dump_work))
return;
- va_start(args, name);
- while ((blk_name = va_arg(args, char*))) {
- if (IS_ERR_OR_NULL(blk_name))
- break;
-
- if (!strcmp(blk_name, "dbg_bus"))
- dump_dbgbus_dpu = true;
-
- if (!strcmp(blk_name, "vbif_dbg_bus"))
- dump_dbgbus_vbif_rt = true;
- }
- va_end(args);
-
- if (queue_work) {
- /* schedule work to dump later */
- dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work =
- dump_dbgbus_dpu;
- dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
- dump_dbgbus_vbif_rt;
- schedule_work(&dpu_dbg_base.dump_work);
- } else {
+ if (!queue_work) {
_dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
+ return;
}
+
+ /* schedule work to dump later */
+ dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = dump_dbgbus_dpu;
+ dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
+ dump_dbgbus_vbif_rt;
+ schedule_work(&dpu_dbg_base.dump_work);
}
/*
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h
index 6a247ce39997..05504e676f6a 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/dpu_dbg.h
@@ -22,14 +22,6 @@ enum dpu_dbg_dump_flag {
DPU_DBG_DUMP_IN_MEM = BIT(1),
};
-/**
- * DPU_DBG_DUMP - trigger dumping of all dpu_dbg facilities
- * @va_args: list of named register dump ranges and regions to dump, as
- * registered previously through dpu_dbg_reg_register_base and
- * dpu_dbg_reg_register_dump_range.
- */
-#define DPU_DBG_DUMP(...) dpu_dbg_dump(false, __func__, ##__VA_ARGS__, NULL)
-
#if defined(CONFIG_DEBUG_FS)
/**
@@ -60,14 +52,14 @@ void dpu_dbg_destroy(void);
/**
* dpu_dbg_dump - trigger dumping of all dpu_dbg facilities
- * @queue_work: whether to queue the dumping work to the work_struct
- * @name: string indicating origin of dump
- * @va_args: list of named register dump ranges and regions to dump, as
- * registered previously through dpu_dbg_reg_register_base and
- * dpu_dbg_reg_register_dump_range.
+ * @queue_work: whether to queue the dumping work to the work_struct
+ * @name: string indicating origin of dump
+ * @dump_dbgbus: dump the dpu debug bus
+ * @dump_vbif_rt: dump the vbif rt bus
* Returns: none
*/
-void dpu_dbg_dump(bool queue_work, const char *name, ...);
+void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt);
/**
* dpu_dbg_set_dpu_top_offset - set the target specific offset from mdss base
@@ -105,7 +97,8 @@ static inline void dpu_dbg_destroy(void)
{
}
-static inline void dpu_dbg_dump(bool queue_work, const char *name, ...)
+static inline void dpu_dbg_dump(bool queue_work, const char *name,
+ bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt);
{
}
--
Sean Paul, Software Engineer, Google / Chromium OS
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^ permalink raw reply related [flat|nested] 33+ messages in thread* [DPU PATCH 19/19] drm/msm: dpu: Move dpu_dbg into dpu1 directory
[not found] ` <20180620204841.56354-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (17 preceding siblings ...)
2018-06-20 20:48 ` [DPU PATCH 18/19] drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP Sean Paul
@ 2018-06-20 20:48 ` Sean Paul
18 siblings, 0 replies; 33+ messages in thread
From: Sean Paul @ 2018-06-20 20:48 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: jsanka-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
Sean Paul, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ
Now that dpu_dbg is cleaned up, move it into dpu directory with the
rest of dpu things.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c | 0
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.h | 0
3 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c (100%)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.h (100%)
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 9c182a9dab2b..1745447922bf 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -49,6 +49,7 @@ msm-y := \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
+ disp/dpu1/dpu_dbg.o \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
@@ -74,7 +75,6 @@ msm-y := \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
- dpu_dbg.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
similarity index 100%
rename from drivers/gpu/drm/msm/dpu_dbg.c
rename to drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
similarity index 100%
rename from drivers/gpu/drm/msm/dpu_dbg.h
rename to drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
--
Sean Paul, Software Engineer, Google / Chromium OS
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^ permalink raw reply related [flat|nested] 33+ messages in thread