From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Marijn Suijten <marijn.suijten@somainline.org>,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Adam Skladowski <a39.skl@gmail.com>,
Loic Poulain <loic.poulain@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Kuogee Hsieh <quic_khsieh@quicinc.com>,
Robert Foss <rfoss@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Rajesh Yadav <ryadav@codeaurora.org>,
Jeykumar Sankaran <jsanka@codeaurora.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Chandan Uddaraju <chandanu@codeaurora.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Martin Botka <martin.botka@somainline.org>,
Jami Kettunen <jami.kettunen@somainline.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Jordan Crouse <jordan@cosmicpenguin.net>,
Archit Taneja <architt@codeaurora.org>,
Sravanthi Kollukuduru <skolluku@codeaurora.org>
Subject: Re: [PATCH v2 10/17] drm/msm/dpu: Disable pingpong TE on DPU 5.0.0 and above
Date: Tue, 18 Apr 2023 14:48:14 +0200 [thread overview]
Message-ID: <5cc3b85c-1860-757e-471c-e69269276e23@linaro.org> (raw)
In-Reply-To: <20230411-dpu-intf-te-v2-10-ef76c877eb97@somainline.org>
On 17.04.2023 22:21, Marijn Suijten wrote:
> Since hardware revision 5.0.0 the TE configuration moved out of the
> PINGPONG block into the INTF block. Writing these registers has no
> effect, and is omitted downstream via the DPU/SDE_PINGPONG_TE feature
> flag. This flag is only added to PINGPONG blocks used by hardware prior
> to 5.0.0.
>
> The existing PP_BLK_TE macro has been removed in favour of directly
> passing this feature flag, which has thus far been the only difference
> with PP_BLK. PP_BLK_DITHER has been left in place as its embedded
> feature flag already excludes this DPU_PINGPONG_TE bit and differs by
> setting the block length to zero, as it only contains a DITHER subblock.
>
> The code that writes to these registers in the INTF block will follow in
> subsequent patches.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
I believe everything here is correct, even though there's
quite a bunch of stuff involved:
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 +++----
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 +++----
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 +++++------
> .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 +++++------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 +++++------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++--
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +-
> .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +-
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 +++++------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 +++----
> .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 24 ++++++++++-----------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 16 +++++++-------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 ++++++++++------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 12 ++++++-----
> 14 files changed, 78 insertions(+), 79 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 2b3ae84057df..b7845591c384 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -112,16 +112,16 @@ static const struct dpu_lm_cfg msm8998_lm[] = {
> };
>
> static const struct dpu_pingpong_cfg msm8998_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index ceca741e93c9..5b9b3b99f1b5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -110,16 +110,16 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
> };
>
> static const struct dpu_pingpong_cfg sdm845_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 282d410269ff..43cf813a4766 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -128,22 +128,22 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8150_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_TE2_MASK, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_TE2_MASK, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> -1),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index c57400265f28..1313193f410b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -116,22 +116,22 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> };
>
> static const struct dpu_pingpong_cfg sc8180x_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_TE2_MASK, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_TE2_MASK, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> -1),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 2c40229ea515..f8378990aa25 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -129,22 +129,22 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8250_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_TE2_MASK, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_TE2_MASK, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> -1),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 8799ed757119..68d1fb988b0d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -80,8 +80,8 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc7180_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_TE2_MASK, 0, sdm845_pp_sblk_te, -1, -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_TE2_MASK, 0, sdm845_pp_sblk_te, -1, -1),
> };
>
> static const struct dpu_intf_cfg sc7180_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 988d820f7ef2..e15dc96f1286 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -60,7 +60,7 @@ static const struct dpu_dspp_cfg sm6115_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm6115_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index c9003dcc1a59..2ff98ef6999f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -57,7 +57,7 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg qcm2290_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 41ef0c8fc993..6b7e1837422a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -127,22 +127,22 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8350_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x69000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> -1),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5957de185984..0961fa5c3907 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -87,10 +87,10 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc7280_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
> + PP_BLK("pingpong_0", PINGPONG_0, 0x69000, PINGPONG_SM8150_MASK, 0, sc7280_pp_sblk, -1, -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, PINGPONG_SM8150_MASK, 0, sc7280_pp_sblk, -1, -1),
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, PINGPONG_SM8150_MASK, 0, sc7280_pp_sblk, -1, -1),
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, PINGPONG_SM8150_MASK, 0, sc7280_pp_sblk, -1, -1),
> };
>
> static const struct dpu_intf_cfg sc7280_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 12c14d15e386..bad1c688517d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -121,18 +121,18 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> + PP_BLK("pingpong_0", PINGPONG_0, 0x69000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
> + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
> + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> };
>
> static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index e409c119b0a2..efd3aa6c9bc1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -128,28 +128,28 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = {
> };
> /* FIXME: interrupts */
> static const struct dpu_pingpong_cfg sm8450_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk,
> + PP_BLK("pingpong_0", PINGPONG_0, 0x69000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk,
> + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> -1),
> - PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk,
> + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, PINGPONG_SM8150_MASK, MERGE_3D_3, sdm845_pp_sblk,
> -1,
> -1),
> - PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk,
> + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, PINGPONG_SM8150_MASK, MERGE_3D_3, sdm845_pp_sblk,
> -1,
> -1),
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index ca8a02debda9..2d16cdbd7d44 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -75,11 +75,18 @@
> #define MIXER_QCM2290_MASK \
> (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
>
> -#define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
> +#define PINGPONG_SDM845_MASK \
> + (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE))
>
> -#define PINGPONG_SDM845_SPLIT_MASK \
> +#define PINGPONG_SDM845_TE2_MASK \
> (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
>
> +#define PINGPONG_SM8150_MASK \
> + (BIT(DPU_PINGPONG_DITHER))
> +
> +#define PINGPONG_SM8150_TE2_MASK \
> + (PINGPONG_SM8150_MASK | BIT(DPU_PINGPONG_TE2))
> +
> #define CTL_SC7280_MASK \
> (BIT(DPU_CTL_ACTIVE_CFG) | \
> BIT(DPU_CTL_FETCH_ACTIVE) | \
> @@ -501,21 +508,11 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> .intr_done = _done, \
> .intr_rdptr = _rdptr, \
> }
> -#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> +#define PP_BLK(_name, _id, _base, _features, _merge_3d, _sblk, _done, _rdptr) \
> {\
> .name = _name, .id = _id, \
> .base = _base, .len = 0xd4, \
> - .features = PINGPONG_SDM845_SPLIT_MASK, \
> - .merge_3d = _merge_3d, \
> - .sblk = &_sblk, \
> - .intr_done = _done, \
> - .intr_rdptr = _rdptr, \
> - }
> -#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0xd4, \
> - .features = PINGPONG_SDM845_MASK, \
> + .features = _features, \
> .merge_3d = _merge_3d, \
> .sblk = &_sblk, \
> .intr_done = _done, \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> index dea270c0936f..4a20a5841f22 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> @@ -300,11 +300,13 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
> static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
> unsigned long features)
> {
> - c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config;
> - c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
> - c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
> - c->ops.get_line_count = dpu_hw_pp_get_line_count;
> - c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
> + if (test_bit(DPU_PINGPONG_TE, &features)) {
> + c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config;
> + c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
> + c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
> + c->ops.get_line_count = dpu_hw_pp_get_line_count;
> + c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
> + }
> c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
> c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
> c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
>
next prev parent reply other threads:[~2023-04-18 12:48 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 20:21 [PATCH v2 00/17] drm/msm/dpu: Implement tearcheck support on INTF block Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 01/17] drm/msm/dpu: Remove unused INTF0 interrupt mask from SM6115/QCM2290 Marijn Suijten
2023-04-20 0:34 ` Dmitry Baryshkov
2023-04-24 16:55 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 02/17] drm/msm/dpu: Remove TE2 block and feature from DPU >= 7.0.0 hardware Marijn Suijten
2023-04-18 12:16 ` Konrad Dybcio
2023-04-20 0:44 ` Dmitry Baryshkov
2023-04-24 20:41 ` Abhinav Kumar
2023-04-24 22:18 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 03/17] drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header Marijn Suijten
2023-04-18 12:16 ` Konrad Dybcio
2023-04-20 0:45 ` Dmitry Baryshkov
2023-04-24 20:44 ` Abhinav Kumar
2023-04-24 22:25 ` Marijn Suijten
2023-04-24 23:52 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 04/17] drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typo Marijn Suijten
2023-04-18 12:17 ` Konrad Dybcio
2023-04-20 0:46 ` Dmitry Baryshkov
2023-04-24 20:53 ` [Freedreno] " Abhinav Kumar
2023-04-24 22:30 ` Marijn Suijten
2023-04-24 23:09 ` Abhinav Kumar
2023-04-25 6:54 ` Marijn Suijten
2023-04-25 16:18 ` Abhinav Kumar
2023-04-25 16:33 ` Marijn Suijten
2023-04-25 16:47 ` Abhinav Kumar
2023-04-25 20:43 ` Marijn Suijten
2023-04-25 21:37 ` Abhinav Kumar
2023-04-25 21:53 ` Marijn Suijten
2023-04-25 21:55 ` Abhinav Kumar
2023-04-25 22:15 ` Marijn Suijten
2023-04-25 22:37 ` Abhinav Kumar
2023-04-25 23:13 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 05/17] drm/msm/dpu: Remove duplicate register defines from INTF Marijn Suijten
2023-04-18 12:17 ` Konrad Dybcio
2023-04-20 0:46 ` Dmitry Baryshkov
2023-04-24 23:54 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 06/17] drm/msm/dpu: Remove extraneous register define indentation Marijn Suijten
2023-04-18 12:18 ` Konrad Dybcio
2023-04-20 0:46 ` Dmitry Baryshkov
2023-04-24 23:55 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 07/17] drm/msm/dpu: Sort INTF registers numerically Marijn Suijten
2023-04-18 12:18 ` Konrad Dybcio
2023-04-20 0:47 ` Dmitry Baryshkov
2023-04-20 21:47 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 08/17] drm/msm/dpu: Drop unused poll_timeout_wr_ptr PINGPONG callback Marijn Suijten
2023-04-18 12:19 ` Konrad Dybcio
2023-04-20 0:48 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 09/17] drm/msm/dpu: Move autorefresh disable from CMD encoder to pingpong Marijn Suijten
2023-04-20 0:49 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 10/17] drm/msm/dpu: Disable pingpong TE on DPU 5.0.0 and above Marijn Suijten
2023-04-18 12:48 ` Konrad Dybcio [this message]
2023-04-20 0:55 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 11/17] drm/msm/dpu: Disable MDP vsync source selection " Marijn Suijten
2023-04-20 1:00 ` Dmitry Baryshkov
2023-04-20 1:01 ` Konrad Dybcio
2023-04-20 1:03 ` Dmitry Baryshkov
2023-04-20 21:51 ` Marijn Suijten
2023-04-20 22:28 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 12/17] drm/msm/dpu: Move dpu_hw_{tear_check,pp_vsync_info} to dpu_hw_mdss.h Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 13/17] drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macro Marijn Suijten
2023-04-18 12:53 ` Konrad Dybcio
2023-04-20 1:02 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 14/17] drm/msm/dpu: Document and enable TEAR interrupts on DSI interfaces Marijn Suijten
2023-04-18 13:04 ` Konrad Dybcio
2023-04-20 1:11 ` Dmitry Baryshkov
2023-04-20 21:55 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 15/17] drm/msm/dpu: Merge setup_- and enable_tearcheck pingpong callbacks Marijn Suijten
2023-04-20 1:12 ` [Freedreno] " Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 16/17] drm/msm/dpu: Implement tearcheck support on INTF block Marijn Suijten
2023-04-20 1:14 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 17/17] drm/msm/dpu: Remove intr_rdptr from DPU >= 5.0.0 pingpong config Marijn Suijten
2023-04-18 13:16 ` Konrad Dybcio
2023-04-24 23:59 ` [PATCH v2 00/17] drm/msm/dpu: Implement tearcheck support on INTF block Abhinav Kumar
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