From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Marijn Suijten <marijn.suijten@somainline.org>,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Adam Skladowski <a39.skl@gmail.com>,
Loic Poulain <loic.poulain@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Kuogee Hsieh <quic_khsieh@quicinc.com>,
Robert Foss <rfoss@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Rajesh Yadav <ryadav@codeaurora.org>,
Jeykumar Sankaran <jsanka@codeaurora.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Chandan Uddaraju <chandanu@codeaurora.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Martin Botka <martin.botka@somainline.org>,
Jami Kettunen <jami.kettunen@somainline.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Jordan Crouse <jordan@cosmicpenguin.net>,
Archit Taneja <architt@codeaurora.org>,
Sravanthi Kollukuduru <skolluku@codeaurora.org>
Subject: Re: [PATCH v2 13/17] drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macro
Date: Tue, 18 Apr 2023 14:53:32 +0200 [thread overview]
Message-ID: <e377d8e4-9335-e9b8-6000-36a8f7d79e15@linaro.org> (raw)
In-Reply-To: <20230411-dpu-intf-te-v2-13-ef76c877eb97@somainline.org>
On 17.04.2023 22:21, Marijn Suijten wrote:
> As the INTF block is going to attain more interrupts that don't share
> the same MDP_SSPP_TOP0_INTR register, factor out the _reg argument for
> the caller to construct the right interrupt index (register and bit
> index) to not make the interrupt bit arguments depend on one of multiple
> interrupt register indices. This brings us more in line with how PP_BLK
> specifies its interrupts and allows for better wrapping in the arrays.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +++++++---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 16 +++++++---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 16 +++++++---
> .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 24 +++++++++++----
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 +++++++---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 +++--
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 6 ++--
> .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 ++--
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 +++++++---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 12 ++++++--
> .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 36 ++++++++++++++++------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 16 +++++++---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16 +++++++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ++--
> 14 files changed, 155 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 6906f8046b9e..c0dd4776f539 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -134,10 +134,18 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
> };
>
> static const struct dpu_intf_cfg msm8998_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_perf_cfg msm8998_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 14ce397800d5..b109757b0672 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -132,10 +132,18 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sdm845_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_perf_cfg sdm845_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 43cf813a4766..e0f62f84b3cf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -162,10 +162,18 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8150_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_perf_cfg sm8150_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 1313193f410b..fbcfbbd74875 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -143,13 +143,25 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
> };
>
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> - INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
> - INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
> + INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> };
>
> static const struct dpu_perf_cfg sc8180x_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index f8378990aa25..b63d244224f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -163,10 +163,18 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8250_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_wb_cfg sm8250_wb[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 68d1fb988b0d..9994b3aa1bb0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -85,8 +85,12 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
> };
>
> static const struct dpu_intf_cfg sc7180_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> };
>
> static const struct dpu_wb_cfg sc7180_wb[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index e15dc96f1286..88a0d6119ad5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -66,8 +66,10 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
> };
>
> static const struct dpu_intf_cfg sm6115_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0, 0),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> };
>
> static const struct dpu_perf_cfg sm6115_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 2ff98ef6999f..cd6f4048f286 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -63,8 +63,10 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
> };
>
> static const struct dpu_intf_cfg qcm2290_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0, 0),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> };
>
> static const struct dpu_perf_cfg qcm2290_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 6b7e1837422a..9b99ec6eb78d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -154,10 +154,18 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> };
>
> static const struct dpu_intf_cfg sm8350_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_perf_cfg sm8350_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 0961fa5c3907..56bd2ec8ca54 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -94,9 +94,15 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
> };
>
> static const struct dpu_intf_cfg sc7280_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> };
>
> static const struct dpu_perf_cfg sc7280_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index bad1c688517d..49fa6eda9c7d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -143,15 +143,33 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
>
> /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
> static const struct dpu_intf_cfg sc8280xp_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> - INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
> - INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> - INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
> - INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
> - INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
> + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> + INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17)),
> + INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19)),
> + INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> };
>
> static const struct dpu_perf_cfg sc8280xp_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index efd3aa6c9bc1..31fec8fc98f2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -162,10 +162,18 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> };
>
> static const struct dpu_intf_cfg sm8450_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_perf_cfg sm8450_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index d0ab351b6a8b..55c72419964d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -166,11 +166,19 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
> };
>
> static const struct dpu_intf_cfg sm8550_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> /* TODO TE sub-blocks for intf1 & intf2 */
> - INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> };
>
> static const struct dpu_perf_cfg sm8550_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 2d16cdbd7d44..d3eda7192908 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -543,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> -#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync) \
> {\
> .name = _name, .id = _id, \
> .base = _base, .len = _len, \
> @@ -551,8 +551,8 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> .type = _type, \
> .controller_id = _ctrl_id, \
> .prog_fetch_lines_worst_case = _progfetch, \
> - .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
> - .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
> + .intr_underrun = _underrun, \
> + .intr_vsync = _vsync, \
> }
>
> /*************************************************************
>
next prev parent reply other threads:[~2023-04-18 12:53 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 20:21 [PATCH v2 00/17] drm/msm/dpu: Implement tearcheck support on INTF block Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 01/17] drm/msm/dpu: Remove unused INTF0 interrupt mask from SM6115/QCM2290 Marijn Suijten
2023-04-20 0:34 ` Dmitry Baryshkov
2023-04-24 16:55 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 02/17] drm/msm/dpu: Remove TE2 block and feature from DPU >= 7.0.0 hardware Marijn Suijten
2023-04-18 12:16 ` Konrad Dybcio
2023-04-20 0:44 ` Dmitry Baryshkov
2023-04-24 20:41 ` Abhinav Kumar
2023-04-24 22:18 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 03/17] drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header Marijn Suijten
2023-04-18 12:16 ` Konrad Dybcio
2023-04-20 0:45 ` Dmitry Baryshkov
2023-04-24 20:44 ` Abhinav Kumar
2023-04-24 22:25 ` Marijn Suijten
2023-04-24 23:52 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 04/17] drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typo Marijn Suijten
2023-04-18 12:17 ` Konrad Dybcio
2023-04-20 0:46 ` Dmitry Baryshkov
2023-04-24 20:53 ` [Freedreno] " Abhinav Kumar
2023-04-24 22:30 ` Marijn Suijten
2023-04-24 23:09 ` Abhinav Kumar
2023-04-25 6:54 ` Marijn Suijten
2023-04-25 16:18 ` Abhinav Kumar
2023-04-25 16:33 ` Marijn Suijten
2023-04-25 16:47 ` Abhinav Kumar
2023-04-25 20:43 ` Marijn Suijten
2023-04-25 21:37 ` Abhinav Kumar
2023-04-25 21:53 ` Marijn Suijten
2023-04-25 21:55 ` Abhinav Kumar
2023-04-25 22:15 ` Marijn Suijten
2023-04-25 22:37 ` Abhinav Kumar
2023-04-25 23:13 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 05/17] drm/msm/dpu: Remove duplicate register defines from INTF Marijn Suijten
2023-04-18 12:17 ` Konrad Dybcio
2023-04-20 0:46 ` Dmitry Baryshkov
2023-04-24 23:54 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 06/17] drm/msm/dpu: Remove extraneous register define indentation Marijn Suijten
2023-04-18 12:18 ` Konrad Dybcio
2023-04-20 0:46 ` Dmitry Baryshkov
2023-04-24 23:55 ` Abhinav Kumar
2023-04-17 20:21 ` [PATCH v2 07/17] drm/msm/dpu: Sort INTF registers numerically Marijn Suijten
2023-04-18 12:18 ` Konrad Dybcio
2023-04-20 0:47 ` Dmitry Baryshkov
2023-04-20 21:47 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 08/17] drm/msm/dpu: Drop unused poll_timeout_wr_ptr PINGPONG callback Marijn Suijten
2023-04-18 12:19 ` Konrad Dybcio
2023-04-20 0:48 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 09/17] drm/msm/dpu: Move autorefresh disable from CMD encoder to pingpong Marijn Suijten
2023-04-20 0:49 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 10/17] drm/msm/dpu: Disable pingpong TE on DPU 5.0.0 and above Marijn Suijten
2023-04-18 12:48 ` Konrad Dybcio
2023-04-20 0:55 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 11/17] drm/msm/dpu: Disable MDP vsync source selection " Marijn Suijten
2023-04-20 1:00 ` Dmitry Baryshkov
2023-04-20 1:01 ` Konrad Dybcio
2023-04-20 1:03 ` Dmitry Baryshkov
2023-04-20 21:51 ` Marijn Suijten
2023-04-20 22:28 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 12/17] drm/msm/dpu: Move dpu_hw_{tear_check,pp_vsync_info} to dpu_hw_mdss.h Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 13/17] drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macro Marijn Suijten
2023-04-18 12:53 ` Konrad Dybcio [this message]
2023-04-20 1:02 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 14/17] drm/msm/dpu: Document and enable TEAR interrupts on DSI interfaces Marijn Suijten
2023-04-18 13:04 ` Konrad Dybcio
2023-04-20 1:11 ` Dmitry Baryshkov
2023-04-20 21:55 ` Marijn Suijten
2023-04-17 20:21 ` [PATCH v2 15/17] drm/msm/dpu: Merge setup_- and enable_tearcheck pingpong callbacks Marijn Suijten
2023-04-20 1:12 ` [Freedreno] " Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 16/17] drm/msm/dpu: Implement tearcheck support on INTF block Marijn Suijten
2023-04-20 1:14 ` Dmitry Baryshkov
2023-04-17 20:21 ` [PATCH v2 17/17] drm/msm/dpu: Remove intr_rdptr from DPU >= 5.0.0 pingpong config Marijn Suijten
2023-04-18 13:16 ` Konrad Dybcio
2023-04-24 23:59 ` [PATCH v2 00/17] drm/msm/dpu: Implement tearcheck support on INTF block Abhinav Kumar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e377d8e4-9335-e9b8-6000-36a8f7d79e15@linaro.org \
--to=konrad.dybcio@linaro.org \
--cc=a39.skl@gmail.com \
--cc=airlied@gmail.com \
--cc=andersson@kernel.org \
--cc=angelogioacchino.delregno@somainline.org \
--cc=architt@codeaurora.org \
--cc=chandanu@codeaurora.org \
--cc=daniel@ffwll.ch \
--cc=dmitry.baryshkov@linaro.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=jami.kettunen@somainline.org \
--cc=jordan@cosmicpenguin.net \
--cc=jsanka@codeaurora.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=loic.poulain@linaro.org \
--cc=marijn.suijten@somainline.org \
--cc=martin.botka@somainline.org \
--cc=neil.armstrong@linaro.org \
--cc=quic_abhinavk@quicinc.com \
--cc=quic_khsieh@quicinc.com \
--cc=rfoss@kernel.org \
--cc=robdclark@gmail.com \
--cc=ryadav@codeaurora.org \
--cc=sean@poorly.run \
--cc=skolluku@codeaurora.org \
--cc=vkoul@kernel.org \
--cc=~postmarketos/upstreaming@lists.sr.ht \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox