Re: [PATCH v3 2/8] drm/msm/dpu: program master INTF value

[Jessica Zhang <quic_jesszhan@quicinc.com>]

On 3/6/2025 10:24 PM, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> If several interfaces are being handled through a single CTL, a main
> ('master') INTF needs to be programmed into a separate register. Write
> corresponding value into that register.
> 
> Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 12 ++++++++++++
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  2 ++
>   2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index cef3bfaa4af82ebc55fb8cf76adef3075c7d73e3..21f4d403e3c278d83d7eaa6a7dd53f471d9e296d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -603,6 +603,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>   	DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
>   	DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
>   
> +	if (cfg->intf_master)
> +		DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0));
> +
>   	if (cfg->cdm)
>   		DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);
>   }
> @@ -645,6 +648,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>   {
>   	struct dpu_hw_blk_reg_map *c = &ctx->hw;
>   	u32 intf_active = 0;
> +	u32 intf_master = 0;
>   	u32 wb_active = 0;
>   	u32 cwb_active = 0;
>   	u32 merge3d_active = 0;
> @@ -672,6 +676,14 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>   		intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
>   		intf_active &= ~BIT(cfg->intf - INTF_0);
>   		DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
> +
> +		intf_master = DPU_REG_READ(c, CTL_INTF_MASTER);
> +
> +		/* Unset this intf as master, if it is the current master */
> +		if (intf_master == BIT(cfg->intf - INTF_0)) {
> +			DPU_DEBUG_DRIVER("Unsetting INTF_%d master\n", cfg->intf - INTF_0);
> +			DPU_REG_WRITE(c, CTL_INTF_MASTER, 0);
> +		}
>   	}
>   
>   	if (cfg->cwb) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 080a9550a0cc6530b4115165dd737857b6213d15..cea23436fc80a17a679363a47f9f287b72623a1c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg {
>   /**
>    * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
>    * @intf :                 Interface id
> + * @intf_master:           Master interface id in the dual pipe topology
>    * @mode_3d:               3d mux configuration
>    * @merge_3d:              3d merge block used
>    * @intf_mode_sel:         Interface mode, cmd / vid
> @@ -46,6 +47,7 @@ struct dpu_hw_stage_cfg {
>    */
>   struct dpu_hw_intf_cfg {
>   	enum dpu_intf intf;
> +	enum dpu_intf intf_master;
>   	enum dpu_wb wb;
>   	enum dpu_3d_blend_mode mode_3d;
>   	enum dpu_merge_3d merge_3d;
>