From: Neil Armstrong <neil.armstrong@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents
Date: Tue, 2 May 2023 10:38:49 +0200 [thread overview]
Message-ID: <68144145-123e-9676-839b-28e7db5bc2bd@linaro.org> (raw)
In-Reply-To: <20230501203401.41393-5-dmitry.baryshkov@linaro.org>
On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/clk/qcom/gcc-mdm9615.c | 42 +++++++++++++++++-----------------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index 8bed02a748ab..fb5c1244fb97 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi1_uart_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi2_uart_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi3_uart_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi4_uart_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi5_uart_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi1_qup_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi2_qup_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi3_qup_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi4_qup_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gsbi5_qup_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gp0_src",
> .parent_names = gcc_cxo,
> - .num_parents = 1,
> + .num_parents = ARRAY_SIZE(gcc_cxo),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_PARENT_GATE,
> },
> @@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gp1_src",
> .parent_names = gcc_cxo,
> - .num_parents = 1,
> + .num_parents = ARRAY_SIZE(gcc_cxo),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = {
> .hw.init = &(struct clk_init_data){
> .name = "gp2_src",
> .parent_names = gcc_cxo,
> - .num_parents = 1,
> + .num_parents = ARRAY_SIZE(gcc_cxo),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -875,7 +875,7 @@ static struct clk_rcg prng_src = {
> .hw.init = &(struct clk_init_data){
> .name = "prng_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> },
> },
> @@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = {
> .hw.init = &(struct clk_init_data){
> .name = "sdc1_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> },
> }
> @@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = {
> .hw.init = &(struct clk_init_data){
> .name = "sdc2_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> },
> }
> @@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
> .hw.init = &(struct clk_init_data){
> .name = "usb_hs1_xcvr_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
> .hw.init = &(struct clk_init_data){
> .name = "usb_hsic_xcvr_fs_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = {
> .hw.init = &(struct clk_init_data){
> .name = "usb_hs1_system_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = {
> .hw.init = &(struct clk_init_data){
> .name = "usb_hsic_system_src",
> .parent_names = gcc_cxo_pll8,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
> .hw.init = &(struct clk_init_data){
> .name = "usb_hsic_hsic_src",
> .parent_names = gcc_cxo_pll14,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_cxo_pll14),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
next prev parent reply other threads:[~2023-05-02 8:39 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
2023-05-01 20:33 ` [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Dmitry Baryshkov
2023-05-02 6:58 ` Krzysztof Kozlowski
2023-05-01 20:33 ` [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file Dmitry Baryshkov
2023-05-02 7:05 ` Krzysztof Kozlowski
2023-05-01 20:33 ` [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615 Dmitry Baryshkov
2023-05-02 6:59 ` Krzysztof Kozlowski
2023-05-01 20:33 ` [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2023-05-02 8:38 ` Neil Armstrong [this message]
2023-05-01 20:33 ` [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 Dmitry Baryshkov
2023-05-02 8:38 ` Neil Armstrong
2023-05-01 20:33 ` [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Dmitry Baryshkov
2023-05-02 8:36 ` Neil Armstrong
2023-05-02 11:15 ` Konrad Dybcio
2023-05-02 12:16 ` Dmitry Baryshkov
2023-05-01 20:33 ` [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2023-05-02 8:38 ` Neil Armstrong
2023-05-02 11:15 ` Konrad Dybcio
2023-05-02 11:23 ` Dmitry Baryshkov
2023-05-02 11:45 ` Konrad Dybcio
2023-05-02 12:20 ` Dmitry Baryshkov
2023-05-04 8:00 ` Konrad Dybcio
2023-05-01 20:33 ` [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock Dmitry Baryshkov
2023-05-02 8:36 ` Neil Armstrong
2023-05-01 20:34 ` [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device Dmitry Baryshkov
2023-05-02 8:36 ` Neil Armstrong
2023-05-01 20:34 ` [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Dmitry Baryshkov
2023-05-02 8:37 ` Neil Armstrong
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