From: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>
Cc: Stephen Boyd <swboyd@chromium.org>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
<linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>
Subject: Re: [PATCH 14/25] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
Date: Fri, 13 May 2022 11:50:49 -0700 [thread overview]
Message-ID: <952f224a-e3a3-0f17-cd06-23b019b39346@quicinc.com> (raw)
In-Reply-To: <20220209172520.3719906-15-dmitry.baryshkov@linaro.org>
On 2/9/2022 9:25 AM, Dmitry Baryshkov wrote:
> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
> dpu_hw_sspp_setup_rects() programs only source and destination
> rectangles.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This separation is logically correct, but there is another codepath
using this.
_dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
So for solid fill, I presume that stride getting programmed is 0 as
there is no buffer to fetch from.
But with this separation, we will miss re-programming stride and it will
remain at the old value even for solid fil cases?
You might want to add setup_sourceaddress call there? But that wont make
sense either because for solid fill there is nothing to fetch from.
Perhaps, another op for stride programming then?
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
> 1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 7194c14f87bc..2186506e6315 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> {
> struct dpu_hw_pipe *ctx = pipe->sspp;
> struct dpu_hw_blk_reg_map *c;
> - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
> + u32 src_size, src_xy, dst_size, dst_xy;
> u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
> u32 idx;
>
> @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> drm_rect_width(&cfg->dst_rect);
>
> - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - ystride0 = (cfg->layout.plane_pitch[0]) |
> - (cfg->layout.plane_pitch[1] << 16);
> - ystride1 = (cfg->layout.plane_pitch[2]) |
> - (cfg->layout.plane_pitch[3] << 16);
> - } else {
> - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
> - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
> -
> - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> - ystride0 = (ystride0 & 0xFFFF0000) |
> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> - ystride1 = (ystride1 & 0xFFFF0000)|
> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> - } else {
> - ystride0 = (ystride0 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[0] << 16) &
> - 0xFFFF0000);
> - ystride1 = (ystride1 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[2] << 16) &
> - 0xFFFF0000);
> - }
> - }
> -
> /* rectangle register programming */
> DPU_REG_WRITE(c, src_size_off + idx, src_size);
> DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
> DPU_REG_WRITE(c, out_size_off + idx, dst_size);
> DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
> -
> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> struct dpu_hw_pipe_cfg *cfg)
> {
> struct dpu_hw_pipe *ctx = pipe->sspp;
> + u32 ystride0, ystride1;
> int i;
> u32 idx;
>
> @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> cfg->layout.plane_addr[2]);
> }
> +
> + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> + ystride0 = (cfg->layout.plane_pitch[0]) |
> + (cfg->layout.plane_pitch[1] << 16);
> + ystride1 = (cfg->layout.plane_pitch[2]) |
> + (cfg->layout.plane_pitch[3] << 16);
> + } else {
> + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> +
> + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> + ystride0 = (ystride0 & 0xFFFF0000) |
> + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> + ystride1 = (ystride1 & 0xFFFF0000)|
> + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> + } else {
> + ystride0 = (ystride0 & 0x0000FFFF) |
> + ((cfg->layout.plane_pitch[0] << 16) &
> + 0xFFFF0000);
> + ystride1 = (ystride1 & 0x0000FFFF) |
> + ((cfg->layout.plane_pitch[2] << 16) &
> + 0xFFFF0000);
> + }
> + }
> +
> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
next prev parent reply other threads:[~2022-05-13 18:51 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 17:24 [PATCH 00/25] drm/msm/dpu: wide planes support Dmitry Baryshkov
2022-02-09 17:24 ` [PATCH 01/25] drm/msm/dpu: rip out master " Dmitry Baryshkov
2022-04-27 1:28 ` Abhinav Kumar
2022-02-09 17:24 ` [PATCH 02/25] drm/msm/dpu: do not limit the zpos property Dmitry Baryshkov
2022-04-27 1:32 ` Abhinav Kumar
2022-02-09 17:24 ` [PATCH 03/25] drm/msm/dpu: add support for SSPP allocation to RM Dmitry Baryshkov
2022-04-27 2:06 ` Abhinav Kumar
2022-02-09 17:24 ` [PATCH 04/25] drm/msm/dpu: move SSPP debugfs creation to dpu_kms.c Dmitry Baryshkov
2022-05-03 21:34 ` Abhinav Kumar
2022-05-03 22:11 ` Dmitry Baryshkov
2022-05-03 22:34 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 05/25] drm/msm/dpu: move pipe_hw to dpu_plane_state Dmitry Baryshkov
2022-05-03 22:32 ` Abhinav Kumar
2022-05-14 6:37 ` Dmitry Baryshkov
2022-05-26 20:21 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 06/25] drm/msm/dpu: inline dpu_plane_get_ctl_flush Dmitry Baryshkov
2022-05-03 22:55 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 07/25] drm/msm/dpu: drop dpu_plane_pipe function Dmitry Baryshkov
2022-05-03 23:04 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 08/25] drm/msm/dpu: get rid of cached flush_mask Dmitry Baryshkov
2022-05-03 23:40 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 09/25] drm/msm/dpu: dpu_crtc_blend_setup: split mixer and ctl logic Dmitry Baryshkov
2022-05-06 18:56 ` Abhinav Kumar
2022-05-06 20:14 ` Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 10/25] drm/msm/dpu: introduce struct dpu_sw_pipe Dmitry Baryshkov
2022-05-06 21:30 ` Abhinav Kumar
2022-05-06 21:39 ` Dmitry Baryshkov
2022-05-06 21:48 ` [Freedreno] " Abhinav Kumar
2022-05-06 22:29 ` Dmitry Baryshkov
2022-05-06 22:46 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 11/25] drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks Dmitry Baryshkov
2022-05-06 22:24 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 12/25] drm/msm/dpu: inline _dpu_plane_set_scanout Dmitry Baryshkov
2022-05-06 23:33 ` Abhinav Kumar
2022-05-06 23:34 ` Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 13/25] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3() Dmitry Baryshkov
2022-05-09 22:30 ` Abhinav Kumar
2022-05-14 6:46 ` Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 14/25] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress Dmitry Baryshkov
2022-05-13 18:50 ` Abhinav Kumar [this message]
2022-02-09 17:25 ` [PATCH 15/25] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg Dmitry Baryshkov
2022-05-13 18:58 ` Abhinav Kumar
2022-05-14 6:53 ` Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 16/25] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout Dmitry Baryshkov
2022-05-13 19:03 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 17/25] drm/msm/dpu: drop src_split and multirect check from dpu_crtc_atomic_check Dmitry Baryshkov
2022-05-26 22:59 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 18/25] drm/msm/dpu: move the rest of plane checks to dpu_plane_atomic_check() Dmitry Baryshkov
2022-05-27 0:14 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 19/25] drm/msm/dpu: don't use unsupported blend stages Dmitry Baryshkov
2022-05-14 1:57 ` Abhinav Kumar
2022-02-09 17:25 ` [PATCH 20/25] drm/msm/dpu: add dpu_hw_pipe_cfg to dpu_plane_state Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 21/25] drm/msm/dpu: simplify dpu_plane_validate_src() Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 22/25] drm/msm/dpu: rewrite plane's QoS-related functions to take dpu_sw_pipe and dpu_format Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 23/25] drm/msm/dpu: rework dpu_plane_atomic_check() and dpu_plane_sspp_atomic_update() Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 24/25] drm/msm/dpu: populate SmartDMA features in hw catalog Dmitry Baryshkov
2022-02-09 17:25 ` [PATCH 25/25] drm/msm/dpu: add support for wide planes Dmitry Baryshkov
2022-03-17 1:10 ` [PATCH 00/25] drm/msm/dpu: wide planes support Abhinav Kumar
2022-03-17 7:59 ` Dmitry Baryshkov
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