[PATCH v3 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes

[PATCH v3 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes

[Sushrut Shree Trivedi]

Add nodes for the two additional TC9563 PCIe switches present on the
QCOM RB3Gen2 Industrial Mezzanine platform.

One of the TC9563 is connected directly to the PCIe0 root-port while
the second TC9563 switch is connected in cascade fashion to another
already available TC9563 switch on PCIe1 via the former's downstream
port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
would look something like below:

                   ┌────────────────────────────┐                                      
                   │                            │                                      
                   │                            │                                      
                   │                            │                                      
                   │            SoC             │                                      
                   │                            │                                      
                   │    PCIe0           PCIe1   │                                      
                   │    ┌───┐           ┌───┐   │                                      
                   └────└─┬─┘───────────└─┬─┘───┘                                      
                          │               │                                            
                          │               │                                            
                          │               │                                            
         ┌────────────────┘               └────────────────┐                           
         │                                                 │                           
         │                                                 │                           
         │                                                 │                           
┌────────┴─────────┐                            ┌──────────┴───────┐                   
│       USP        │                            │        USP       │                   
│                  │                            │                  │                   
│      TC9563      │                            │      TC9563      │                   
│                  │                            │                  │                   
│                  │                            │                  │                   
│ DSP1  DSP2  DSP3 │                            │ DSP1  DSP2  DSP3 │                   
└──┬──────┬─────┬──┘                            └───┬─────┬─────┬──┘                   
   │      │     │                                   │     │     │                      
   │      │     │                                   │     │     │                      
   │      │     │                                   │     │     │                      
   │      │     │                                   │     EP    ETHERNET               
   │      │     │                                   │                                  
   │      │     │                                   └──────┐                           
   EP     EP    ETHERNET                                   │                           
                                                           │                           
                                                           │                           
                                                 ┌─────────┴────────┐                  
                                                 │        USP       │                  
                                                 │                  │                  
                                                 │      TC9563      │                  
                                                 │                  │                  
                                                 │                  │                  
                                                 │ DSP1  DSP2  DSP3 │                  
                                                 └──┬──────┬─────┬──┘                  
                                                    │      │     │                     
                                                    │      │     │                     
                                                    │      │     │                     
                                                    │      │     │                     
                                                    │      │     │                     
                                                    EP     EP    ETHERNET              
                                                                                       
                                                                                       

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
Changes in v3:
- Fixed DT binding errors.
- Removed labels from unused TC9563 switch ports. (Konrad)
- Sort nodes in alphabetical order. (Dmitry)
- Fixed styling issues (Konrad)
- Link to v2: https://lore.kernel.org/r/20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com

Changes in v2:
- Posted as v2 by error. Please consider as v1.

---
Sushrut Shree Trivedi (2):
      arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
      arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

 .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 250 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts       |   2 +-
 2 files changed, 251 insertions(+), 1 deletion(-)
---
base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04

Best regards,
-- 
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

[PATCH v3 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0

[Sushrut Shree Trivedi]

Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. All the ports present in the
node represent the downstream ports and embedded endpoints.

Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 145 +++++++++++++++++++++
 1 file changed, 145 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 619a42b5ef48..0fb89e71bf7f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -5,9 +5,45 @@
 
 /dts-v1/;
 /plugin/;
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 
+&{/} {
+
+	vreg_0p9: regulator-vreg-0p9 {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_0P9";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vreg_dc_12v>;
+	};
+
+	vreg_1p8: regulator-vreg-1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vreg_dc_12v>;
+	};
+
+	vreg_dc_12v: regulator-vreg-dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_DC_12V";
+		regulator-min-microvolt = <24000000>;
+		regulator-max-microvolt = <24000000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
 &spi11 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -19,3 +55,112 @@ st33htpm0: tpm@0 {
 		spi-max-frequency = <20000000>;
 	};
 };
+
+&pcie0 {
+	iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+		    <0x100 &apps_smmu 0x1c01 0x1>,
+		    <0x208 &apps_smmu 0x1c04 0x1>,
+		    <0x210 &apps_smmu 0x1c05 0x1>,
+		    <0x218 &apps_smmu 0x1c06 0x1>,
+		    <0x300 &apps_smmu 0x1c07 0x1>,
+		    <0x400 &apps_smmu 0x1c08 0x1>,
+		    <0x500 &apps_smmu 0x1c09 0x1>,
+		    <0x501 &apps_smmu 0x1c10 0x1>;
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l10c_0p88>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
+&pcie0_port {
+	#address-cells = <3>;
+	#size-cells = <2>;
+
+	pcie@0,0 {
+		compatible = "pci1179,0623";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		device_type = "pci";
+		ranges;
+		bus-range = <0x2 0xff>;
+
+		vddc-supply = <&vreg_0p9>;
+		vdd18-supply = <&vreg_1p8>;
+		vdd09-supply = <&vreg_0p9>;
+		vddio1-supply = <&vreg_1p8>;
+		vddio2-supply = <&vreg_1p8>;
+		vddio18-supply = <&vreg_1p8>;
+
+		i2c-parent = <&i2c1 0x77>;
+
+		resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&pcie0_tc9563_resx_n>;
+		pinctrl-names = "default";
+
+		pcie@1,0 {
+			reg = <0x20800 0x0 0x0 0x0 0x0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			ranges;
+			bus-range = <0x3 0xff>;
+		};
+
+		pcie@2,0 {
+			reg = <0x21000 0x0 0x0 0x0 0x0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			ranges;
+			bus-range = <0x4 0xff>;
+		};
+
+		pcie@3,0 {
+			reg = <0x21800 0x0 0x0 0x0 0x0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges;
+			bus-range = <0x5 0xff>;
+
+			pci@0,0 {
+				reg = <0x50000 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				ranges;
+			};
+
+			pci@0,1 {
+				reg = <0x50100 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				ranges;
+			};
+		};
+
+	};
+};
+
+&tlmm {
+	pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
+		pins = "gpio78";
+		function = "gpio";
+
+		bias-disable;
+		input-disable;
+		output-enable;
+		power-source = <0>;
+	};
+};

-- 
2.25.1

[PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Sushrut Shree Trivedi]

Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
in cascade to the first TC9563 switch via the former's downstream port.

Two embedded Ethernet devices are present on one of the downstream
ports of this second switch as well. All the ports present in the
node represent the downstream ports and embedded endpoints.

The second TC9563 is powered up via the same LDO regulators as the first
one, and these can be controlled via two GPIOs, which are already present
as fixed regulators. This TC9563 can also be configured through I2C.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 105 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts       |   2 +-
 2 files changed, 106 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 0fb89e71bf7f..a8ccb9d8f6e2 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -153,6 +153,100 @@ pci@0,1 {
 	};
 };
 
+&pcie1 {
+	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+		    <0x100 &apps_smmu 0x1c81 0x1>,
+		    <0x208 &apps_smmu 0x1c84 0x1>,
+		    <0x210 &apps_smmu 0x1c85 0x1>,
+		    <0x218 &apps_smmu 0x1c86 0x1>,
+		    <0x300 &apps_smmu 0x1c87 0x1>,
+		    <0x408 &apps_smmu 0x1c90 0x1>,
+		    <0x410 &apps_smmu 0x1c91 0x1>,
+		    <0x418 &apps_smmu 0x1c92 0x1>,
+		    <0x500 &apps_smmu 0x1c93 0x1>,
+		    <0x600 &apps_smmu 0x1c94 0x1>,
+		    <0x700 &apps_smmu 0x1c95 0x1>,
+		    <0x701 &apps_smmu 0x1c96 0x1>,
+		    <0x800 &apps_smmu 0x1c97 0x1>,
+		    <0x900 &apps_smmu 0x1c98 0x1>,
+		    <0x901 &apps_smmu 0x1c99 0x1>;
+};
+
+&pcie1_switch0_dsp1 {
+	#address-cells = <3>;
+	#size-cells = <2>;
+
+	pcie@0,0 {
+		compatible = "pci1179,0623";
+		reg = <0x30000 0x0 0x0 0x0 0x0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		device_type = "pci";
+		ranges;
+		bus-range = <0x2 0xff>;
+
+		vddc-supply = <&vdd_ntn_0p9>;
+		vdd18-supply = <&vdd_ntn_1p8>;
+		vdd09-supply = <&vdd_ntn_0p9>;
+		vddio1-supply = <&vdd_ntn_1p8>;
+		vddio2-supply = <&vdd_ntn_1p8>;
+		vddio18-supply = <&vdd_ntn_1p8>;
+
+		i2c-parent = <&i2c1 0x33>;
+
+		resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&pcie1_tc9563_resx_n>;
+		pinctrl-names = "default";
+
+		pcie@1,0 {
+			reg = <0x40800 0x0 0x0 0x0 0x0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			ranges;
+			bus-range = <0x3 0xff>;
+		};
+
+		pcie@2,0 {
+			reg = <0x41000 0x0 0x0 0x0 0x0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			ranges;
+			bus-range = <0x4 0xff>;
+		};
+
+		pcie@3,0 {
+			reg = <0x41800 0x0 0x0 0x0 0x0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges;
+			bus-range = <0x5 0xff>;
+
+			pci@0,0 {
+				reg = <0x50000 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				ranges;
+			};
+
+			pci@0,1 {
+				reg = <0x50100 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				ranges;
+			};
+		};
+	};
+};
+
 &tlmm {
 	pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
 		pins = "gpio78";
@@ -163,4 +257,15 @@ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
 		output-enable;
 		power-source = <0>;
 	};
+
+	pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
+		pins = "gpio124";
+		function = "gpio";
+
+		bias-disable;
+		input-disable;
+		output-enable;
+		power-source = <0>;
+	};
+
 };
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e3d2f01881ae..cd54525e45e0 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -852,7 +852,7 @@ pcie@0,0 {
 		pinctrl-0 = <&tc9563_resx_n>;
 		pinctrl-names = "default";
 
-		pcie@1,0 {
+		pcie1_switch0_dsp1: pcie@1,0 {
 			reg = <0x20800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
 			#size-cells = <2>;

-- 
2.25.1

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Konrad Dybcio]

On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
> in cascade to the first TC9563 switch via the former's downstream port.
> 
> Two embedded Ethernet devices are present on one of the downstream
> ports of this second switch as well. All the ports present in the
> node represent the downstream ports and embedded endpoints.
> 
> The second TC9563 is powered up via the same LDO regulators as the first
> one, and these can be controlled via two GPIOs, which are already present
> as fixed regulators. This TC9563 can also be configured through I2C.
> 
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---

> +&pcie1 {
> +	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> +		    <0x100 &apps_smmu 0x1c81 0x1>,
> +		    <0x208 &apps_smmu 0x1c84 0x1>,
> +		    <0x210 &apps_smmu 0x1c85 0x1>,
> +		    <0x218 &apps_smmu 0x1c86 0x1>,
> +		    <0x300 &apps_smmu 0x1c87 0x1>,
> +		    <0x408 &apps_smmu 0x1c90 0x1>,
> +		    <0x410 &apps_smmu 0x1c91 0x1>,
> +		    <0x418 &apps_smmu 0x1c92 0x1>,
> +		    <0x500 &apps_smmu 0x1c93 0x1>,
> +		    <0x600 &apps_smmu 0x1c94 0x1>,
> +		    <0x700 &apps_smmu 0x1c95 0x1>,
> +		    <0x701 &apps_smmu 0x1c96 0x1>,
> +		    <0x800 &apps_smmu 0x1c97 0x1>,
> +		    <0x900 &apps_smmu 0x1c98 0x1>,
> +		    <0x901 &apps_smmu 0x1c99 0x1>;

This map is not just an extension of the existing one - is that
intentional?

Konrad

Re: [PATCH v3 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0

[Konrad Dybcio]

On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
> Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
> has three downstream ports.Two embedded Ethernet devices are present
> on one of the downstream ports. All the ports present in the
> node represent the downstream ports and embedded endpoints.
> 
> Power to the TC9563 is supplied through two LDO regulators, which
> are on by default and are added as fixed regulators. TC9563 can be
> configured through I2C.
> 
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---

[...]

> +
> +&tlmm {
> +	pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
> +		pins = "gpio78";
> +		function = "gpio";
> +
> +		bias-disable;

In case you're going to respin, please drop the blank line in both patches

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v3 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes

[Konrad Dybcio]

On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
> Add nodes for the two additional TC9563 PCIe switches present on the
> QCOM RB3Gen2 Industrial Mezzanine platform.
> 
> One of the TC9563 is connected directly to the PCIe0 root-port while
> the second TC9563 switch is connected in cascade fashion to another
> already available TC9563 switch on PCIe1 via the former's downstream
> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
	^ +Mani is that PCIe terminology, or is that a Toshiba-ism?

Konrad

Re: [PATCH v3 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0

[Dmitry Baryshkov]

On Thu, Feb 12, 2026 at 04:14:01PM +0530, Sushrut Shree Trivedi wrote:
> Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
> has three downstream ports.Two embedded Ethernet devices are present
> on one of the downstream ports. All the ports present in the
> node represent the downstream ports and embedded endpoints.
> 
> Power to the TC9563 is supplied through two LDO regulators, which
> are on by default and are added as fixed regulators. TC9563 can be
> configured through I2C.
> 
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
>  .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 145 +++++++++++++++++++++
>  1 file changed, 145 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Sushrut Shree Trivedi]

On 2/12/2026 5:16 PM, Konrad Dybcio wrote:
> On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
>> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
>> in cascade to the first TC9563 switch via the former's downstream port.
>>
>> Two embedded Ethernet devices are present on one of the downstream
>> ports of this second switch as well. All the ports present in the
>> node represent the downstream ports and embedded endpoints.
>>
>> The second TC9563 is powered up via the same LDO regulators as the first
>> one, and these can be controlled via two GPIOs, which are already present
>> as fixed regulators. This TC9563 can also be configured through I2C.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
>> +&pcie1 {
>> +	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
>> +		    <0x100 &apps_smmu 0x1c81 0x1>,
>> +		    <0x208 &apps_smmu 0x1c84 0x1>,
>> +		    <0x210 &apps_smmu 0x1c85 0x1>,
>> +		    <0x218 &apps_smmu 0x1c86 0x1>,
>> +		    <0x300 &apps_smmu 0x1c87 0x1>,
>> +		    <0x408 &apps_smmu 0x1c90 0x1>,
>> +		    <0x410 &apps_smmu 0x1c91 0x1>,
>> +		    <0x418 &apps_smmu 0x1c92 0x1>,
>> +		    <0x500 &apps_smmu 0x1c93 0x1>,
>> +		    <0x600 &apps_smmu 0x1c94 0x1>,
>> +		    <0x700 &apps_smmu 0x1c95 0x1>,
>> +		    <0x701 &apps_smmu 0x1c96 0x1>,
>> +		    <0x800 &apps_smmu 0x1c97 0x1>,
>> +		    <0x900 &apps_smmu 0x1c98 0x1>,
>> +		    <0x901 &apps_smmu 0x1c99 0x1>;
> This map is not just an extension of the existing one - is that
> intentional?
Yeah, I created a new map just for readability. Should I instead just 
add new mappings
and keep the older core-kit map intact ?
>
> Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Konrad Dybcio]

On 2/15/26 3:19 PM, Sushrut Shree Trivedi wrote:
> 
> On 2/12/2026 5:16 PM, Konrad Dybcio wrote:
>> On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
>>> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
>>> in cascade to the first TC9563 switch via the former's downstream port.
>>>
>>> Two embedded Ethernet devices are present on one of the downstream
>>> ports of this second switch as well. All the ports present in the
>>> node represent the downstream ports and embedded endpoints.
>>>
>>> The second TC9563 is powered up via the same LDO regulators as the first
>>> one, and these can be controlled via two GPIOs, which are already present
>>> as fixed regulators. This TC9563 can also be configured through I2C.
>>>
>>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>>> ---
>>> +&pcie1 {
>>> +    iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
>>> +            <0x100 &apps_smmu 0x1c81 0x1>,
>>> +            <0x208 &apps_smmu 0x1c84 0x1>,
>>> +            <0x210 &apps_smmu 0x1c85 0x1>,
>>> +            <0x218 &apps_smmu 0x1c86 0x1>,
>>> +            <0x300 &apps_smmu 0x1c87 0x1>,
>>> +            <0x408 &apps_smmu 0x1c90 0x1>,
>>> +            <0x410 &apps_smmu 0x1c91 0x1>,
>>> +            <0x418 &apps_smmu 0x1c92 0x1>,
>>> +            <0x500 &apps_smmu 0x1c93 0x1>,
>>> +            <0x600 &apps_smmu 0x1c94 0x1>,
>>> +            <0x700 &apps_smmu 0x1c95 0x1>,
>>> +            <0x701 &apps_smmu 0x1c96 0x1>,
>>> +            <0x800 &apps_smmu 0x1c97 0x1>,
>>> +            <0x900 &apps_smmu 0x1c98 0x1>,
>>> +            <0x901 &apps_smmu 0x1c99 0x1>;
>> This map is not just an extension of the existing one - is that
>> intentional?
> Yeah, I created a new map just for readability. Should I instead just add new mappings
> and keep the older core-kit map intact ?

Quite frankly, I don't know. I that against the "base" it's missing:

0x400
0x501

so presumably the second DSP and an endpoint for the primary switch's
ethernet port?

Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Sushrut Shree Trivedi]

On 2/16/2026 4:58 PM, Konrad Dybcio wrote:
> On 2/15/26 3:19 PM, Sushrut Shree Trivedi wrote:
>> On 2/12/2026 5:16 PM, Konrad Dybcio wrote:
>>> On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
>>>> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
>>>> in cascade to the first TC9563 switch via the former's downstream port.
>>>>
>>>> Two embedded Ethernet devices are present on one of the downstream
>>>> ports of this second switch as well. All the ports present in the
>>>> node represent the downstream ports and embedded endpoints.
>>>>
>>>> The second TC9563 is powered up via the same LDO regulators as the first
>>>> one, and these can be controlled via two GPIOs, which are already present
>>>> as fixed regulators. This TC9563 can also be configured through I2C.
>>>>
>>>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>>>> ---
>>>> +&pcie1 {
>>>> +    iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
>>>> +            <0x100 &apps_smmu 0x1c81 0x1>,
>>>> +            <0x208 &apps_smmu 0x1c84 0x1>,
>>>> +            <0x210 &apps_smmu 0x1c85 0x1>,
>>>> +            <0x218 &apps_smmu 0x1c86 0x1>,
>>>> +            <0x300 &apps_smmu 0x1c87 0x1>,
>>>> +            <0x408 &apps_smmu 0x1c90 0x1>,
>>>> +            <0x410 &apps_smmu 0x1c91 0x1>,
>>>> +            <0x418 &apps_smmu 0x1c92 0x1>,
>>>> +            <0x500 &apps_smmu 0x1c93 0x1>,
>>>> +            <0x600 &apps_smmu 0x1c94 0x1>,
>>>> +            <0x700 &apps_smmu 0x1c95 0x1>,
>>>> +            <0x701 &apps_smmu 0x1c96 0x1>,
>>>> +            <0x800 &apps_smmu 0x1c97 0x1>,
>>>> +            <0x900 &apps_smmu 0x1c98 0x1>,
>>>> +            <0x901 &apps_smmu 0x1c99 0x1>;
>>> This map is not just an extension of the existing one - is that
>>> intentional?
>> Yeah, I created a new map just for readability. Should I instead just add new mappings
>> and keep the older core-kit map intact ?
> Quite frankly, I don't know. I that against the "base" it's missing:
>
> 0x400
> 0x501
>
> so presumably the second DSP and an endpoint for the primary switch's
> ethernet port?
Since PCIe enumeration happens in a Depth-First Search manner, bus numbers
3 to 7 are alloted to the cascade switch connected to DSP1 of primary 
switch.
Bus no.'s 8 and 9 are alloted to DSP2 endpoint and embedded ethernet EP
respectively, on the primary switch.

So, in the cascade hierarchy, bus no. 4 is alloted to Cascade switch DSP's.
There is no DSP with device no. 0 so BDF 0x400 doesn't exist and is
omitted. For the same reason, BDF 0x200 on the primary switch is also
not mapped.

BDF 0x501 in single switch case maps to the ethernet EP. In cascade,
that EP is being mapped to 0x901.

Lspci (single switch):
sh-5.2# lspci
0001:00:00.0 PCI bridge: Qualcomm Technologies, Inc SM8250 PCIe RC
0001:01:00.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:01.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:02.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:03.0 PCI bridge: Toshiba Corporation Device 0623
0001:05:00.0 Ethernet controller: Toshiba Corporation Device 0220
0001:05:00.1 Ethernet controller: Toshiba Corporation Device 0220

Lspci (cascade switch):
0001:00:00.0 PCI bridge: Qualcomm Technologies, Inc SM8250 PCIe RC
0001:01:00.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:01.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:02.0 PCI bridge: Toshiba Corporation Device 0623
0001:02:03.0 PCI bridge: Toshiba Corporation Device 0623
0001:03:00.0 PCI bridge: Toshiba Corporation Device 0623
0001:04:01.0 PCI bridge: Toshiba Corporation Device 0623
0001:04:02.0 PCI bridge: Toshiba Corporation Device 0623
0001:04:03.0 PCI bridge: Toshiba Corporation Device 0623
0001:07:00.0 Ethernet controller: Toshiba Corporation Device 0220
0001:07:00.1 Ethernet controller: Toshiba Corporation Device 0220
0001:09:00.0 Ethernet controller: Toshiba Corporation Device 0220
0001:09:00.1 Ethernet controller: Toshiba Corporation Device 0220

Sushrut
>
> Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Konrad Dybcio]

On 2/18/26 11:00 AM, Sushrut Shree Trivedi wrote:
> 
> On 2/16/2026 4:58 PM, Konrad Dybcio wrote:
>> On 2/15/26 3:19 PM, Sushrut Shree Trivedi wrote:
>>> On 2/12/2026 5:16 PM, Konrad Dybcio wrote:
>>>> On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
>>>>> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
>>>>> in cascade to the first TC9563 switch via the former's downstream port.
>>>>>
>>>>> Two embedded Ethernet devices are present on one of the downstream
>>>>> ports of this second switch as well. All the ports present in the
>>>>> node represent the downstream ports and embedded endpoints.
>>>>>
>>>>> The second TC9563 is powered up via the same LDO regulators as the first
>>>>> one, and these can be controlled via two GPIOs, which are already present
>>>>> as fixed regulators. This TC9563 can also be configured through I2C.
>>>>>
>>>>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>>>>> ---
>>>>> +&pcie1 {
>>>>> +    iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
>>>>> +            <0x100 &apps_smmu 0x1c81 0x1>,
>>>>> +            <0x208 &apps_smmu 0x1c84 0x1>,
>>>>> +            <0x210 &apps_smmu 0x1c85 0x1>,
>>>>> +            <0x218 &apps_smmu 0x1c86 0x1>,
>>>>> +            <0x300 &apps_smmu 0x1c87 0x1>,
>>>>> +            <0x408 &apps_smmu 0x1c90 0x1>,
>>>>> +            <0x410 &apps_smmu 0x1c91 0x1>,
>>>>> +            <0x418 &apps_smmu 0x1c92 0x1>,
>>>>> +            <0x500 &apps_smmu 0x1c93 0x1>,
>>>>> +            <0x600 &apps_smmu 0x1c94 0x1>,
>>>>> +            <0x700 &apps_smmu 0x1c95 0x1>,
>>>>> +            <0x701 &apps_smmu 0x1c96 0x1>,
>>>>> +            <0x800 &apps_smmu 0x1c97 0x1>,
>>>>> +            <0x900 &apps_smmu 0x1c98 0x1>,
>>>>> +            <0x901 &apps_smmu 0x1c99 0x1>;
>>>> This map is not just an extension of the existing one - is that
>>>> intentional?
>>> Yeah, I created a new map just for readability. Should I instead just add new mappings
>>> and keep the older core-kit map intact ?
>> Quite frankly, I don't know. I that against the "base" it's missing:
>>
>> 0x400
>> 0x501
>>
>> so presumably the second DSP and an endpoint for the primary switch's
>> ethernet port?
> Since PCIe enumeration happens in a Depth-First Search manner, bus numbers
> 3 to 7 are alloted to the cascade switch connected to DSP1 of primary switch.
> Bus no.'s 8 and 9 are alloted to DSP2 endpoint and embedded ethernet EP
> respectively, on the primary switch.
> 
> So, in the cascade hierarchy, bus no. 4 is alloted to Cascade switch DSP's.
> There is no DSP with device no. 0 so BDF 0x400 doesn't exist and is
> omitted. For the same reason, BDF 0x200 on the primary switch is also
> not mapped.
> 
> BDF 0x501 in single switch case maps to the ethernet EP. In cascade,
> that EP is being mapped to 0x901.

OK, this is very useful to know, thank you

Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1

[Konrad Dybcio]

On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
> in cascade to the first TC9563 switch via the former's downstream port.
> 
> Two embedded Ethernet devices are present on one of the downstream
> ports of this second switch as well. All the ports present in the
> node represent the downstream ports and embedded endpoints.
> 
> The second TC9563 is powered up via the same LDO regulators as the first
> one, and these can be controlled via two GPIOs, which are already present
> as fixed regulators. This TC9563 can also be configured through I2C.
> 
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v3 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes

[Sushrut Shree Trivedi]

On 2/12/2026 5:18 PM, Konrad Dybcio wrote:
> On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
>> Add nodes for the two additional TC9563 PCIe switches present on the
>> QCOM RB3Gen2 Industrial Mezzanine platform.
>>
>> One of the TC9563 is connected directly to the PCIe0 root-port while
>> the second TC9563 switch is connected in cascade fashion to another
>> already available TC9563 switch on PCIe1 via the former's downstream
>> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
> 	^ +Mani is that PCIe terminology, or is that a Toshiba-ism?
The PCIe Spec actually uses the DSP terminology
under r6.2 sec 7.9.29: Streamlined Virtual Channel
Extended Capability (SVC)

"If the SVC Extended Capability structure is implemented in a
USP containing one or more Switch USP Functions, it must be
implemented in all associated Switch DSP Functions"

Sushrut
>
> Konrad