[PATCH v5 0/6] Add initial DTS for Samsung Galaxy Book4 Edge

[PATCH v5 0/6] Add initial DTS for Samsung Galaxy Book4 Edge

[Marcus Glocker]

This DTS adds initial support for the Samsung Galaxy Book4 Edge laptop.
Keyboard, Touch-pad, and UFS are working.  The Touch-screen needs further
investigation, and is therefore disabled for now.

Changed from v4:
* Fix previously missed commits:
- Improved commit messages.
- Added missing clock line for ufs.
- Removed invalid microamp lines for ufs.

Changed from v3:
- Improved commit messages.
- Added missing clock line for ufs.
- Removed invalid microamp lines for ufs.

Changed from v2:
- Squash Makefile patch to new DTS file patch.

Changed from v1:
- Provide the patch in the expected format.
- Added missing bindings.
- Removed sound node.
- Changed regulator syntax to be consistent.
- Changed touchscreen node comment, and removed false pin definition.
- Rename ufshc@ to ufs@.

Marcus Glocker (6):
  dt-bindings: crypto: Add X1E80100 Crypto Engine
  dt-bindings: phy: Add X1E80100 UFS
  dt-bindings: ufs: Add X1E80100 UFS
  arm64: dts: qcom: Add UFS node
  dt-bindings: arm: Add Samsung Galaxy Book4 Edge
  arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS

 .../devicetree/bindings/arm/qcom.yaml         |   1 +
 .../crypto/qcom,inline-crypto-engine.yaml     |   1 +
 .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   2 +
 .../devicetree/bindings/ufs/qcom,ufs.yaml     |   2 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../x1e80100-samsung-galaxy-book4-edge.dts    | 957 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/x1e80100.dtsi        |  72 ++
 7 files changed, 1036 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts

-- 
2.39.2

[PATCH v5 1/6] dt-bindings: crypto: Add X1E80100 Crypto Engine

[Marcus Glocker]

Add the UFS Crypto Engine binding.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 0304f074cf08..915db3d28892 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -19,6 +19,7 @@ properties:
           - qcom,sm8450-inline-crypto-engine
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
+          - qcom,x1e80100-inline-crypto-engine
       - const: qcom,inline-crypto-engine
 
   reg:
-- 
2.39.2

[PATCH v5 2/6] dt-bindings: phy: Add X1E80100 UFS

[Marcus Glocker]

Document the qmp ufs phy compatible for the Qualcomm X1E80100.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml      | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index f9cfbd0b2de6..c8a61cddb311 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -35,6 +35,7 @@ properties:
       - qcom,sm8475-qmp-ufs-phy
       - qcom,sm8550-qmp-ufs-phy
       - qcom,sm8650-qmp-ufs-phy
+      - qcom,x1e80100-qmp-ufs-phy
 
   reg:
     maxItems: 1
@@ -102,6 +103,7 @@ allOf:
               - qcom,sm8475-qmp-ufs-phy
               - qcom,sm8550-qmp-ufs-phy
               - qcom,sm8650-qmp-ufs-phy
+              - qcom,x1e80100-qmp-ufs-phy
     then:
       properties:
         clocks:
-- 
2.39.2

[PATCH v5 3/6] dt-bindings: ufs: Add X1E80100 UFS

[Marcus Glocker]

Document the ufs host controller compatible for the Qualcomm X1E80100.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
---
 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 25a5edeea164..4cb3fea53651 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -41,6 +41,7 @@ properties:
           - qcom,sm8450-ufshc
           - qcom,sm8550-ufshc
           - qcom,sm8650-ufshc
+          - qcom,x1e80100-ufshc
       - const: qcom,ufshc
       - const: jedec,ufs-2.0
 
@@ -121,6 +122,7 @@ allOf:
           contains:
             enum:
               - qcom,sc7180-ufshc
+              - qcom,x1e80100-ufshc
     then:
       properties:
         clocks:
-- 
2.39.2

[PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Marcus Glocker]

Add the UFS Host Controller node.  This was basically copied from the
arch/arm64/boot/dts/qcom/sc7180.dtsi file.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 7bca5fcd7d52..9f01b3ff3737 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
 			#interconnect-cells = <2>;
 		};
 
+		ufs_mem_hc: ufs@1d84000 {
+			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0 0x01d84000 0 0x3000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <1>;
+			#reset-cells = <1>;
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			iommus = <&apps_smmu 0xa0 0x0>;
+
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk";
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+			freq-table-hz = <50000000 200000000>,
+					<0 0>,
+					<0 0>,
+					<37500000 150000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>;
+
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ufs-ddr", "cpu-ufs";
+
+			qcom,ice = <&ice>;
+
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,x1e80100-qmp-ufs-phy";
+			reg = <0 0x01d87000 0 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		ice: crypto@1d90000 {
+			compatible = "qcom,x1e80100-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0 0x01d90000 0 0x8000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
 		pcie6a: pci@1bf8000 {
 			device_type = "pci";
 			compatible = "qcom,pcie-x1e80100";
-- 
2.39.2

[PATCH v5 5/6] dt-bindings: arm: Add Samsung Galaxy Book4 Edge

[Marcus Glocker]

Add the Samsung Galaxy Book4 Edge compatibility binding.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index f08e13b61172..c8a32e5d2c74 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1044,6 +1044,7 @@ properties:
               - lenovo,yoga-slim7x
               - qcom,x1e80100-crd
               - qcom,x1e80100-qcp
+              - samsung,galaxy-book4-edge
           - const: qcom,x1e80100
 
   # Board compatibles go above
-- 
2.39.2

[PATCH v5 6/6] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS

[Marcus Glocker]

Add the initial DTS file for the Samsung Galaxy Book4 Edge laptop.
This was a copy of the arch/arm64/boot/dts/qcom/x1e80100-crd.dts file and
adapted to our needs.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../x1e80100-samsung-galaxy-book4-edge.dts    | 957 ++++++++++++++++++
 2 files changed, 958 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 0e5c810304fb..77a48a5780ed 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -265,3 +265,4 @@ dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-asus-vivobook-s15.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-crd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-lenovo-yoga-slim7x.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-qcp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-samsung-galaxy-book4-edge.dtb
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts b/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts
new file mode 100644
index 000000000000..894854399a93
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts
@@ -0,0 +1,957 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+	model = "Samsung Galaxy Book4 Edge";
+	compatible = "samsung,galaxy-book4-edge", "qcom,x1e80100";
+	chassis-type = "laptop";
+
+	pmic-glink {
+		compatible = "qcom,x1e80100-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 123 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+		/* Left-side rear port */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss0_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss0_ss_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+					};
+				};
+			};
+		};
+
+		/* Left-side front port */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss1_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss1_ss_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+					};
+				};
+			};
+		};
+
+		/* Right-side port */
+		connector@2 {
+			compatible = "usb-c-connector";
+			reg = <2>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss2_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss2_ss_in: endpoint {
+						remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_edp_3p3: regulator-edp-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_EDP_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&edp_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob2>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l12-supply = <&vreg_s5j_1p2>;
+		vdd-l15-supply = <&vreg_s4c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p0: ldo5 {
+			regulator-name = "vreg_l5b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p8: ldo7 {
+			regulator-name = "vreg_l7b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_3p0: ldo8 {
+			regulator-name = "vreg_l8b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p2: ldo12 {
+			regulator-name = "vreg_l12b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p0: ldo14 {
+			regulator-name = "vreg_l14b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p9: ldo16 {
+			regulator-name = "vreg_l16b_2p9";
+			regulator-min-microvolt = <2912000>;
+			regulator-max-microvolt = <2912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4c_1p8: smps4 {
+			regulator-name = "vreg_s4c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_0p8: ldo2 {
+			regulator-name = "vreg_l2c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_0p8: ldo3 {
+			regulator-name = "vreg_l3c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s4c_1p8>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_l1d_0p8: ldo1 {
+			regulator-name = "vreg_l1d_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p9: ldo2 {
+			regulator-name = "vreg_l2d_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_1p8: ldo3 {
+			regulator-name = "vreg_l3d_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+
+		vreg_l2e_0p8: ldo2 {
+			regulator-name = "vreg_l2e_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_s1f_0p7: smps1 {
+			regulator-name = "vreg_s1f_0p7";
+			regulator-min-microvolt = <700000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_1p0: ldo1 {
+			regulator-name = "vreg_l1f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p0: ldo2 {
+			regulator-name = "vreg_l2f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p0: ldo3 {
+			regulator-name = "vreg_l3f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "i";
+
+		vdd-l1-supply = <&vreg_s4c_1p8>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+
+		vreg_s1i_0p9: smps1 {
+			regulator-name = "vreg_s1i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2i_1p0: smps2 {
+			regulator-name = "vreg_s2i_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p8: ldo1 {
+			regulator-name = "vreg_l1i_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p8: ldo3 {
+			regulator-name = "vreg_l3i_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "j";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s5j_1p2: smps5 {
+			regulator-name = "vreg_s5j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p8: ldo1 {
+			regulator-name = "vreg_l1j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3j_0p8: ldo3 {
+			regulator-name = "vreg_l3j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	keyboard@5 {
+		compatible = "hid-over-i2c";
+		reg = <0x5>;
+
+		hid-descr-addr = <0x20>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&kybd_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "disabled";
+
+	touchscreen@5d {
+		compatible = "hid-over-i2c";
+		reg = <0x5d>;
+
+		hid-descr-addr = <0x1>;
+		/* XXX: Pin 51 is creating an interrupt storm. */
+		interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&ts0_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c13 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchpad@40 {
+		compatible = "hid-over-i2c";
+		reg = <0x40>;
+
+		hid-descr-addr = <0xe>;
+		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&tpad_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	spkr_23_sd_n_active: spkr-23-sd-n-active-state {
+		pins = "gpio13";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l1b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp3 {
+	compatible = "qcom,x1e80100-dp";
+	/delete-property/ #sound-dai-cells;
+
+	status = "okay";
+
+	aux-bus {
+		panel {
+			compatible = "edp-panel";
+			power-supply = <&vreg_edp_3p3>;
+
+			port {
+				edp_panel_in: endpoint {
+					remote-endpoint = <&mdss_dp3_out>;
+				};
+			};
+		};
+	};
+
+	ports {
+		port@1 {
+			reg = <1>;
+			mdss_dp3_out: endpoint {
+				data-lanes = <0 1 2 3>;
+				link-frequencies =
+				    /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+				remote-endpoint = <&edp_panel_in>;
+			};
+		};
+	};
+};
+
+&mdss_dp3_phy {
+	vdda-phy-supply = <&vreg_l3j_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&qupv3_0 {
+	status = "okay";
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&qupv3_2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qcadsp8380.mbn",
+			"qcom/x1e80100/SAMSUNG/galaxy-book4-edge/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qccdsp8380.mbn",
+			"qcom/x1e80100/SAMSUNG/galaxy-book4-edge/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&smb2360_1_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l14b_3p0>;
+};
+
+&smb2360_2 {
+	status = "okay";
+};
+
+&smb2360_2_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l8b_3p0>;
+};
+
+&swr0 {
+	status = "okay";
+
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	/* WSA8845, Left Woofer */
+	left_woofer: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "WooferLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+	};
+
+	/* WSA8845, Left Tweeter */
+	left_tweeter: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TwitterLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
+&swr3 {
+	status = "okay";
+
+	pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>;
+	pinctrl-names = "default";
+
+	/* WSA8845, Right Woofer */
+	right_woofer: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "WooferRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+	};
+
+	/* WSA8845, Right Tweeter */
+	right_tweeter: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TwitterRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <34 2>, /* Unused */
+			       <44 4>, /* SPI (TPM) */
+			       <238 1>; /* UFS Reset */
+
+	edp_reg_en: edp-reg-en-state {
+		pins = "gpio70";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	kybd_default: kybd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		bias-disable;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	tpad_default: tpad-default-state {
+		pins = "gpio3";
+		function = "gpio";
+		bias-disable;
+	};
+
+	ts0_default: ts0-default-state {
+		int-n-pins {
+			pins = "gpio51";
+			function = "gpio";
+			bias-disable;
+		};
+
+		reset-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			output-high;
+			drive-strength = <16>;
+		};
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&ufs_mem_hc {
+	status = "okay";
+
+	vcc-supply = <&vreg_l9b_2p9>;
+	vcc-max-microamp = <600000>;
+	vccq2-supply = <&vreg_l4b_1p8>;
+	vccq2-max-microamp = <600000>;
+};
+
+&ufs_mem_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l2c_0p8>;
+	vdda-pll-supply = <&vreg_l12b_1p2>;
+};
+
+&uart21 {
+	compatible = "qcom,geni-debug-uart";
+	status = "okay";
+};
+
+&usb_1_ss0_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_0_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l1j_0p8>;
+
+	status = "okay";
+};
+
+&usb_1_ss0 {
+	status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_1_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss1 {
+	status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss1_ss_in>;
+};
+
+&usb_1_ss2_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_2_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss2 {
+	status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss2_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss2_hs_in>;
+};
+
+&usb_1_ss2_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss2_ss_in>;
+};
-- 
2.39.2

Re: [PATCH v5 3/6] dt-bindings: ufs: Add X1E80100 UFS

[Krzysztof Kozlowski]

On 17/08/2024 22:36, Marcus Glocker wrote:
> Document the ufs host controller compatible for the Qualcomm X1E80100.
> 
> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Konrad Dybcio]

On 17.08.2024 10:38 PM, Marcus Glocker wrote:
> Add the UFS Host Controller node.  This was basically copied from the
> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
> 
> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 7bca5fcd7d52..9f01b3ff3737 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
>  			#interconnect-cells = <2>;
>  		};
>  
> +		ufs_mem_hc: ufs@1d84000 {
> +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
> +				     "jedec,ufs-2.0";
> +			reg = <0 0x01d84000 0 0x3000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&ufs_mem_phy>;
> +			phy-names = "ufsphy";
> +			lanes-per-direction = <1>;
> +			#reset-cells = <1>;
> +			resets = <&gcc GCC_UFS_PHY_BCR>;
> +			reset-names = "rst";
> +
> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> +
> +			iommus = <&apps_smmu 0xa0 0x0>;

Looks like this should be 0x1a0 maybe
> +
> +			clock-names = "core_clk",
> +				      "bus_aggr_clk",
> +				      "iface_clk",
> +				      "core_clk_unipro",
> +				      "ref_clk",
> +				      "tx_lane0_sync_clk",
> +				      "rx_lane0_sync_clk";
> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> +				 <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;

You also want

<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>

> +			freq-table-hz = <50000000 200000000>,
25000000 300000000

> +					<0 0>,
> +					<0 0>,
> +					<37500000 150000000>,
75000000 300000000

> +					<0 0>,
> +					<0 0>,
> +					<0 0>;
> +
> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> +			interconnect-names = "ufs-ddr", "cpu-ufs";
> +
> +			qcom,ice = <&ice>;
> +
> +			status = "disabled";
> +		};
> +
> +		ufs_mem_phy: phy@1d87000 {
> +			compatible = "qcom,x1e80100-qmp-ufs-phy";
> +			reg = <0 0x01d87000 0 0x1000>;

most definitely should be 0x01d80000 with a size of 0x2000

> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> +			clock-names = "ref",
> +				      "ref_aux",
> +				      "qref";
> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		ice: crypto@1d90000 {
> +			compatible = "qcom,x1e80100-inline-crypto-engine",
> +				     "qcom,inline-crypto-engine";
> +			reg = <0 0x01d90000 0 0x8000>;

0x1d88000


All this combined means you probably wrote your init sequence into some
free(?) register space and the one left over from the bootloader was
good enough :P

Konrad

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Johan Hovold]

On Sat, Aug 17, 2024 at 10:38:39PM +0200, Marcus Glocker wrote:
> Add the UFS Host Controller node.  This was basically copied from the
> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
> 
> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Also, when respinning, please add the missing "x1e80100: " to the
Subject prefix.

Johan

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Marcus Glocker]

On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:

> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
> > Add the UFS Host Controller node.  This was basically copied from the
> > arch/arm64/boot/dts/qcom/sc7180.dtsi file.
> >
> > Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
> >  1 file changed, 72 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
> > b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index 7bca5fcd7d52..9f01b3ff3737 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
> >  			#interconnect-cells = <2>;
> >  		};
> >
> > +		ufs_mem_hc: ufs@1d84000 {
> > +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
> > +				     "jedec,ufs-2.0";
> > +			reg = <0 0x01d84000 0 0x3000>;
> > +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> > +			phys = <&ufs_mem_phy>;
> > +			phy-names = "ufsphy";
> > +			lanes-per-direction = <1>;
> > +			#reset-cells = <1>;
> > +			resets = <&gcc GCC_UFS_PHY_BCR>;
> > +			reset-names = "rst";
> > +
> > +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> > +
> > +			iommus = <&apps_smmu 0xa0 0x0>;
> 
> Looks like this should be 0x1a0 maybe
> > +
> > +			clock-names = "core_clk",
> > +				      "bus_aggr_clk",
> > +				      "iface_clk",
> > +				      "core_clk_unipro",
> > +				      "ref_clk",
> > +				      "tx_lane0_sync_clk",
> > +				      "rx_lane0_sync_clk";
> > +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> > +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> > +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> > +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> > +				 <&rpmhcc RPMH_CXO_CLK>,
> > +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> > +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
> 
> You also want
> 
> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
> 
> > +			freq-table-hz = <50000000 200000000>,
> 25000000 300000000
> 
> > +					<0 0>,
> > +					<0 0>,
> > +					<37500000 150000000>,
> 75000000 300000000
> 
> > +					<0 0>,
> > +					<0 0>,
> > +					<0 0>;
> > +
> > +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> > +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> > +			interconnect-names = "ufs-ddr", "cpu-ufs";
> > +
> > +			qcom,ice = <&ice>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		ufs_mem_phy: phy@1d87000 {
> > +			compatible = "qcom,x1e80100-qmp-ufs-phy";
> > +			reg = <0 0x01d87000 0 0x1000>;
> 
> most definitely should be 0x01d80000 with a size of 0x2000
> 
> > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> > +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> > +			clock-names = "ref",
> > +				      "ref_aux",
> > +				      "qref";
> > +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> > +			resets = <&ufs_mem_hc 0>;
> > +			reset-names = "ufsphy";
> > +			#phy-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		ice: crypto@1d90000 {
> > +			compatible = "qcom,x1e80100-inline-crypto-engine",
> > +				     "qcom,inline-crypto-engine";
> > +			reg = <0 0x01d90000 0 0x8000>;
> 
> 0x1d88000
> 
> 
> All this combined means you probably wrote your init sequence into some
> free(?) register space and the one left over from the bootloader was
> good enough :P
> 
> Konrad

I have not done anything special in our sub-system to boot this DTB.
Changing the values as suggested by you also doesn't make any difference
to me.

Anyway, I think I'll give up at this point, since this process is
getting too time consuming for me.  We'll go ahead with out downstream
patches, which works for us so far.

Cheers,
Marcus

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Daniel Gomez]

On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote:
> On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:
>
>> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
>> > Add the UFS Host Controller node.  This was basically copied from the
>> > arch/arm64/boot/dts/qcom/sc7180.dtsi file.
>> >
>> > Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
>> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> > ---
>> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
>> >  1 file changed, 72 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
>> > b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> > index 7bca5fcd7d52..9f01b3ff3737 100644
>> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> > @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
>> >  			#interconnect-cells = <2>;
>> >  		};
>> >
>> > +		ufs_mem_hc: ufs@1d84000 {
>> > +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
>> > +				     "jedec,ufs-2.0";
>> > +			reg = <0 0x01d84000 0 0x3000>;
>> > +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>> > +			phys = <&ufs_mem_phy>;
>> > +			phy-names = "ufsphy";
>> > +			lanes-per-direction = <1>;
>> > +			#reset-cells = <1>;
>> > +			resets = <&gcc GCC_UFS_PHY_BCR>;
>> > +			reset-names = "rst";
>> > +
>> > +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>> > +
>> > +			iommus = <&apps_smmu 0xa0 0x0>;
>> 
>> Looks like this should be 0x1a0 maybe
>> > +
>> > +			clock-names = "core_clk",
>> > +				      "bus_aggr_clk",
>> > +				      "iface_clk",
>> > +				      "core_clk_unipro",
>> > +				      "ref_clk",
>> > +				      "tx_lane0_sync_clk",
>> > +				      "rx_lane0_sync_clk";
>> > +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>> > +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>> > +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>> > +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>> > +				 <&rpmhcc RPMH_CXO_CLK>,
>> > +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>> > +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
>> 
>> You also want
>> 
>> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
>> 
>> > +			freq-table-hz = <50000000 200000000>,
>> 25000000 300000000
>> 
>> > +					<0 0>,
>> > +					<0 0>,
>> > +					<37500000 150000000>,
>> 75000000 300000000
>> 
>> > +					<0 0>,
>> > +					<0 0>,
>> > +					<0 0>;
>> > +
>> > +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>> > +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> > +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> > +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>> > +			interconnect-names = "ufs-ddr", "cpu-ufs";
>> > +
>> > +			qcom,ice = <&ice>;
>> > +
>> > +			status = "disabled";
>> > +		};
>> > +
>> > +		ufs_mem_phy: phy@1d87000 {
>> > +			compatible = "qcom,x1e80100-qmp-ufs-phy";
>> > +			reg = <0 0x01d87000 0 0x1000>;
>> 
>> most definitely should be 0x01d80000 with a size of 0x2000
>> 
>> > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>> > +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> > +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>> > +			clock-names = "ref",
>> > +				      "ref_aux",
>> > +				      "qref";
>> > +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>> > +			resets = <&ufs_mem_hc 0>;
>> > +			reset-names = "ufsphy";
>> > +			#phy-cells = <0>;
>> > +			status = "disabled";
>> > +		};
>> > +
>> > +		ice: crypto@1d90000 {
>> > +			compatible = "qcom,x1e80100-inline-crypto-engine",
>> > +				     "qcom,inline-crypto-engine";
>> > +			reg = <0 0x01d90000 0 0x8000>;
>> 
>> 0x1d88000
>> 
>> 
>> All this combined means you probably wrote your init sequence into some
>> free(?) register space and the one left over from the bootloader was
>> good enough :P
>> 
>> Konrad
>
> I have not done anything special in our sub-system to boot this DTB.
> Changing the values as suggested by you also doesn't make any difference
> to me.
>
> Anyway, I think I'll give up at this point, since this process is
> getting too time consuming for me.  We'll go ahead with out downstream
> patches, which works for us so far.

Hi Marcus,

I came across this and I'd be interested in picking up the patches for testing.
Is there any guide or documentation available that I could follow to boot Linux
on this machine using this patchset? Also, could you share where I might be able
to find those downstream patches?

Thanks,
Daniel

>
> Cheers,
> Marcus

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Wesley Cheng]

On 11/9/2024 3:31 PM, Daniel Gomez wrote:
> On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote:
>> On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:
>>
>>> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
>>>> Add the UFS Host Controller node.  This was basically copied from the
>>>> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
>>>>
>>>> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
>>>>  1 file changed, 72 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
>>>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>> index 7bca5fcd7d52..9f01b3ff3737 100644
>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>> @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
>>>>  			#interconnect-cells = <2>;
>>>>  		};
>>>>
>>>> +		ufs_mem_hc: ufs@1d84000 {
>>>> +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
>>>> +				     "jedec,ufs-2.0";
>>>> +			reg = <0 0x01d84000 0 0x3000>;
>>>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>>>> +			phys = <&ufs_mem_phy>;
>>>> +			phy-names = "ufsphy";
>>>> +			lanes-per-direction = <1>;
>>>> +			#reset-cells = <1>;
>>>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
>>>> +			reset-names = "rst";
>>>> +
>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>>> +
>>>> +			iommus = <&apps_smmu 0xa0 0x0>;
>>> Looks like this should be 0x1a0 maybe
>>>> +
>>>> +			clock-names = "core_clk",
>>>> +				      "bus_aggr_clk",
>>>> +				      "iface_clk",
>>>> +				      "core_clk_unipro",
>>>> +				      "ref_clk",
>>>> +				      "tx_lane0_sync_clk",
>>>> +				      "rx_lane0_sync_clk";
>>>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>>>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>>> +				 <&rpmhcc RPMH_CXO_CLK>,
>>>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
>>> You also want
>>>
>>> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
>>>
>>>> +			freq-table-hz = <50000000 200000000>,
>>> 25000000 300000000
>>>
>>>> +					<0 0>,
>>>> +					<0 0>,
>>>> +					<37500000 150000000>,
>>> 75000000 300000000
>>>
>>>> +					<0 0>,
>>>> +					<0 0>,
>>>> +					<0 0>;
>>>> +
>>>> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>> +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>>>> +			interconnect-names = "ufs-ddr", "cpu-ufs";
>>>> +
>>>> +			qcom,ice = <&ice>;
>>>> +
>>>> +			status = "disabled";
>>>> +		};
>>>> +
>>>> +		ufs_mem_phy: phy@1d87000 {
>>>> +			compatible = "qcom,x1e80100-qmp-ufs-phy";
>>>> +			reg = <0 0x01d87000 0 0x1000>;
>>> most definitely should be 0x01d80000 with a size of 0x2000
>>>
>>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>>>> +			clock-names = "ref",
>>>> +				      "ref_aux",
>>>> +				      "qref";
>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>>> +			resets = <&ufs_mem_hc 0>;
>>>> +			reset-names = "ufsphy";
>>>> +			#phy-cells = <0>;
>>>> +			status = "disabled";
>>>> +		};
>>>> +
>>>> +		ice: crypto@1d90000 {
>>>> +			compatible = "qcom,x1e80100-inline-crypto-engine",
>>>> +				     "qcom,inline-crypto-engine";
>>>> +			reg = <0 0x01d90000 0 0x8000>;
>>> 0x1d88000
>>>
>>>
>>> All this combined means you probably wrote your init sequence into some
>>> free(?) register space and the one left over from the bootloader was
>>> good enough :P
>>>
>>> Konrad
>> I have not done anything special in our sub-system to boot this DTB.
>> Changing the values as suggested by you also doesn't make any difference
>> to me.
>>
>> Anyway, I think I'll give up at this point, since this process is
>> getting too time consuming for me.  We'll go ahead with out downstream
>> patches, which works for us so far.


Hi Marcus,


Do you mind if I take over this series?  I started working on getting at least the UFS and USB portions of the DT file to work on my Samsung Galaxy book4 with your patches, along with some required modifications.  If you're OK, I'll keep you as the author for the main DT file, and submit my changes on top.


Thanks

Wesley Cheng

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Marcus Glocker]

On Thu, Jan 02, 2025 at 01:38:10PM GMT, Wesley Cheng wrote:

> 
> On 11/9/2024 3:31 PM, Daniel Gomez wrote:
> > On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote:
> >> On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:
> >>
> >>> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
> >>>> Add the UFS Host Controller node.  This was basically copied from the
> >>>> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
> >>>>
> >>>> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> >>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >>>> ---
> >>>>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
> >>>>  1 file changed, 72 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
> >>>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>> index 7bca5fcd7d52..9f01b3ff3737 100644
> >>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>> @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
> >>>>  			#interconnect-cells = <2>;
> >>>>  		};
> >>>>
> >>>> +		ufs_mem_hc: ufs@1d84000 {
> >>>> +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
> >>>> +				     "jedec,ufs-2.0";
> >>>> +			reg = <0 0x01d84000 0 0x3000>;
> >>>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> >>>> +			phys = <&ufs_mem_phy>;
> >>>> +			phy-names = "ufsphy";
> >>>> +			lanes-per-direction = <1>;
> >>>> +			#reset-cells = <1>;
> >>>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
> >>>> +			reset-names = "rst";
> >>>> +
> >>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> >>>> +
> >>>> +			iommus = <&apps_smmu 0xa0 0x0>;
> >>> Looks like this should be 0x1a0 maybe
> >>>> +
> >>>> +			clock-names = "core_clk",
> >>>> +				      "bus_aggr_clk",
> >>>> +				      "iface_clk",
> >>>> +				      "core_clk_unipro",
> >>>> +				      "ref_clk",
> >>>> +				      "tx_lane0_sync_clk",
> >>>> +				      "rx_lane0_sync_clk";
> >>>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> >>>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> >>>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> >>>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> >>>> +				 <&rpmhcc RPMH_CXO_CLK>,
> >>>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> >>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
> >>> You also want
> >>>
> >>> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
> >>>
> >>>> +			freq-table-hz = <50000000 200000000>,
> >>> 25000000 300000000
> >>>
> >>>> +					<0 0>,
> >>>> +					<0 0>,
> >>>> +					<37500000 150000000>,
> >>> 75000000 300000000
> >>>
> >>>> +					<0 0>,
> >>>> +					<0 0>,
> >>>> +					<0 0>;
> >>>> +
> >>>> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> >>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> >>>> +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> >>>> +			interconnect-names = "ufs-ddr", "cpu-ufs";
> >>>> +
> >>>> +			qcom,ice = <&ice>;
> >>>> +
> >>>> +			status = "disabled";
> >>>> +		};
> >>>> +
> >>>> +		ufs_mem_phy: phy@1d87000 {
> >>>> +			compatible = "qcom,x1e80100-qmp-ufs-phy";
> >>>> +			reg = <0 0x01d87000 0 0x1000>;
> >>> most definitely should be 0x01d80000 with a size of 0x2000
> >>>
> >>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> >>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> >>>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> >>>> +			clock-names = "ref",
> >>>> +				      "ref_aux",
> >>>> +				      "qref";
> >>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> >>>> +			resets = <&ufs_mem_hc 0>;
> >>>> +			reset-names = "ufsphy";
> >>>> +			#phy-cells = <0>;
> >>>> +			status = "disabled";
> >>>> +		};
> >>>> +
> >>>> +		ice: crypto@1d90000 {
> >>>> +			compatible = "qcom,x1e80100-inline-crypto-engine",
> >>>> +				     "qcom,inline-crypto-engine";
> >>>> +			reg = <0 0x01d90000 0 0x8000>;
> >>> 0x1d88000
> >>>
> >>>
> >>> All this combined means you probably wrote your init sequence into some
> >>> free(?) register space and the one left over from the bootloader was
> >>> good enough :P
> >>>
> >>> Konrad
> >> I have not done anything special in our sub-system to boot this DTB.
> >> Changing the values as suggested by you also doesn't make any difference
> >> to me.
> >>
> >> Anyway, I think I'll give up at this point, since this process is
> >> getting too time consuming for me.  We'll go ahead with out downstream
> >> patches, which works for us so far.
> 
> 
> Hi Marcus,
> 
> 
> Do you mind if I take over this series??? I started working on getting at least the UFS and USB portions of the DT file to work on my Samsung Galaxy book4 with your patches, along with some required modifications.?? If you're OK, I'll keep you as the author for the main DT file, and submit my changes on top.
> 
> 
> Thanks
> 
> Wesley Cheng

Hi Wesley,

Perfectly fine for me.  I'm glad if there is progress.

Thanks and Regards,
Marcus

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Maxim Storetvedt]

On 1/3/25 00:17, Marcus Glocker wrote:
> On Thu, Jan 02, 2025 at 01:38:10PM GMT, Wesley Cheng wrote:
> 
>>
>> On 11/9/2024 3:31 PM, Daniel Gomez wrote:
>>> On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote:
>>>> On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:
>>>>
>>>>> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
>>>>>> Add the UFS Host Controller node.  This was basically copied from the
>>>>>> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
>>>>>>
>>>>>> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
>>>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>>> ---
>>>>>>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
>>>>>>  1 file changed, 72 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
>>>>>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>> index 7bca5fcd7d52..9f01b3ff3737 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>> @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
>>>>>>  			#interconnect-cells = <2>;
>>>>>>  		};
>>>>>>
>>>>>> +		ufs_mem_hc: ufs@1d84000 {
>>>>>> +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
>>>>>> +				     "jedec,ufs-2.0";
>>>>>> +			reg = <0 0x01d84000 0 0x3000>;
>>>>>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +			phys = <&ufs_mem_phy>;
>>>>>> +			phy-names = "ufsphy";
>>>>>> +			lanes-per-direction = <1>;
>>>>>> +			#reset-cells = <1>;
>>>>>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
>>>>>> +			reset-names = "rst";
>>>>>> +
>>>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>>>>> +
>>>>>> +			iommus = <&apps_smmu 0xa0 0x0>;
>>>>> Looks like this should be 0x1a0 maybe
>>>>>> +
>>>>>> +			clock-names = "core_clk",
>>>>>> +				      "bus_aggr_clk",
>>>>>> +				      "iface_clk",
>>>>>> +				      "core_clk_unipro",
>>>>>> +				      "ref_clk",
>>>>>> +				      "tx_lane0_sync_clk",
>>>>>> +				      "rx_lane0_sync_clk";
>>>>>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>>>>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>>>>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>>>>>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>>>>> +				 <&rpmhcc RPMH_CXO_CLK>,
>>>>>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>>>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
>>>>> You also want
>>>>>
>>>>> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
>>>>>
>>>>>> +			freq-table-hz = <50000000 200000000>,
>>>>> 25000000 300000000
>>>>>
>>>>>> +					<0 0>,
>>>>>> +					<0 0>,
>>>>>> +					<37500000 150000000>,
>>>>> 75000000 300000000
>>>>>
>>>>>> +					<0 0>,
>>>>>> +					<0 0>,
>>>>>> +					<0 0>;
>>>>>> +
>>>>>> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>>>> +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>>>>>> +			interconnect-names = "ufs-ddr", "cpu-ufs";
>>>>>> +
>>>>>> +			qcom,ice = <&ice>;
>>>>>> +
>>>>>> +			status = "disabled";
>>>>>> +		};
>>>>>> +
>>>>>> +		ufs_mem_phy: phy@1d87000 {
>>>>>> +			compatible = "qcom,x1e80100-qmp-ufs-phy";
>>>>>> +			reg = <0 0x01d87000 0 0x1000>;
>>>>> most definitely should be 0x01d80000 with a size of 0x2000
>>>>>
>>>>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>>>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>>>>>> +			clock-names = "ref",
>>>>>> +				      "ref_aux",
>>>>>> +				      "qref";
>>>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>>>>> +			resets = <&ufs_mem_hc 0>;
>>>>>> +			reset-names = "ufsphy";
>>>>>> +			#phy-cells = <0>;
>>>>>> +			status = "disabled";
>>>>>> +		};
>>>>>> +
>>>>>> +		ice: crypto@1d90000 {
>>>>>> +			compatible = "qcom,x1e80100-inline-crypto-engine",
>>>>>> +				     "qcom,inline-crypto-engine";
>>>>>> +			reg = <0 0x01d90000 0 0x8000>;
>>>>> 0x1d88000
>>>>>
>>>>>
>>>>> All this combined means you probably wrote your init sequence into some
>>>>> free(?) register space and the one left over from the bootloader was
>>>>> good enough :P
>>>>>
>>>>> Konrad
>>>> I have not done anything special in our sub-system to boot this DTB.
>>>> Changing the values as suggested by you also doesn't make any difference
>>>> to me.
>>>>
>>>> Anyway, I think I'll give up at this point, since this process is
>>>> getting too time consuming for me.  We'll go ahead with out downstream
>>>> patches, which works for us so far.
>>
>>
>> Hi Marcus,
>>
>>
>> Do you mind if I take over this series??? I started working on getting at least the UFS and USB portions of the DT file to work on my Samsung Galaxy book4 with your patches, along with some required modifications.?? If you're OK, I'll keep you as the author for the main DT file, and submit my changes on top.
>>
>>
>> Thanks
>>
>> Wesley Cheng
> 
> Hi Wesley,
> 
> Perfectly fine for me.  I'm glad if there is progress.
> 
> Thanks and Regards,
> Marcus
> 

Hi Marcus, Wesley,

We've continued to iterate on this device over at its thread on
Launchpad, and been able to get a fairly usable system up and running on
Linux for both the 14" and 16" SKUs. I'd be happy to update the series
with the changes.

Cheers,
-Max

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Marcus Glocker]

On Sat, Mar 07, 2026 at 05:01:14PM +0100, Maxim Storetvedt wrote:

> 
> On 1/3/25 00:17, Marcus Glocker wrote:
> > On Thu, Jan 02, 2025 at 01:38:10PM GMT, Wesley Cheng wrote:
> > 
> >>
> >> On 11/9/2024 3:31 PM, Daniel Gomez wrote:
> >>> On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote:
> >>>> On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:
> >>>>
> >>>>> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
> >>>>>> Add the UFS Host Controller node.  This was basically copied from the
> >>>>>> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
> >>>>>>
> >>>>>> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> >>>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >>>>>> ---
> >>>>>>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
> >>>>>>  1 file changed, 72 insertions(+)
> >>>>>>
> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
> >>>>>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>>>> index 7bca5fcd7d52..9f01b3ff3737 100644
> >>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>>>> @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
> >>>>>>  			#interconnect-cells = <2>;
> >>>>>>  		};
> >>>>>>
> >>>>>> +		ufs_mem_hc: ufs@1d84000 {
> >>>>>> +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
> >>>>>> +				     "jedec,ufs-2.0";
> >>>>>> +			reg = <0 0x01d84000 0 0x3000>;
> >>>>>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> >>>>>> +			phys = <&ufs_mem_phy>;
> >>>>>> +			phy-names = "ufsphy";
> >>>>>> +			lanes-per-direction = <1>;
> >>>>>> +			#reset-cells = <1>;
> >>>>>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
> >>>>>> +			reset-names = "rst";
> >>>>>> +
> >>>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> >>>>>> +
> >>>>>> +			iommus = <&apps_smmu 0xa0 0x0>;
> >>>>> Looks like this should be 0x1a0 maybe
> >>>>>> +
> >>>>>> +			clock-names = "core_clk",
> >>>>>> +				      "bus_aggr_clk",
> >>>>>> +				      "iface_clk",
> >>>>>> +				      "core_clk_unipro",
> >>>>>> +				      "ref_clk",
> >>>>>> +				      "tx_lane0_sync_clk",
> >>>>>> +				      "rx_lane0_sync_clk";
> >>>>>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> >>>>>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> >>>>>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> >>>>>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> >>>>>> +				 <&rpmhcc RPMH_CXO_CLK>,
> >>>>>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> >>>>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
> >>>>> You also want
> >>>>>
> >>>>> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
> >>>>>
> >>>>>> +			freq-table-hz = <50000000 200000000>,
> >>>>> 25000000 300000000
> >>>>>
> >>>>>> +					<0 0>,
> >>>>>> +					<0 0>,
> >>>>>> +					<37500000 150000000>,
> >>>>> 75000000 300000000
> >>>>>
> >>>>>> +					<0 0>,
> >>>>>> +					<0 0>,
> >>>>>> +					<0 0>;
> >>>>>> +
> >>>>>> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> >>>>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >>>>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> >>>>>> +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> >>>>>> +			interconnect-names = "ufs-ddr", "cpu-ufs";
> >>>>>> +
> >>>>>> +			qcom,ice = <&ice>;
> >>>>>> +
> >>>>>> +			status = "disabled";
> >>>>>> +		};
> >>>>>> +
> >>>>>> +		ufs_mem_phy: phy@1d87000 {
> >>>>>> +			compatible = "qcom,x1e80100-qmp-ufs-phy";
> >>>>>> +			reg = <0 0x01d87000 0 0x1000>;
> >>>>> most definitely should be 0x01d80000 with a size of 0x2000
> >>>>>
> >>>>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> >>>>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> >>>>>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> >>>>>> +			clock-names = "ref",
> >>>>>> +				      "ref_aux",
> >>>>>> +				      "qref";
> >>>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> >>>>>> +			resets = <&ufs_mem_hc 0>;
> >>>>>> +			reset-names = "ufsphy";
> >>>>>> +			#phy-cells = <0>;
> >>>>>> +			status = "disabled";
> >>>>>> +		};
> >>>>>> +
> >>>>>> +		ice: crypto@1d90000 {
> >>>>>> +			compatible = "qcom,x1e80100-inline-crypto-engine",
> >>>>>> +				     "qcom,inline-crypto-engine";
> >>>>>> +			reg = <0 0x01d90000 0 0x8000>;
> >>>>> 0x1d88000
> >>>>>
> >>>>>
> >>>>> All this combined means you probably wrote your init sequence into some
> >>>>> free(?) register space and the one left over from the bootloader was
> >>>>> good enough :P
> >>>>>
> >>>>> Konrad
> >>>> I have not done anything special in our sub-system to boot this DTB.
> >>>> Changing the values as suggested by you also doesn't make any difference
> >>>> to me.
> >>>>
> >>>> Anyway, I think I'll give up at this point, since this process is
> >>>> getting too time consuming for me.  We'll go ahead with out downstream
> >>>> patches, which works for us so far.
> >>
> >>
> >> Hi Marcus,
> >>
> >>
> >> Do you mind if I take over this series??? I started working on getting at least the UFS and USB portions of the DT file to work on my Samsung Galaxy book4 with your patches, along with some required modifications.?? If you're OK, I'll keep you as the author for the main DT file, and submit my changes on top.
> >>
> >>
> >> Thanks
> >>
> >> Wesley Cheng
> > 
> > Hi Wesley,
> > 
> > Perfectly fine for me.  I'm glad if there is progress.
> > 
> > Thanks and Regards,
> > Marcus
> > 
> 
> Hi Marcus, Wesley,
> 
> We've continued to iterate on this device over at its thread on
> Launchpad, and been able to get a fairly usable system up and running on
> Linux for both the 14" and 16" SKUs. I'd be happy to update the series
> with the changes.
> 
> Cheers,
> -Max

Hi Max,

Good to read!  Sure, I would welcome to see your changes.  If you also
could send me your full DTS to my e-mail address, I could also test it
with OpenBSD.

Thanks,
Marcus

Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node

[Konrad Dybcio]

On 3/8/26 9:35 PM, Marcus Glocker wrote:
> On Sat, Mar 07, 2026 at 05:01:14PM +0100, Maxim Storetvedt wrote:
> 
>>
>> On 1/3/25 00:17, Marcus Glocker wrote:
>>> On Thu, Jan 02, 2025 at 01:38:10PM GMT, Wesley Cheng wrote:
>>>
>>>>
>>>> On 11/9/2024 3:31 PM, Daniel Gomez wrote:
>>>>> On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote:
>>>>>> On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote:
>>>>>>
>>>>>>> On 17.08.2024 10:38 PM, Marcus Glocker wrote:
>>>>>>>> Add the UFS Host Controller node.  This was basically copied from the
>>>>>>>> arch/arm64/boot/dts/qcom/sc7180.dtsi file.
>>>>>>>>
>>>>>>>> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
>>>>>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>>>>> ---
>>>>>>>>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 ++++++++++++++++++++++++++
>>>>>>>>  1 file changed, 72 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
>>>>>>>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>>>> index 7bca5fcd7d52..9f01b3ff3737 100644
>>>>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>>>> @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 {
>>>>>>>>  			#interconnect-cells = <2>;
>>>>>>>>  		};
>>>>>>>>
>>>>>>>> +		ufs_mem_hc: ufs@1d84000 {
>>>>>>>> +			compatible = "qcom,x1e80100-ufshc", "qcom,ufshc",
>>>>>>>> +				     "jedec,ufs-2.0";
>>>>>>>> +			reg = <0 0x01d84000 0 0x3000>;
>>>>>>>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>>> +			phys = <&ufs_mem_phy>;
>>>>>>>> +			phy-names = "ufsphy";
>>>>>>>> +			lanes-per-direction = <1>;
>>>>>>>> +			#reset-cells = <1>;
>>>>>>>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
>>>>>>>> +			reset-names = "rst";
>>>>>>>> +
>>>>>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>>>>>>> +
>>>>>>>> +			iommus = <&apps_smmu 0xa0 0x0>;
>>>>>>> Looks like this should be 0x1a0 maybe
>>>>>>>> +
>>>>>>>> +			clock-names = "core_clk",
>>>>>>>> +				      "bus_aggr_clk",
>>>>>>>> +				      "iface_clk",
>>>>>>>> +				      "core_clk_unipro",
>>>>>>>> +				      "ref_clk",
>>>>>>>> +				      "tx_lane0_sync_clk",
>>>>>>>> +				      "rx_lane0_sync_clk";
>>>>>>>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>>>>>>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>>>>>>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>>>>>>>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>>>>>>> +				 <&rpmhcc RPMH_CXO_CLK>,
>>>>>>>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>>>>>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
>>>>>>> You also want
>>>>>>>
>>>>>>> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>
>>>>>>>
>>>>>>>> +			freq-table-hz = <50000000 200000000>,
>>>>>>> 25000000 300000000
>>>>>>>
>>>>>>>> +					<0 0>,
>>>>>>>> +					<0 0>,
>>>>>>>> +					<37500000 150000000>,
>>>>>>> 75000000 300000000
>>>>>>>
>>>>>>>> +					<0 0>,
>>>>>>>> +					<0 0>,
>>>>>>>> +					<0 0>;
>>>>>>>> +
>>>>>>>> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>>>>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>>>>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>>>>>> +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>>>>>>>> +			interconnect-names = "ufs-ddr", "cpu-ufs";
>>>>>>>> +
>>>>>>>> +			qcom,ice = <&ice>;
>>>>>>>> +
>>>>>>>> +			status = "disabled";
>>>>>>>> +		};
>>>>>>>> +
>>>>>>>> +		ufs_mem_phy: phy@1d87000 {
>>>>>>>> +			compatible = "qcom,x1e80100-qmp-ufs-phy";
>>>>>>>> +			reg = <0 0x01d87000 0 0x1000>;
>>>>>>> most definitely should be 0x01d80000 with a size of 0x2000
>>>>>>>
>>>>>>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>>>>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>>>>>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>>>>>>>> +			clock-names = "ref",
>>>>>>>> +				      "ref_aux",
>>>>>>>> +				      "qref";
>>>>>>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>>>>>>> +			resets = <&ufs_mem_hc 0>;
>>>>>>>> +			reset-names = "ufsphy";
>>>>>>>> +			#phy-cells = <0>;
>>>>>>>> +			status = "disabled";
>>>>>>>> +		};
>>>>>>>> +
>>>>>>>> +		ice: crypto@1d90000 {
>>>>>>>> +			compatible = "qcom,x1e80100-inline-crypto-engine",
>>>>>>>> +				     "qcom,inline-crypto-engine";
>>>>>>>> +			reg = <0 0x01d90000 0 0x8000>;
>>>>>>> 0x1d88000
>>>>>>>
>>>>>>>
>>>>>>> All this combined means you probably wrote your init sequence into some
>>>>>>> free(?) register space and the one left over from the bootloader was
>>>>>>> good enough :P
>>>>>>>
>>>>>>> Konrad
>>>>>> I have not done anything special in our sub-system to boot this DTB.
>>>>>> Changing the values as suggested by you also doesn't make any difference
>>>>>> to me.
>>>>>>
>>>>>> Anyway, I think I'll give up at this point, since this process is
>>>>>> getting too time consuming for me.  We'll go ahead with out downstream
>>>>>> patches, which works for us so far.
>>>>
>>>>
>>>> Hi Marcus,
>>>>
>>>>
>>>> Do you mind if I take over this series??? I started working on getting at least the UFS and USB portions of the DT file to work on my Samsung Galaxy book4 with your patches, along with some required modifications.?? If you're OK, I'll keep you as the author for the main DT file, and submit my changes on top.
>>>>
>>>>
>>>> Thanks
>>>>
>>>> Wesley Cheng
>>>
>>> Hi Wesley,
>>>
>>> Perfectly fine for me.  I'm glad if there is progress.
>>>
>>> Thanks and Regards,
>>> Marcus
>>>
>>
>> Hi Marcus, Wesley,
>>
>> We've continued to iterate on this device over at its thread on
>> Launchpad, and been able to get a fairly usable system up and running on
>> Linux for both the 14" and 16" SKUs. I'd be happy to update the series
>> with the changes.
>>
>> Cheers,
>> -Max
> 
> Hi Max,
> 
> Good to read!  Sure, I would welcome to see your changes.  If you also
> could send me your full DTS to my e-mail address, I could also test it
> with OpenBSD.

JFYI

https://lore.kernel.org/linux-arm-msm/20260211132926.3716716-4-pradeep.pragallapati@oss.qualcomm.com/

Konrad

[PATCH v6 0/3] Add initial DTS for Samsung Galaxy Book4 Edge

[Maxim Storetvedt]

This patch introduces devicetrees to support the Samsung Galaxy Book4 Edge laptop,
and includes the X1E80100 14-inch SKU and X1E84100 16-inch SKU.

It continues the earlier patch series for this device, originally submitted
by Marcus Glocker (v5):

Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms

Supported features:
- Keyboard
- Touchpad
- USB type-c
- Display
- HDMI
- WiFi
- Bluetooth
- ADSP / CDSP
- GPU
- UFS*

UFS requires changes that are now in the process of being upstreamed
as part of another patch, specifically:

Link: https://lore.kernel.org/all/20260211132926.3716716-1-pradeep.pragallapati@oss.qualcomm.com/

Changed from v5:
- Reworked DTS/DTSI for both 14- & 16-inch SKUs
- Added Galaxy Book4 Edge to QSEECOM
- Removed UFS node from the patch

Changed from v4:
* Fix previously missed commits:
- Improved commit messages.
- Added missing clock line for ufs.
- Removed invalid microamp lines for ufs.

Changed from v3:
- Improved commit messages.
- Added missing clock line for ufs.
- Removed invalid microamp lines for ufs.

Changed from v2:
- Squash Makefile patch to new DTS file patch.

Changed from v1:
- Provide the patch in the expected format.
- Added missing bindings.
- Removed sound node.
- Changed regulator syntax to be consistent.
- Changed touchscreen node comment, and removed false pin definition.
- Rename ufshc@ to ufs@.

Marcus Glocker (1):
  dt-bindings: arm: Add Samsung Galaxy Book4 Edge

Maxim Storetvedt (2):
  firmware: qcom: scm: Allow QSEECOM on Samsung Galaxy Book4 Edge
  arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

 .../devicetree/bindings/arm/qcom.yaml         |    1 +
 arch/arm64/boot/dts/qcom/Makefile             |    2 +
 .../qcom/x1-samsung-galaxy-book4-edge.dtsi    | 1518 +++++++++++++++++
 .../x1e80100-samsung-galaxy-book4-edge-14.dts |   39 +
 .../x1e84100-samsung-galaxy-book4-edge-16.dts |   29 +
 drivers/firmware/qcom/qcom_scm.c              |    1 +
 6 files changed, 1590 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/x1-samsung-galaxy-book4-edge.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge-14.dts
 create mode 100644 arch/arm64/boot/dts/qcom/x1e84100-samsung-galaxy-book4-edge-16.dts

-- 
2.43.0

[PATCH v6 1/3] firmware: qcom: scm: Allow QSEECOM on Samsung Galaxy Book4 Edge

[Maxim Storetvedt]

Signed-off-by: Maxim Storetvedt <mstoretv@cern.ch>
---
 drivers/firmware/qcom/qcom_scm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 5c4375a7f..5d3de476c 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -2318,6 +2318,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
 	{ .compatible = "qcom,x1e80100-crd" },
 	{ .compatible = "qcom,x1e80100-qcp" },
 	{ .compatible = "qcom,x1p42100-crd" },
+	{ .compatible = "samsung,galaxy-book4-edge"},
 	{ }
 };
 
-- 
2.43.0

[PATCH v6 2/3] dt-bindings: arm: Add Samsung Galaxy Book4 Edge

[Maxim Storetvedt]

From: Marcus Glocker <marcus@nazgul.ch>

Add the Samsung Galaxy Book4 Edge compatibility binding.

Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index d054a8f56..b82ddf167 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1129,6 +1129,7 @@ properties:
               - microsoft,romulus15
               - qcom,x1e80100-crd
               - qcom,x1e80100-qcp
+              - samsung,galaxy-book4-edge
           - const: qcom,x1e80100
 
       - items:
-- 
2.43.0

[PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Maxim Storetvedt]

Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.

These use a common dtsi derived from nodes that were able to work on Linux
from the initial Galaxy Book4 Edge DTS by Marcus:

Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/

combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
Valentin Manea, which shares device similarities:

Link: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/
Link: https://github.com/vamanea/linux-magicbook (downstream)

as well as a few more adjustments on top of that again to get additional features working.
Special thanks to Jesse Ahn for helping expand on what would eventually become this dtsi.

Based-on-a-patch-by: Marcus Glocker <marcus@nazgul.ch>
Based-on-a-patch-by: Kirill A. Korinsky <kirill@korins.ky>
Signed-off-by: Maxim Storetvedt <mstoretv@cern.ch>
---
 arch/arm64/boot/dts/qcom/Makefile             |    2 +
 .../qcom/x1-samsung-galaxy-book4-edge.dtsi    | 1518 +++++++++++++++++
 .../x1e80100-samsung-galaxy-book4-edge-14.dts |   39 +
 .../x1e84100-samsung-galaxy-book4-edge-16.dts |   29 +
 4 files changed, 1588 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/x1-samsung-galaxy-book4-edge.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge-14.dts
 create mode 100644 arch/arm64/boot/dts/qcom/x1e84100-samsung-galaxy-book4-edge-16.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 02921a495..3546a3be9 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -398,6 +398,8 @@ x1e80100-microsoft-romulus15-el2-dtbs	:= x1e80100-microsoft-romulus15.dtb x1-el2
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb
 x1e80100-qcp-el2-dtbs	:= x1e80100-qcp.dtb x1-el2.dtbo
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-qcp.dtb x1e80100-qcp-el2.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-samsung-galaxy-book4-edge-14.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= x1e84100-samsung-galaxy-book4-edge-16.dtb
 x1p42100-asus-vivobook-s15-el2-dtbs	:= x1p42100-asus-vivobook-s15.dtb x1-el2.dtbo
 dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-asus-vivobook-s15.dtb x1p42100-asus-vivobook-s15-el2.dtb
 x1p42100-asus-zenbook-a14-el2-dtbs	:= x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo
diff --git a/arch/arm64/boot/dts/qcom/x1-samsung-galaxy-book4-edge.dtsi b/arch/arm64/boot/dts/qcom/x1-samsung-galaxy-book4-edge.dtsi
new file mode 100644
index 000000000..2f9e76a82
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/x1-samsung-galaxy-book4-edge.dtsi
@@ -0,0 +1,1518 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025 Kirill A. Korinsky <kirill@korins.ky>
+ * Copyright (c) 2025 Valentin Manea <valentin.manea@mrs.ro>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "hamoa.dtsi"
+#include "hamoa-pmics.dtsi"
+
+/ {
+	model = "Samsung Galaxy Book4 Edge";
+	compatible = "samsung,galaxy-book4-edge", "qcom,x1e80100";
+	chassis-type = "laptop";
+
+	aliases {
+		serial0 = &uart21;
+		serial1 = &uart14;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+		pinctrl-0 = <&hdmi_hpd_default>;
+		pinctrl-names = "default";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+			};
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,x1e80100-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 123 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+		/* Left-side rear port */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss0_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss0_ss_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss0_sbu_mux>;
+					};
+				};
+			};
+		};
+
+		/* Left-side front port */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss1_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss1_ss_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss1_sbu_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-CRD";
+		audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
+				"TweeterLeft IN", "WSA WSA_SPK2 OUT",
+				"WooferRight IN", "WSA2 WSA_SPK2 OUT",
+				"TweeterRight IN", "WSA2 WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS3",
+				"VA DMIC1", "MIC BIAS3",
+				"VA DMIC2", "MIC BIAS1",
+				"VA DMIC3", "MIC BIAS1",
+				"VA DMIC0", "VA MIC BIAS3",
+				"VA DMIC1", "VA MIC BIAS3",
+				"VA DMIC2", "VA MIC BIAS1",
+				"VA DMIC3", "VA MIC BIAS1",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_woofer>, <&left_tweeter>,
+					    <&swr0 0>, <&lpass_wsamacro 0>,
+					    <&right_woofer>, <&right_tweeter>,
+					    <&swr3 0>, <&lpass_wsa2macro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	vreg_octa_vdd: regulator-octa-vdd {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_OCTA_VDD";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 111 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&octa_vdd_en>;
+		pinctrl-names = "default";
+
+		startup-delay-us = <1000>;
+		regulator-enable-ramp-delay = <1000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_display_vdd: regulator-display-vdd {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_DISPLAY_VDD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 120 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&display_vdd_en>;
+		pinctrl-names = "default";
+
+		startup-delay-us = <400000>;
+		regulator-enable-ramp-delay = <400000>;
+
+		vin-supply = <&vreg_octa_vdd>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_edp_3p3: regulator-edp-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_EDP_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
+		enable-active-low;
+
+		pinctrl-0 = <&edp_reg_en>;
+		pinctrl-names = "default";
+
+		startup-delay-us = <1000>;
+		regulator-enable-ramp-delay = <1000>;
+
+		vin-supply = <&vreg_display_vdd>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_MISC_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&misc_3p3_reg_en>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_wcn_3p3: regulator-wcn-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wcn_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	usb-1-ss0-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>;
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss0_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss0_sbu>;
+			};
+		};
+	};
+
+	usb-1-ss1-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>;
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss1_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss1_sbu>;
+			};
+		};
+	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&wcn_wlan_bt_en>;
+		pinctrl-names = "default";
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob2>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l12-supply = <&vreg_s5j_1p2>;
+		vdd-l15-supply = <&vreg_s4c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p0: ldo5 {
+			regulator-name = "vreg_l5b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p8: ldo7 {
+			regulator-name = "vreg_l7b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_3p0: ldo8 {
+			regulator-name = "vreg_l8b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p2: ldo12 {
+			regulator-name = "vreg_l12b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p0: ldo14 {
+			regulator-name = "vreg_l14b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l16b_2p9: ldo16 {
+			regulator-name = "vreg_l16b_2p9";
+			regulator-min-microvolt = <2912000>;
+			regulator-max-microvolt = <2912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4c_1p8: smps4 {
+			regulator-name = "vreg_s4c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_0p8: ldo2 {
+			regulator-name = "vreg_l2c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_0p8: ldo3 {
+			regulator-name = "vreg_l3c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s4c_1p8>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_l1d_0p8: ldo1 {
+			regulator-name = "vreg_l1d_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p9: ldo2 {
+			regulator-name = "vreg_l2d_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_1p8: ldo3 {
+			regulator-name = "vreg_l3d_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+
+		vreg_l2e_0p8: ldo2 {
+			regulator-name = "vreg_l2e_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_s1f_0p7: smps1 {
+			regulator-name = "vreg_s1f_0p7";
+			regulator-min-microvolt = <700000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_1p0: ldo1 {
+			regulator-name = "vreg_l1f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p0: ldo2 {
+			regulator-name = "vreg_l2f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p0: ldo3 {
+			regulator-name = "vreg_l3f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "i";
+
+		vdd-l1-supply = <&vreg_s4c_1p8>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+
+		vreg_s1i_0p9: smps1 {
+			regulator-name = "vreg_s1i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2i_1p0: smps2 {
+			regulator-name = "vreg_s2i_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p8: ldo1 {
+			regulator-name = "vreg_l1i_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p8: ldo3 {
+			regulator-name = "vreg_l3i_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "j";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s5j_1p2: smps5 {
+			regulator-name = "vreg_s5j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p8: ldo1 {
+			regulator-name = "vreg_l1j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3j_0p8: ldo3 {
+			regulator-name = "vreg_l3j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+       status = "okay";
+
+       zap-shader {
+               firmware-name = "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qcdxkmsuc8380.mbn";
+       };
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	keyboard@5 {
+		compatible = "hid-over-i2c";
+		reg = <0x5>;
+
+		hid-descr-addr = <0x20>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&kybd_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb0_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l2b_3p0>;
+		vdd1v8-supply = <&vreg_l3d_1p8>;
+
+		reset-gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb0_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb1_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l14b_3p0>;
+		vdd1v8-supply = <&vreg_l3d_1p8>;
+
+		reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb1_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c6 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb5_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l8b_3p0>;
+		vdd1v8-supply = <&vreg_l3d_1p8>;
+
+		reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb5_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c18 {
+	eusb6_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 74 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb6_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchscreen@5d {
+		compatible = "hid-over-i2c";
+		reg = <0x5d>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		/* Lower power supply is not enoug to work. */
+		// vddl-supply = <&vreg_l15b_1p8>;
+
+		pinctrl-0 = <&ts0_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c13 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	spkr_23_sd_n_active: spkr-23-sd-n-active-state {
+		pins = "gpio13";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l1b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp2 {
+	status = "okay";
+};
+
+&mdss_dp2_out {
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dp3 {
+	/delete-property/ #sound-dai-cells;
+
+	pinctrl-0 = <&edp0_hpd_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	aux-bus {
+		panel: panel {
+			compatible = "samsung,atna60cl07", "samsung,atna33xc20";
+			enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+			power-supply = <&vreg_edp_3p3>;
+			hpd-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>;
+
+			pinctrl-0 = <&edp_bl_en>;
+			pinctrl-names = "default";
+
+			port {
+				edp_panel_in: endpoint {
+					remote-endpoint = <&mdss_dp3_out>;
+				};
+			};
+		};
+	};
+
+	ports {
+		port@1 {
+			reg = <1>;
+			mdss_dp3_out: endpoint {
+				data-lanes = <0 1 2 3>;
+				link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
+
+				remote-endpoint = <&edp_panel_in>;
+			};
+		};
+	};
+};
+
+
+&mdss_dp3_phy {
+	vdda-phy-supply = <&vreg_l3j_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+	};
+};
+
+&pm8550ve_8_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-disable;
+		input-disable;
+		output-enable;
+		drive-push-pull;
+		power-source = <1>; /* 1.8 V */
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+	};
+};
+
+&pmc8380_3_gpios {
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio4";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		input-disable;
+		output-enable;
+	};
+};
+
+&qupv3_0 {
+	status = "okay";
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&qupv3_2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qcadsp8380.mbn",
+			"qcom/x1e80100/SAMSUNG/galaxy-book4-edge/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qccdsp8380.mbn",
+			"qcom/x1e80100/SAMSUNG/galaxy-book4-edge/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&swr0 {
+	status = "okay";
+
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	/* WSA8845, Left Woofer */
+	left_woofer: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "WooferLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Left Tweeter */
+	left_tweeter: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TweeterLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
+&swr3 {
+	status = "okay";
+
+	pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>;
+	pinctrl-names = "default";
+
+	/* WSA8845, Right Woofer */
+	right_woofer: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "WooferRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right Tweeter */
+	right_tweeter: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TweeterRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <34 2>, /* Unused */
+			       <44 4>; /* SPI (TPM) */
+
+	edp_reg_en: edp-reg-en-state {
+		pins = "gpio70";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-pull-up;
+		output-low;
+	};
+
+	octa_vdd_en: octa-vdd-en-state {
+		pins = "gpio111";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-pull-up;
+		output-high;
+	};
+
+	display_vdd_en: display-vdd-en-state {
+		pins = "gpio120";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-pull-up;
+		output-high;
+	};
+
+	edp0_hpd_default: edp0-hpd-default-state {
+		pins = "gpio119";
+		function = "edp0_hot";
+		bias-pull-down;
+		input-enable;
+		drive-strength = <2>;
+	};
+
+
+	hall_int_n_default: hall-int-n-state {
+		pins = "gpio92";
+		function = "gpio";
+		bias-disable;
+	};
+
+	kybd_default: kybd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		bias-disable;
+	};
+
+	hdmi_hpd_default: hdmi-hpd-default-state {
+		pins = "gpio126";
+		function = "usb2_dp";
+		bias-disable;
+	};
+
+	eusb0_reset_n: eusb0-reset-n-state {
+		pins = "gpio10";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb1_reset_n: eusb1-reset-n-state {
+		pins = "gpio19";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb5_reset_n: eusb5-reset-n-state {
+		pins = "gpio26";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb6_reset_n: eusb6-reset-n-state {
+		pins = "gpio74";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	tpad_default: tpad-default-state {
+		pins = "gpio3";
+		function = "gpio";
+		bias-disable;
+	};
+
+	ts0_default: ts0-default-state {
+		int-n-pins {
+			pins = "gpio34";
+			function = "gpio";
+			bias-disable;
+		};
+
+		reset-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			output-high;
+			drive-strength = <16>;
+		};
+	};
+
+	wcn_sw_en: wcn-sw-en-state {
+		pins = "gpio214";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
+		pins = "gpio116", "gpio117";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&ufs_mem_hc {
+	status = "okay";
+
+	reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l17b_2p5>;
+	vcc-max-microamp = <600000>;
+
+	vccq-supply = <&vreg_l2i_1p2>;
+	vccq-max-microamp = <600000>;
+};
+
+&ufs_mem_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+		max-speed = <3200000>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+	};
+};
+
+&uart21 {
+	compatible = "qcom,geni-debug-uart";
+	status = "okay";
+};
+
+/* usb1 covers left side typec ports */
+
+/* back(towards the display) typec port */
+&usb_1_ss0 {
+	status = "okay";
+};
+
+&usb_1_ss0_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l1j_0p8>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss0_ss_in>;
+};
+
+/* front typec port */
+&usb_1_ss1 {
+	status = "okay";
+};
+
+&usb_1_ss1_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss1_ss_in>;
+};
+
+/* DP-HDMI bridge connected here? */
+&usb_1_ss2_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	qcom,combo-initial-mode = "dp";
+
+	/delete-property/ mode-switch;
+	/delete-property/ orientation-switch;
+
+	status = "okay";
+};
+
+&usb_1_ss2_qmpphy_out {
+	remote-endpoint = <&hdmi_con>;
+};
+
+
+/* MP0 goes to the USB-A port(USB3) and FPC */
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&usb_mp_hsphy1 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge-14.dts b/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge-14.dts
new file mode 100644
index 000000000..1713ea4ce
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge-14.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include "x1-samsung-galaxy-book4-edge.dtsi"
+
+/ {
+	model = "Samsung Galaxy Book4 Edge (14 inch)";
+	compatible = "samsung,galaxy-book4-edge-14", "samsung,galaxy-book4-edge",
+		     "qcom,x1e80100";
+
+};
+
+&i2c13 {
+	touchpad@40 {
+		compatible = "hid-over-i2c";
+		reg = <0x40>;
+
+		hid-descr-addr = <0xe>;
+		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&tpad_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&panel {
+	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
+	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+	power-supply = <&vreg_edp_3p3>;
+	no-hpd;
+
+	pinctrl-0 = <&edp_bl_en>;
+	pinctrl-names = "default";
+
+	port {
+		edp_panel_in: endpoint {
+			remote-endpoint = <&mdss_dp3_out>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/x1e84100-samsung-galaxy-book4-edge-16.dts b/arch/arm64/boot/dts/qcom/x1e84100-samsung-galaxy-book4-edge-16.dts
new file mode 100644
index 000000000..1bc49d994
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/x1e84100-samsung-galaxy-book4-edge-16.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include "x1-samsung-galaxy-book4-edge.dtsi"
+
+/ {
+	model = "Samsung Galaxy Book4 Edge (16 inch)";
+	compatible = "samsung,galaxy-book4-edge-16", "samsung,galaxy-book4-edge",
+		     "qcom,x1e80100";
+};
+
+&i2c13 {
+	touchpad@50 {
+		compatible = "hid-over-i2c";
+		reg = <0x50>;
+
+		hid-descr-addr = <0xd1>;
+		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l15b_1p8>;
+
+		pinctrl-0 = <&tpad_default>;
+		pinctrl-names = "default";
+	};
+};
+
+
+
+
-- 
2.43.0

Re: [PATCH v6 1/3] firmware: qcom: scm: Allow QSEECOM on Samsung Galaxy Book4 Edge

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 05:03:10PM +0100, Maxim Storetvedt wrote:
> Signed-off-by: Maxim Storetvedt <mstoretv@cern.ch>
> ---
>  drivers/firmware/qcom/qcom_scm.c | 1 +
>  1 file changed, 1 insertion(+)

Missing commit message.

Also, please don't send next iterations as a reply to the previous
series. Always start a new thread.

> 
> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
> index 5c4375a7f..5d3de476c 100644
> --- a/drivers/firmware/qcom/qcom_scm.c
> +++ b/drivers/firmware/qcom/qcom_scm.c
> @@ -2318,6 +2318,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
>  	{ .compatible = "qcom,x1e80100-crd" },
>  	{ .compatible = "qcom,x1e80100-qcp" },
>  	{ .compatible = "qcom,x1p42100-crd" },
> +	{ .compatible = "samsung,galaxy-book4-edge"},
>  	{ }
>  };
>  
> -- 
> 2.43.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Konrad Dybcio]

On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
> 
> These use a common dtsi derived from nodes that were able to work on Linux
> from the initial Galaxy Book4 Edge DTS by Marcus:
> 
> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
> 
> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
> Valentin Manea, which shares device similarities:

[...]

> +	model = "Samsung Galaxy Book4 Edge";
> +	compatible = "samsung,galaxy-book4-edge", "qcom,x1e80100";
> +	chassis-type = "laptop";
> +
> +	aliases {
> +		serial0 = &uart21;
> +		serial1 = &uart14;
> +	};
> +
> +	wcd938x: audio-codec {
> +		compatible = "qcom,wcd9385-codec";
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&wcd_default>;

property-n
property-names

in this order, file-wide, please

[...]

> +	pmic-glink {
> +		compatible = "qcom,x1e80100-pmic-glink",
> +			     "qcom,pmic-glink";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
> +				    <&tlmm 123 GPIO_ACTIVE_HIGH>,
> +				    <&tlmm 125 GPIO_ACTIVE_HIGH>;

You provide 3 orientation-gpios but there's only two ports

[...]

> +	sound {
> +		compatible = "qcom,x1e80100-sndcard";
> +		model = "X1E80100-CRD";

This should reflect the actual machine

> +		audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
> +				"TweeterLeft IN", "WSA WSA_SPK2 OUT",
> +				"WooferRight IN", "WSA2 WSA_SPK2 OUT",
> +				"TweeterRight IN", "WSA2 WSA_SPK2 OUT",
> +				"IN1_HPHL", "HPHL_OUT",
> +				"IN2_HPHR", "HPHR_OUT",
> +				"AMIC2", "MIC BIAS2",
> +				"VA DMIC0", "MIC BIAS3",
> +				"VA DMIC1", "MIC BIAS3",
> +				"VA DMIC2", "MIC BIAS1",
> +				"VA DMIC3", "MIC BIAS1",
> +				"VA DMIC0", "VA MIC BIAS3",
> +				"VA DMIC1", "VA MIC BIAS3",
> +				"VA DMIC2", "VA MIC BIAS1",
> +				"VA DMIC3", "VA MIC BIAS1",

See:

b49e37de8e70 ("arm64: dts: qcom: x1e80100-crd: Drop duplicate DMIC supplies")


> +				"TX SWR_INPUT1", "ADC2_OUTPUT";
> +
> +		wcd-playback-dai-link {
> +			link-name = "WCD Playback";
> +
> +			cpu {
> +				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
> +			};
> +
> +			codec {

'co'dec < 'cp'u, please reorder

[...]

> +&i2c8 {
> +	clock-frequency = <400000>;
> +
> +	status = "okay";
> +
> +	touchscreen@5d {
> +		compatible = "hid-over-i2c";
> +		reg = <0x5d>;
> +
> +		hid-descr-addr = <0x1>;
> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
> +
> +		vdd-supply = <&vreg_misc_3p3>;
> +		/* Lower power supply is not enoug to work. */
> +		// vddl-supply = <&vreg_l15b_1p8>;

How should we interpret that?

[...]

> +/* usb1 covers left side typec ports */
> +
> +/* back(towards the display) typec port */

You already have these comments near the type-c connector definitions
at the top of the file

[...]

> +/* DP-HDMI bridge connected here? */
> +&usb_1_ss2_qmpphy {
> +	vdda-phy-supply = <&vreg_l2j_1p2>;
> +	vdda-pll-supply = <&vreg_l2d_0p9>;
> +
> +	qcom,combo-initial-mode = "dp";

This was used in some previous version of the QMPPHY-DP-only patchset,
see e.g. x1p42100-lenovo-thinkbook-16.dts and align with that to get
it working again

[...]

> +&panel {
> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";

I think it'd make sense to move the compatible from 'common' to the
16in DTS then too

> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;

this matches the common definition

> +	power-supply = <&vreg_edp_3p3>;

ditto

> +	no-hpd;

really??

Konrad

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Maxim Storetvedt]

On 3/23/26 13:17, Konrad Dybcio wrote:
> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
>>
>> These use a common dtsi derived from nodes that were able to work on Linux
>> from the initial Galaxy Book4 Edge DTS by Marcus:
>>
>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
>>
>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
>> Valentin Manea, which shares device similarities:
> 
> [...]
> 
>> +&i2c8 {
>> +	clock-frequency = <400000>;
>> +
>> +	status = "okay";
>> +
>> +	touchscreen@5d {
>> +		compatible = "hid-over-i2c";
>> +		reg = <0x5d>;
>> +
>> +		hid-descr-addr = <0x1>;
>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
>> +
>> +		vdd-supply = <&vreg_misc_3p3>;
>> +		/* Lower power supply is not enoug to work. */
>> +		// vddl-supply = <&vreg_l15b_1p8>;
> 
> How should we interpret that?
> 

This was in the original patch, but using that same regulator appears to
be enough to also get touchscreen working on the 16" book4e. That said,
it still does not work on the 14". Something to revisit later...

> 
> [...]
> 
>> +&panel {
>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
> 
> I think it'd make sense to move the compatible from 'common' to the
> 16in DTS then too
> 
>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
> 
> this matches the common definition
> 
>> +	power-supply = <&vreg_edp_3p3>;
> 
> ditto
> 
>> +	no-hpd;
> 
> really??
> 
One less thing to debug while previously attempting to work around the
"illegal link rate" error, which turned out to be related to eDP 1.4
(similar to the sp11). I've kept it as-is in case other SKUs attempt
booting from this dts, such as the x1e80100 16" (as it might be getting
a black screen using the current x1e84100 16" dts, though this is not
fully tested).


Worth mentioning is that we originally had two separate devicetrees for
the 14" and 16" SKUs, and the dts for the 16" eventually became this
dtsi. More could indeed still be cleaned and likewise moved to what is
now the 16" dts (i.e. for v7).

Cheers,
-Max

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Konrad Dybcio]

On 3/25/26 7:30 PM, Maxim Storetvedt wrote:
> 
> 
> On 3/23/26 13:17, Konrad Dybcio wrote:
>> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
>>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
>>>
>>> These use a common dtsi derived from nodes that were able to work on Linux
>>> from the initial Galaxy Book4 Edge DTS by Marcus:
>>>
>>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
>>>
>>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
>>> Valentin Manea, which shares device similarities:
>>
>> [...]
>>
>>> +&i2c8 {
>>> +	clock-frequency = <400000>;
>>> +
>>> +	status = "okay";
>>> +
>>> +	touchscreen@5d {
>>> +		compatible = "hid-over-i2c";
>>> +		reg = <0x5d>;
>>> +
>>> +		hid-descr-addr = <0x1>;
>>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
>>> +
>>> +		vdd-supply = <&vreg_misc_3p3>;
>>> +		/* Lower power supply is not enoug to work. */
>>> +		// vddl-supply = <&vreg_l15b_1p8>;
>>
>> How should we interpret that?
>>
> 
> This was in the original patch, but using that same regulator appears to
> be enough to also get touchscreen working on the 16" book4e. That said,
> it still does not work on the 14". Something to revisit later...
> 
>>
>> [...]
>>
>>> +&panel {
>>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
>>
>> I think it'd make sense to move the compatible from 'common' to the
>> 16in DTS then too
>>
>>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
>>
>> this matches the common definition
>>
>>> +	power-supply = <&vreg_edp_3p3>;
>>
>> ditto
>>
>>> +	no-hpd;
>>
>> really??
>>
> One less thing to debug while previously attempting to work around the
> "illegal link rate" error, which turned out to be related to eDP 1.4
> (similar to the sp11). I've kept it as-is in case other SKUs attempt
> booting from this dts, such as the x1e80100 16" (as it might be getting
> a black screen using the current x1e84100 16" dts, though this is not
> fully tested).

So do the 80100 and 84100-equipped SKUs of the laptop come with different
displays?

Konrad

Re: [PATCH v6 2/3] dt-bindings: arm: Add Samsung Galaxy Book4 Edge

[Krzysztof Kozlowski]

On 22/03/2026 17:03, Maxim Storetvedt wrote:
> From: Marcus Glocker <marcus@nazgul.ch>
> 
> Add the Samsung Galaxy Book4 Edge compatibility binding.
> 
> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Incomplete DCO. Please read submitting patches about certification you
have to make.

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets. See also:
https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L830

Please organize the patch documenting the compatible (DT bindings)
before the patch using that compatible.
See also:
https://elixir.bootlin.com/linux/v6.14-rc6/source/Documentation/devicetree/bindings/submitting-patches.rst#L46

Best regards,
Krzysztof

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Maxim Storetvedt]

On 3/26/26 12:33, Konrad Dybcio wrote:
> On 3/25/26 7:30 PM, Maxim Storetvedt wrote:
>>
>>
>> On 3/23/26 13:17, Konrad Dybcio wrote:
>>> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
>>>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
>>>>
>>>> These use a common dtsi derived from nodes that were able to work on Linux
>>>> from the initial Galaxy Book4 Edge DTS by Marcus:
>>>>
>>>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
>>>>
>>>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
>>>> Valentin Manea, which shares device similarities:
>>>
>>> [...]
>>>
>>>> +&i2c8 {
>>>> +	clock-frequency = <400000>;
>>>> +
>>>> +	status = "okay";
>>>> +
>>>> +	touchscreen@5d {
>>>> +		compatible = "hid-over-i2c";
>>>> +		reg = <0x5d>;
>>>> +
>>>> +		hid-descr-addr = <0x1>;
>>>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
>>>> +
>>>> +		vdd-supply = <&vreg_misc_3p3>;
>>>> +		/* Lower power supply is not enoug to work. */
>>>> +		// vddl-supply = <&vreg_l15b_1p8>;
>>>
>>> How should we interpret that?
>>>
>>
>> This was in the original patch, but using that same regulator appears to
>> be enough to also get touchscreen working on the 16" book4e. That said,
>> it still does not work on the 14". Something to revisit later...
>>
>>>
>>> [...]
>>>
>>>> +&panel {
>>>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
>>>
>>> I think it'd make sense to move the compatible from 'common' to the
>>> 16in DTS then too
>>>
>>>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
>>>
>>> this matches the common definition
>>>
>>>> +	power-supply = <&vreg_edp_3p3>;
>>>
>>> ditto
>>>
>>>> +	no-hpd;
>>>
>>> really??
>>>
>> One less thing to debug while previously attempting to work around the
>> "illegal link rate" error, which turned out to be related to eDP 1.4
>> (similar to the sp11). I've kept it as-is in case other SKUs attempt
>> booting from this dts, such as the x1e80100 16" (as it might be getting
>> a black screen using the current x1e84100 16" dts, though this is not
>> fully tested).
> 
> So do the 80100 and 84100-equipped SKUs of the laptop come with different
> displays?
> 
> Konrad

So far assumed both 16" variants to be fairly similar, though one
valiant 16" 80100 user over in the debug thread did try to boot via the
84100 dts, with no success. Instead having the screen go dark after the
first post-tux kernel prints.

This was strapped together via WSL though, so could be there was
something else at fault, but strange it didn't at least fall back to a
visible initramfs shell.

Cheers,
-Max

Re: [PATCH v6 2/3] dt-bindings: arm: Add Samsung Galaxy Book4 Edge

[Maxim Storetvedt]

On 3/26/26 12:44, Krzysztof Kozlowski wrote:
> On 22/03/2026 17:03, Maxim Storetvedt wrote:
>> From: Marcus Glocker <marcus@nazgul.ch>
>>
>> Add the Samsung Galaxy Book4 Edge compatibility binding.
>>
>> Signed-off-by: Marcus Glocker <marcus@nazgul.ch>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> Incomplete DCO. Please read submitting patches about certification you
> have to make.
> 
> Do not attach (thread) your patchsets to some other threads (unrelated
> or older versions). This buries them deep in the mailbox and might
> interfere with applying entire sets. See also:
> https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L830
> 
> Please organize the patch documenting the compatible (DT bindings)
> before the patch using that compatible.
> See also:
> https://elixir.bootlin.com/linux/v6.14-rc6/source/Documentation/devicetree/bindings/submitting-patches.rst#L46
> 
> Best regards,
> Krzysztof

Duly noted. There's already plenty of useful info/feedback added here,
so appreciate the responses despite the entangled thread. To be
continued in next (and hopefully correctly threaded) patch revision.

Cheers,
-Max

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Konrad Dybcio]

On 3/26/26 7:30 PM, Maxim Storetvedt wrote:
> 
> 
> On 3/26/26 12:33, Konrad Dybcio wrote:
>> On 3/25/26 7:30 PM, Maxim Storetvedt wrote:
>>>
>>>
>>> On 3/23/26 13:17, Konrad Dybcio wrote:
>>>> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
>>>>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
>>>>>
>>>>> These use a common dtsi derived from nodes that were able to work on Linux
>>>>> from the initial Galaxy Book4 Edge DTS by Marcus:
>>>>>
>>>>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
>>>>>
>>>>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
>>>>> Valentin Manea, which shares device similarities:
>>>>
>>>> [...]
>>>>
>>>>> +&i2c8 {
>>>>> +	clock-frequency = <400000>;
>>>>> +
>>>>> +	status = "okay";
>>>>> +
>>>>> +	touchscreen@5d {
>>>>> +		compatible = "hid-over-i2c";
>>>>> +		reg = <0x5d>;
>>>>> +
>>>>> +		hid-descr-addr = <0x1>;
>>>>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
>>>>> +
>>>>> +		vdd-supply = <&vreg_misc_3p3>;
>>>>> +		/* Lower power supply is not enoug to work. */
>>>>> +		// vddl-supply = <&vreg_l15b_1p8>;
>>>>
>>>> How should we interpret that?
>>>>
>>>
>>> This was in the original patch, but using that same regulator appears to
>>> be enough to also get touchscreen working on the 16" book4e. That said,
>>> it still does not work on the 14". Something to revisit later...
>>>
>>>>
>>>> [...]
>>>>
>>>>> +&panel {
>>>>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
>>>>
>>>> I think it'd make sense to move the compatible from 'common' to the
>>>> 16in DTS then too
>>>>
>>>>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
>>>>
>>>> this matches the common definition
>>>>
>>>>> +	power-supply = <&vreg_edp_3p3>;
>>>>
>>>> ditto
>>>>
>>>>> +	no-hpd;
>>>>
>>>> really??
>>>>
>>> One less thing to debug while previously attempting to work around the
>>> "illegal link rate" error, which turned out to be related to eDP 1.4
>>> (similar to the sp11). I've kept it as-is in case other SKUs attempt
>>> booting from this dts, such as the x1e80100 16" (as it might be getting
>>> a black screen using the current x1e84100 16" dts, though this is not
>>> fully tested).
>>
>> So do the 80100 and 84100-equipped SKUs of the laptop come with different
>> displays?
>>
>> Konrad
> 
> So far assumed both 16" variants to be fairly similar, though one
> valiant 16" 80100 user over in the debug thread did try to boot via the
> 84100 dts, with no success. Instead having the screen go dark after the
> first post-tux kernel prints.

Does switching to the generic edp-panel compatible (which will parse the
EDID and try not to be overly smart about it) help here?

> This was strapped together via WSL though, so could be there was
> something else at fault, but strange it didn't at least fall back to a
> visible initramfs shell.

You mean the kernel had been compiled via WSL? That shouldn't be a problem..

Konrad

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Dmitry Baryshkov]

On Mon, Mar 30, 2026 at 12:41:57PM +0200, Konrad Dybcio wrote:
> On 3/26/26 7:30 PM, Maxim Storetvedt wrote:
> > 
> > 
> > On 3/26/26 12:33, Konrad Dybcio wrote:
> >> On 3/25/26 7:30 PM, Maxim Storetvedt wrote:
> >>>
> >>>
> >>> On 3/23/26 13:17, Konrad Dybcio wrote:
> >>>> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
> >>>>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
> >>>>>
> >>>>> These use a common dtsi derived from nodes that were able to work on Linux
> >>>>> from the initial Galaxy Book4 Edge DTS by Marcus:
> >>>>>
> >>>>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
> >>>>>
> >>>>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
> >>>>> Valentin Manea, which shares device similarities:
> >>>>
> >>>> [...]
> >>>>
> >>>>> +&i2c8 {
> >>>>> +	clock-frequency = <400000>;
> >>>>> +
> >>>>> +	status = "okay";
> >>>>> +
> >>>>> +	touchscreen@5d {
> >>>>> +		compatible = "hid-over-i2c";
> >>>>> +		reg = <0x5d>;
> >>>>> +
> >>>>> +		hid-descr-addr = <0x1>;
> >>>>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
> >>>>> +
> >>>>> +		vdd-supply = <&vreg_misc_3p3>;
> >>>>> +		/* Lower power supply is not enoug to work. */
> >>>>> +		// vddl-supply = <&vreg_l15b_1p8>;
> >>>>
> >>>> How should we interpret that?
> >>>>
> >>>
> >>> This was in the original patch, but using that same regulator appears to
> >>> be enough to also get touchscreen working on the 16" book4e. That said,
> >>> it still does not work on the 14". Something to revisit later...
> >>>
> >>>>
> >>>> [...]
> >>>>
> >>>>> +&panel {
> >>>>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
> >>>>
> >>>> I think it'd make sense to move the compatible from 'common' to the
> >>>> 16in DTS then too
> >>>>
> >>>>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
> >>>>
> >>>> this matches the common definition
> >>>>
> >>>>> +	power-supply = <&vreg_edp_3p3>;
> >>>>
> >>>> ditto
> >>>>
> >>>>> +	no-hpd;
> >>>>
> >>>> really??
> >>>>
> >>> One less thing to debug while previously attempting to work around the
> >>> "illegal link rate" error, which turned out to be related to eDP 1.4
> >>> (similar to the sp11). I've kept it as-is in case other SKUs attempt
> >>> booting from this dts, such as the x1e80100 16" (as it might be getting
> >>> a black screen using the current x1e84100 16" dts, though this is not
> >>> fully tested).
> >>
> >> So do the 80100 and 84100-equipped SKUs of the laptop come with different
> >> displays?
> >>
> >> Konrad
> > 
> > So far assumed both 16" variants to be fairly similar, though one
> > valiant 16" 80100 user over in the debug thread did try to boot via the
> > 84100 dts, with no success. Instead having the screen go dark after the
> > first post-tux kernel prints.
> 
> Does switching to the generic edp-panel compatible (which will parse the
> EDID and try not to be overly smart about it) help here?

I think it was not possible because those panels need special treatment.

> 
> > This was strapped together via WSL though, so could be there was
> > something else at fault, but strange it didn't at least fall back to a
> > visible initramfs shell.
> 
> You mean the kernel had been compiled via WSL? That shouldn't be a problem..
> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Maxim Storetvedt]

On 3/30/26 12:41, Konrad Dybcio wrote:
> On 3/26/26 7:30 PM, Maxim Storetvedt wrote:
>>
>>
>> On 3/26/26 12:33, Konrad Dybcio wrote:
>>> On 3/25/26 7:30 PM, Maxim Storetvedt wrote:
>>>>
>>>>
>>>> On 3/23/26 13:17, Konrad Dybcio wrote:
>>>>> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
>>>>>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
>>>>>>
>>>>>> These use a common dtsi derived from nodes that were able to work on Linux
>>>>>> from the initial Galaxy Book4 Edge DTS by Marcus:
>>>>>>
>>>>>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
>>>>>>
>>>>>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
>>>>>> Valentin Manea, which shares device similarities:
>>>>>
>>>>> [...]
>>>>>
>>>>>> +&i2c8 {
>>>>>> +	clock-frequency = <400000>;
>>>>>> +
>>>>>> +	status = "okay";
>>>>>> +
>>>>>> +	touchscreen@5d {
>>>>>> +		compatible = "hid-over-i2c";
>>>>>> +		reg = <0x5d>;
>>>>>> +
>>>>>> +		hid-descr-addr = <0x1>;
>>>>>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
>>>>>> +
>>>>>> +		vdd-supply = <&vreg_misc_3p3>;
>>>>>> +		/* Lower power supply is not enoug to work. */
>>>>>> +		// vddl-supply = <&vreg_l15b_1p8>;
>>>>>
>>>>> How should we interpret that?
>>>>>
>>>>
>>>> This was in the original patch, but using that same regulator appears to
>>>> be enough to also get touchscreen working on the 16" book4e. That said,
>>>> it still does not work on the 14". Something to revisit later...
>>>>
>>>>>
>>>>> [...]
>>>>>
>>>>>> +&panel {
>>>>>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
>>>>>
>>>>> I think it'd make sense to move the compatible from 'common' to the
>>>>> 16in DTS then too
>>>>>
>>>>>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
>>>>>
>>>>> this matches the common definition
>>>>>
>>>>>> +	power-supply = <&vreg_edp_3p3>;
>>>>>
>>>>> ditto
>>>>>
>>>>>> +	no-hpd;
>>>>>
>>>>> really??
>>>>>
>>>> One less thing to debug while previously attempting to work around the
>>>> "illegal link rate" error, which turned out to be related to eDP 1.4
>>>> (similar to the sp11). I've kept it as-is in case other SKUs attempt
>>>> booting from this dts, such as the x1e80100 16" (as it might be getting
>>>> a black screen using the current x1e84100 16" dts, though this is not
>>>> fully tested).
>>>
>>> So do the 80100 and 84100-equipped SKUs of the laptop come with different
>>> displays?
>>>
>>> Konrad
>>
>> So far assumed both 16" variants to be fairly similar, though one
>> valiant 16" 80100 user over in the debug thread did try to boot via the
>> 84100 dts, with no success. Instead having the screen go dark after the
>> first post-tux kernel prints.
> 
> Does switching to the generic edp-panel compatible (which will parse the
> EDID and try not to be overly smart about it) help here?
> 
>> This was strapped together via WSL though, so could be there was
>> something else at fault, but strange it didn't at least fall back to a
>> visible initramfs shell.
> 
> You mean the kernel had been compiled via WSL? That shouldn't be a problem..
> 
> Konrad

Kernel was one shared by me in advance (same I've been using as a
daily), so it should be OK, but there was an uphill battle in creating
the modified system image afaik (that would boot).

Can only speculate until there is another go at this, but could likewise
be something completely unrelated that's simple to fix, e.g. older mesa
in image, but final attempt at boot used a dts with gpu node enabled.

Cheers,
-Max

Re: [PATCH v6 3/3] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS/DTSI

[Konrad Dybcio]

On 3/31/26 6:34 PM, Maxim Storetvedt wrote:
> 
> 
> On 3/30/26 12:41, Konrad Dybcio wrote:
>> On 3/26/26 7:30 PM, Maxim Storetvedt wrote:
>>>
>>>
>>> On 3/26/26 12:33, Konrad Dybcio wrote:
>>>> On 3/25/26 7:30 PM, Maxim Storetvedt wrote:
>>>>>
>>>>>
>>>>> On 3/23/26 13:17, Konrad Dybcio wrote:
>>>>>> On 3/22/26 5:03 PM, Maxim Storetvedt wrote:
>>>>>>> Adds devicetrees for the 14-inch and 16-inch SKUs of the Samsung Galaxy Book4 Edge.
>>>>>>>
>>>>>>> These use a common dtsi derived from nodes that were able to work on Linux
>>>>>>> from the initial Galaxy Book4 Edge DTS by Marcus:
>>>>>>>
>>>>>>> Link: https://lore.kernel.org/all/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
>>>>>>>
>>>>>>> combined with the ongoing patch for the Honor Magicbook Art 14, and its downstream by
>>>>>>> Valentin Manea, which shares device similarities:
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> +&i2c8 {
>>>>>>> +	clock-frequency = <400000>;
>>>>>>> +
>>>>>>> +	status = "okay";
>>>>>>> +
>>>>>>> +	touchscreen@5d {
>>>>>>> +		compatible = "hid-over-i2c";
>>>>>>> +		reg = <0x5d>;
>>>>>>> +
>>>>>>> +		hid-descr-addr = <0x1>;
>>>>>>> +		interrupts-extended = <&tlmm 34 IRQ_TYPE_LEVEL_LOW>;
>>>>>>> +
>>>>>>> +		vdd-supply = <&vreg_misc_3p3>;
>>>>>>> +		/* Lower power supply is not enoug to work. */
>>>>>>> +		// vddl-supply = <&vreg_l15b_1p8>;
>>>>>>
>>>>>> How should we interpret that?
>>>>>>
>>>>>
>>>>> This was in the original patch, but using that same regulator appears to
>>>>> be enough to also get touchscreen working on the 16" book4e. That said,
>>>>> it still does not work on the 14". Something to revisit later...
>>>>>
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> +&panel {
>>>>>>> +	compatible = "samsung,atna40cu07", "samsung,atna33xc20";
>>>>>>
>>>>>> I think it'd make sense to move the compatible from 'common' to the
>>>>>> 16in DTS then too
>>>>>>
>>>>>>> +	enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
>>>>>>
>>>>>> this matches the common definition
>>>>>>
>>>>>>> +	power-supply = <&vreg_edp_3p3>;
>>>>>>
>>>>>> ditto
>>>>>>
>>>>>>> +	no-hpd;
>>>>>>
>>>>>> really??
>>>>>>
>>>>> One less thing to debug while previously attempting to work around the
>>>>> "illegal link rate" error, which turned out to be related to eDP 1.4
>>>>> (similar to the sp11). I've kept it as-is in case other SKUs attempt
>>>>> booting from this dts, such as the x1e80100 16" (as it might be getting
>>>>> a black screen using the current x1e84100 16" dts, though this is not
>>>>> fully tested).
>>>>
>>>> So do the 80100 and 84100-equipped SKUs of the laptop come with different
>>>> displays?
>>>>
>>>> Konrad
>>>
>>> So far assumed both 16" variants to be fairly similar, though one
>>> valiant 16" 80100 user over in the debug thread did try to boot via the
>>> 84100 dts, with no success. Instead having the screen go dark after the
>>> first post-tux kernel prints.
>>
>> Does switching to the generic edp-panel compatible (which will parse the
>> EDID and try not to be overly smart about it) help here?
>>
>>> This was strapped together via WSL though, so could be there was
>>> something else at fault, but strange it didn't at least fall back to a
>>> visible initramfs shell.
>>
>> You mean the kernel had been compiled via WSL? That shouldn't be a problem..
>>
>> Konrad
> 
> Kernel was one shared by me in advance (same I've been using as a
> daily), so it should be OK, but there was an uphill battle in creating
> the modified system image afaik (that would boot).
> 
> Can only speculate until there is another go at this, but could likewise
> be something completely unrelated that's simple to fix, e.g. older mesa
> in image, but final attempt at boot used a dts with gpu node enabled.

FWIW the GPU and display engine are completely disjoint, so mesa itself
shouldn't be an issue (unless something was caught in a restart loop due
to poor error handling.. I've seen that N years ago but have no clue
that would still be a problem nowadays)

Konrad