From: "Luca Weiss" <luca.weiss@fairphone.com>
To: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
<andersson@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <bp@alien8.de>,
<tony.luck@intel.com>
Cc: <quic_saipraka@quicinc.com>, <konrad.dybcio@linaro.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<james.morse@arm.com>, <mchehab@kernel.org>, <rric@kernel.org>,
<linux-edac@vger.kernel.org>, <quic_ppareek@quicinc.com>
Subject: Re: [PATCH v2 13/13] qcom: llcc/edac: Support polling mode for ECC handling
Date: Mon, 12 Dec 2022 16:53:49 +0100 [thread overview]
Message-ID: <COZYL8MWN97H.MROQ391BGA09@otso> (raw)
In-Reply-To: <20221212123311.146261-14-manivannan.sadhasivam@linaro.org>
Hi Manivannan,
On Mon Dec 12, 2022 at 1:33 PM CET, Manivannan Sadhasivam wrote:
> Not all Qcom platforms support IRQ mode for ECC handling. For those
> platforms, the current EDAC driver will not be probed due to missing ECC
> IRQ in devicetree.
>
> So add support for polling mode so that the EDAC driver can be used on all
> Qcom platforms supporting LLCC.
>
> The polling delay of 5000ms is chosed based on Qcom downstream/vendor
> driver.
I think it does work for me on SM6350, I get this in dmesg:
[ 0.054608] EDAC MC: Ver: 3.0.0
[ 0.273913] EDAC DEVICE0: Giving out device to module qcom_llcc_edac controller llcc: DEV qcom_llcc_edac (POLLED)
What I've noticed though is that the 5000ms poll you defined in the
driver doesn't seem to be reflected at runtime? Or am I looking at
different things?
/ # cat /sys/devices/system/edac/qcom-llcc/poll_msec
1000
Regards
Luca
>
> Reported-by: Luca Weiss <luca.weiss@fairphone.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++-----------
> drivers/soc/qcom/llcc-qcom.c | 13 ++++++-------
> 2 files changed, 32 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> index 5be93577fc03..f7afb5375293 100644
> --- a/drivers/edac/qcom_edac.c
> +++ b/drivers/edac/qcom_edac.c
> @@ -76,6 +76,8 @@
> #define DRP0_INTERRUPT_ENABLE BIT(6)
> #define SB_DB_DRP_INTERRUPT_ENABLE 0x3
>
> +#define ECC_POLL_MSEC 5000
> +
> enum {
> LLCC_DRAM_CE = 0,
> LLCC_DRAM_UE,
> @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
> return ret;
> }
>
> -static irqreturn_t
> -llcc_ecc_irq_handler(int irq, void *edev_ctl)
> +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl)
> {
> struct edac_device_ctl_info *edac_dev_ctl = edev_ctl;
> struct llcc_drv_data *drv = edac_dev_ctl->pvt_info;
> @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl)
> return irq_rc;
> }
>
> +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl)
> +{
> + llcc_ecc_irq_handler(0, edev_ctl);
> +}
> +
> static int qcom_llcc_edac_probe(struct platform_device *pdev)
> {
> struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
> @@ -356,22 +362,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev)
> edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
> edev_ctl->pvt_info = llcc_driv_data;
>
> + /* Check if LLCC driver has passed ECC IRQ */
> + ecc_irq = llcc_driv_data->ecc_irq;
> + if (ecc_irq > 0) {
> + /* Use interrupt mode if IRQ is available */
> + edac_op_state = EDAC_OPSTATE_INT;
> + } else {
> + /* Fall back to polling mode otherwise */
> + edac_op_state = EDAC_OPSTATE_POLL;
> + edev_ctl->poll_msec = ECC_POLL_MSEC;
> + edev_ctl->edac_check = llcc_ecc_check;
> + }
> +
> rc = edac_device_add_device(edev_ctl);
> if (rc)
> goto out_mem;
>
> platform_set_drvdata(pdev, edev_ctl);
>
> - /* Request for ecc irq */
> - ecc_irq = llcc_driv_data->ecc_irq;
> - if (ecc_irq < 0) {
> - rc = -ENODEV;
> - goto out_dev;
> - }
> - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
> + /* Request ECC IRQ if available */
> + if (ecc_irq > 0) {
> + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
> IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
> - if (rc)
> - goto out_dev;
> + if (rc)
> + goto out_dev;
> + }
>
> return rc;
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index a29f22dad7fa..e044e6756415 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> goto err;
>
> drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
> - if (drv_data->ecc_irq >= 0) {
> - llcc_edac = platform_device_register_data(&pdev->dev,
> - "qcom_llcc_edac", -1, drv_data,
> - sizeof(*drv_data));
> - if (IS_ERR(llcc_edac))
> - dev_err(dev, "Failed to register llcc edac driver\n");
> - }
> +
> + llcc_edac = platform_device_register_data(&pdev->dev,
> + "qcom_llcc_edac", -1, drv_data,
> + sizeof(*drv_data));
> + if (IS_ERR(llcc_edac))
> + dev_err(dev, "Failed to register llcc edac driver\n");
>
> return 0;
> err:
> --
> 2.25.1
next prev parent reply other threads:[~2022-12-12 15:53 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-12 12:32 [PATCH v2 00/13] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2022-12-12 12:32 ` [PATCH v2 01/13] dt-bindings: arm: msm: Update the maintainers for LLCC Manivannan Sadhasivam
2022-12-13 16:20 ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 02/13] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2022-12-13 16:24 ` Krzysztof Kozlowski
2022-12-13 17:30 ` Manivannan Sadhasivam
2022-12-13 18:34 ` Krzysztof Kozlowski
2022-12-13 16:28 ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 03/13] arm64: dts: qcom: sdm845: Fix the base addresses of " Manivannan Sadhasivam
2022-12-13 5:04 ` Sai Prakash Ranjan
2022-12-13 16:27 ` Krzysztof Kozlowski
2022-12-13 17:13 ` Manivannan Sadhasivam
2022-12-13 18:37 ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 04/13] arm64: dts: qcom: sc7180: Remove reg-names property from LLCC node Manivannan Sadhasivam
2022-12-13 5:05 ` Sai Prakash Ranjan
2022-12-13 16:30 ` Krzysztof Kozlowski
2022-12-13 17:16 ` Manivannan Sadhasivam
2022-12-12 12:33 ` [PATCH v2 05/13] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Manivannan Sadhasivam
2022-12-13 5:06 ` Sai Prakash Ranjan
2022-12-13 16:30 ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 06/13] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2022-12-13 5:06 ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 07/13] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2022-12-13 5:07 ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 08/13] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2022-12-13 5:07 ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 09/13] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2022-12-13 5:08 ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 10/13] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2022-12-13 5:08 ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 11/13] arm64: dts: qcom: sm6350: Remove reg-names property from LLCC node Manivannan Sadhasivam
2022-12-13 5:09 ` Sai Prakash Ranjan
2022-12-13 16:31 ` Krzysztof Kozlowski
2022-12-13 17:17 ` Manivannan Sadhasivam
2022-12-12 12:33 ` [PATCH v2 12/13] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Manivannan Sadhasivam
2022-12-13 16:37 ` Krzysztof Kozlowski
2022-12-13 17:44 ` Manivannan Sadhasivam
2022-12-13 18:44 ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 13/13] qcom: llcc/edac: Support polling mode for ECC handling Manivannan Sadhasivam
2022-12-12 15:53 ` Luca Weiss [this message]
2022-12-12 16:16 ` Manivannan Sadhasivam
2022-12-12 19:23 ` [PATCH v2 00/13] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Andrew Halaney
2022-12-13 5:28 ` Manivannan Sadhasivam
2022-12-13 16:17 ` Andrew Halaney
2022-12-13 16:54 ` Krzysztof Kozlowski
2022-12-13 17:57 ` Manivannan Sadhasivam
2022-12-13 18:47 ` Krzysztof Kozlowski
2022-12-19 13:50 ` Manivannan Sadhasivam
2022-12-19 14:11 ` Krzysztof Kozlowski
2022-12-19 14:16 ` Manivannan Sadhasivam
2022-12-19 14:21 ` Krzysztof Kozlowski
2022-12-19 16:49 ` Dmitry Baryshkov
2022-12-19 17:31 ` Manivannan Sadhasivam
2022-12-19 18:31 ` Manivannan Sadhasivam
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