[PATCH v16 0/2] Add DT support for Multiport controller on SC8280XP

[PATCH v16 0/2] Add DT support for Multiport controller on SC8280XP

[Krishna Kurapati]

Series [1] introduces binding and driver support for DWC3 Multiport
controllers. This series adds support for tertiary controller of SC8280
and enabled multiport controller for SA8295P-ADP platform.

Till v13 [2] the DT was pushed along with driver code. Separated the DT
changes from driver update and pushing it as this series. The first two
versions were marked as v1 and v2. Marked this as v16 to avoid missing
of change log till v13.

Changes in v16:
Marked it as v16 rather than v3 since till v13, there were DT changes
sent along with driver code but were separated and this version is
supposed to be v16.
Fixed interrupt triggers from EDGE_RISING to EDGE_BOTH.

Link to v15:
https://lore.kernel.org/all/20240213082724.1789096-1-quic_kriskura@quicinc.com/

Changes in v15:
SA8540 Ride related code changes have been dropped and will pushed later
due to unavailability of hardware with either Andrew or me for testing the
gpio hog changes suggested in v1.
Implemented vbus boost regulators as fixed regulators instead of modelling
their enable pins as pinctrl nodes.

Link to v14:
https://lore.kernel.org/all/20240206114745.1388491-1-quic_kriskura@quicinc.com/

[1]: https://lore.kernel.org/all/20240420044901.884098-1-quic_kriskura@quicinc.com/
[2]: https://lore.kernel.org/all/20231007154806.605-1-quic_kriskura@quicinc.com/#r

Krishna Kurapati (2):
  arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller
  arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
    ports

 arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 83 ++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi   | 82 +++++++++++++++++++++++
 2 files changed, 165 insertions(+)

-- 
2.34.1

[PATCH v16 1/2] arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller

[Krishna Kurapati]

Add USB and DWC3 node for tertiary port of SC8280 along with
Multiport interrupts and PHYs.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 82 ++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index a5b194813079..dca8dc695f9f 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3337,6 +3337,88 @@ system-cache-controller@9200000 {
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		usb_2: usb@a4f8800 {
+			compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
+			reg = <0 0x0a4f8800 0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+				 <&gcc GCC_USB30_MP_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+				 <&gcc GCC_USB30_MP_SLEEP_CLK>,
+				 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
+				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
+
+			assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_MP_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 127 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 126 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 129 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 128 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 131 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 130 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 133 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 132 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-names = "pwr_event_1", "pwr_event_2",
+					  "pwr_event_3", "pwr_event_4",
+					  "hs_phy_1",	 "hs_phy_2",
+					  "hs_phy_3",	 "hs_phy_4",
+					  "dp_hs_phy_1", "dm_hs_phy_1",
+					  "dp_hs_phy_2", "dm_hs_phy_2",
+					  "dp_hs_phy_3", "dm_hs_phy_3",
+					  "dp_hs_phy_4", "dm_hs_phy_4",
+					  "ss_phy_1",	 "ss_phy_2";
+
+			power-domains = <&gcc USB30_MP_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_MP_BCR>;
+
+			interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			wakeup-source;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a400000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x0a400000 0 0xcd00>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x800 0x0>;
+				phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
+				       <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
+				       <&usb_2_hsphy2>,
+				       <&usb_2_hsphy3>;
+				phy-names = "usb2-0", "usb3-0",
+					    "usb2-1", "usb3-1",
+					    "usb2-2",
+					    "usb2-3";
+				dr_mode = "host";
+			};
+		};
+
 		usb_0: usb@a6f8800 {
 			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
 			reg = <0 0x0a6f8800 0 0x400>;
-- 
2.34.1

Re: [PATCH v16 1/2] arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller

[Johan Hovold]

On Mon, Apr 29, 2024 at 09:50:47PM +0530, Krishna Kurapati wrote:
> Add USB and DWC3 node for tertiary port of SC8280 along with
> Multiport interrupts and PHYs.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>

All looks good now.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>

[PATCH v16 2/2] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports

[Krishna Kurapati]

Multiport USB controller (host-only) of SA8295 ADP has 4 Type-A ports
exposed for connecting peripherals. The VBUS to these peripherals is
provided by TPS2559QWDRCTQ1 regulators connected to these ports. Each
regulator has an enable pin controlled by PMM8540. Since these regulators
are GPIO controlled regulators, model them as fixed regulators and keep
them Always-On at boot since we are wakeup capable and we don't need to
turn them off on suspend. Also since we don't enter device mode, these
regulators can be kept on.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 83 ++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 78e933c42c31..2fd1dafe63ce 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 
 #include "sa8540p.dtsi"
 #include "sa8540p-pmics.dtsi"
@@ -109,6 +110,46 @@ edp3_connector_in: endpoint {
 		};
 	};
 
+	regulator-usb2-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB2_VBUS";
+		gpio = <&pmm8540c_gpios 9 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb2_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	regulator-usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB3_VBUS";
+		gpio = <&pmm8540e_gpios 5 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb3_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	regulator-usb4-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB4_VBUS";
+		gpio = <&pmm8540g_gpios 5 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb4_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	regulator-usb5-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB5_VBUS";
+		gpio = <&pmm8540g_gpios 9 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb5_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
+
 	reserved-memory {
 		gpu_mem: gpu-mem@8bf00000 {
 			reg = <0 0x8bf00000 0 0x2000>;
@@ -637,6 +678,10 @@ &usb_1_qmpphy {
 	status = "okay";
 };
 
+&usb_2 {
+	status = "okay";
+};
+
 &usb_2_hsphy0 {
 	vdda-pll-supply = <&vreg_l5a>;
 	vdda18-supply = <&vreg_l7g>;
@@ -697,6 +742,44 @@ max20411_en: max20411-en-state {
 	};
 };
 
+&pmm8540c_gpios {
+	usb2_en: usb2-en-state {
+		pins = "gpio9";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-enable;
+		power-source = <0>;
+	};
+};
+
+&pmm8540e_gpios {
+	usb3_en: usb3-en-state {
+		pins = "gpio5";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-enable;
+		power-source = <0>;
+	};
+};
+
+&pmm8540g_gpios {
+	usb4_en: usb4-en-state {
+		pins = "gpio5";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-enable;
+		power-source = <0>;
+	};
+
+	usb5_en: usb5-en-state {
+		pins = "gpio9";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		output-enable;
+		power-source = <0>;
+	};
+};
+
 &tlmm {
 	pcie2a_default: pcie2a-default-state {
 		clkreq-n-pins {
-- 
2.34.1

Re: [PATCH v16 2/2] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports

[Johan Hovold]

On Mon, Apr 29, 2024 at 09:50:48PM +0530, Krishna Kurapati wrote:
> Multiport USB controller (host-only) of SA8295 ADP has 4 Type-A ports
> exposed for connecting peripherals. The VBUS to these peripherals is
> provided by TPS2559QWDRCTQ1 regulators connected to these ports. Each
> regulator has an enable pin controlled by PMM8540. Since these regulators
> are GPIO controlled regulators, model them as fixed regulators and keep
> them Always-On at boot since we are wakeup capable and we don't need to
> turn them off on suspend.

This does not follow from the fact that the controller is wakeup
capable. What matters is if user space has enabled wakeup from suspend
or not.

Perhaps the driver cannot handle vbus regulators currently and that's
why you do things this way, but the commit message here should at least
be updated to reflect that.

> Also since we don't enter device mode, these
> regulators can be kept on.

Not sure this is needed. You already mentioned that the controller is
host-only above.

Johan

Re: [PATCH v16 0/2] Add DT support for Multiport controller on SC8280XP

[Rob Herring]

On Mon, 29 Apr 2024 21:50:46 +0530, Krishna Kurapati wrote:
> Series [1] introduces binding and driver support for DWC3 Multiport
> controllers. This series adds support for tertiary controller of SC8280
> and enabled multiport controller for SA8295P-ADP platform.
> 
> Till v13 [2] the DT was pushed along with driver code. Separated the DT
> changes from driver update and pushing it as this series. The first two
> versions were marked as v1 and v2. Marked this as v16 to avoid missing
> of change log till v13.
> 
> Changes in v16:
> Marked it as v16 rather than v3 since till v13, there were DT changes
> sent along with driver code but were separated and this version is
> supposed to be v16.
> Fixed interrupt triggers from EDGE_RISING to EDGE_BOTH.
> 
> Link to v15:
> https://lore.kernel.org/all/20240213082724.1789096-1-quic_kriskura@quicinc.com/
> 
> Changes in v15:
> SA8540 Ride related code changes have been dropped and will pushed later
> due to unavailability of hardware with either Andrew or me for testing the
> gpio hog changes suggested in v1.
> Implemented vbus boost regulators as fixed regulators instead of modelling
> their enable pins as pinctrl nodes.
> 
> Link to v14:
> https://lore.kernel.org/all/20240206114745.1388491-1-quic_kriskura@quicinc.com/
> 
> [1]: https://lore.kernel.org/all/20240420044901.884098-1-quic_kriskura@quicinc.com/
> [2]: https://lore.kernel.org/all/20231007154806.605-1-quic_kriskura@quicinc.com/#r
> 
> Krishna Kurapati (2):
>   arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller
>   arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
>     ports
> 
>  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 83 ++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi   | 82 +++++++++++++++++++++++
>  2 files changed, 165 insertions(+)
> 
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y qcom/sa8295p-adp.dtb' for 20240429162048.2133512-1-quic_kriskura@quicinc.com:

arch/arm64/boot/dts/qcom/sa8295p-adp.dtb: usb@a4f8800: interrupt-names: ['pwr_event_1', 'pwr_event_2', 'pwr_event_3', 'pwr_event_4', 'hs_phy_1', 'hs_phy_2', 'hs_phy_3', 'hs_phy_4', 'dp_hs_phy_1', 'dm_hs_phy_1', 'dp_hs_phy_2', 'dm_hs_phy_2', 'dp_hs_phy_3', 'dm_hs_phy_3', 'dp_hs_phy_4', 'dm_hs_phy_4', 'ss_phy_1', 'ss_phy_2'] is too long
	from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
arch/arm64/boot/dts/qcom/sa8295p-adp.dtb: usb@a4f8800: interrupts-extended: [[1, 0, 130, 4], [1, 0, 135, 4], [1, 0, 857, 4], [1, 0, 856, 4], [1, 0, 131, 4], [1, 0, 136, 4], [1, 0, 860, 4], [1, 0, 859, 4], [118, 127, 3], [118, 126, 3], [118, 129, 3], [118, 128, 3], [118, 131, 3], [118, 130, 3], [118, 133, 3], [118, 132, 3], [118, 16, 4], [118, 17, 4]] is too long
	from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#

Re: (subset) [PATCH v16 0/2] Add DT support for Multiport controller on SC8280XP

[Bjorn Andersson]

On Mon, 29 Apr 2024 21:50:46 +0530, Krishna Kurapati wrote:
> Series [1] introduces binding and driver support for DWC3 Multiport
> controllers. This series adds support for tertiary controller of SC8280
> and enabled multiport controller for SA8295P-ADP platform.
> 
> Till v13 [2] the DT was pushed along with driver code. Separated the DT
> changes from driver update and pushing it as this series. The first two
> versions were marked as v1 and v2. Marked this as v16 to avoid missing
> of change log till v13.
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller
      commit: 3170a2c906c61407d725e9022b6225c5ff062d9f

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>