From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>,
Konrad Dybcio <konradybcio@kernel.org>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sibi Sankar <quic_sibis@quicinc.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags
Date: Fri, 18 Oct 2024 11:34:26 +0200 [thread overview]
Message-ID: <ZxIrosY6-bkEc6XT@hovoldconsulting.com> (raw)
In-Reply-To: <20241014-x1e80100-clk-gcc-fix-usb-mp-phy-gdsc-pwrsts-flags-v1-1-241a68c02be7@linaro.org>
On Mon, Oct 14, 2024 at 05:58:23PM +0300, Abel Vesa wrote:
> Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
> configuration on machine suspend. Currently, the QMP combo PHY driver
> doesn't reinitialise the HW on resume. Under such conditions, the USB
> SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
> RET_ON. This has been already done for USB 0 and 1 SS PHY GDSCs,
> Do this USB MP SS1 PHY GDSC config. The USB MP SS1 PHY GDSC already has
> it.
s/Do this/Do this also for the/ (or similar)
The last sentence was supposed to say "SS0".
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Looks good otherwise:
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
prev parent reply other threads:[~2024-10-18 9:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-14 14:58 [PATCH] clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags Abel Vesa
2024-10-18 9:34 ` Johan Hovold [this message]
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