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* [PATCH] clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags
@ 2024-10-14 14:58 Abel Vesa
  2024-10-18  9:34 ` Johan Hovold
  0 siblings, 1 reply; 2+ messages in thread
From: Abel Vesa @ 2024-10-14 14:58 UTC (permalink / raw)
  To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rajendra Nayak,
	Konrad Dybcio, Bryan O'Donoghue
  Cc: Johan Hovold, Dmitry Baryshkov, Sibi Sankar, linux-arm-msm,
	linux-clk, linux-kernel, Abel Vesa

Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
configuration on machine suspend. Currently, the QMP combo PHY driver
doesn't reinitialise the HW on resume. Under such conditions, the USB
SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
RET_ON. This has been already done for USB 0 and 1 SS PHY GDSCs,
Do this USB MP SS1 PHY GDSC config. The USB MP SS1 PHY GDSC already has
it.

Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/clk/qcom/gcc-x1e80100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 0f578771071fadb0ea7f610f04c5510a85a8485a..33afad9c878d30f487f63b311bcea6296d0653fd 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -6155,7 +6155,7 @@ static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
 	.pd = {
 		.name = "gcc_usb3_mp_ss1_phy_gdsc",
 	},
-	.pwrsts = PWRSTS_OFF_ON,
+	.pwrsts = PWRSTS_RET_ON,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 

---
base-commit: d61a00525464bfc5fe92c6ad713350988e492b88
change-id: 20241014-x1e80100-clk-gcc-fix-usb-mp-phy-gdsc-pwrsts-flags-3e51fba26aa4

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags
  2024-10-14 14:58 [PATCH] clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags Abel Vesa
@ 2024-10-18  9:34 ` Johan Hovold
  0 siblings, 0 replies; 2+ messages in thread
From: Johan Hovold @ 2024-10-18  9:34 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rajendra Nayak,
	Konrad Dybcio, Bryan O'Donoghue, Dmitry Baryshkov,
	Sibi Sankar, linux-arm-msm, linux-clk, linux-kernel

On Mon, Oct 14, 2024 at 05:58:23PM +0300, Abel Vesa wrote:
> Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
> configuration on machine suspend. Currently, the QMP combo PHY driver
> doesn't reinitialise the HW on resume. Under such conditions, the USB
> SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
> RET_ON. This has been already done for USB 0 and 1 SS PHY GDSCs,
> Do this USB MP SS1 PHY GDSC config. The USB MP SS1 PHY GDSC already has
> it.

s/Do this/Do this also for the/ (or similar)

The last sentence was supposed to say "SS0".

> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

Looks good otherwise:

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2024-10-18  9:34 UTC | newest]

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2024-10-14 14:58 [PATCH] clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags Abel Vesa
2024-10-18  9:34 ` Johan Hovold

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