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From: Johan Hovold <johan@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
	kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
	konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org,
	quic_msarkar@quicinc.com, quic_devipriy@quicinc.com,
	dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org,
	neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, johan+linaro@kernel.org,
	stable@vger.kernel.org
Subject: Re: [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for X1E80100 SoC
Date: Fri, 18 Oct 2024 16:06:09 +0200	[thread overview]
Message-ID: <ZxJrUQDGMDw3wI3Q@hovoldconsulting.com> (raw)
In-Reply-To: <20241017030412.265000-7-quic_qianyu@quicinc.com>

Please use a more concise subject (e.g. try to stay within 72 chars)
than:

	PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for X1E80100 SoC

Here you could drop "SoC", maybe "ASPM" and "config" for example.

On Wed, Oct 16, 2024 at 08:04:11PM -0700, Qiang Yu wrote:
> Currently, the cfg_1_9_0 which is being used for X1E80100 has config_sid
> callback in its ops and doesn't disable ASPM L0s. However, as same as
> SC8280X, PCIe controllers on X1E80100 are connected to SMMUv3, hence don't
> need config_sid() callback and hardware team has recommended to disable
> L0s as it is broken in the controller. Hence reuse cfg_sc8280xp for
> X1E80100.

Since the x1e80100 dtsi, like sc8280xp, do not specify an iommu-map,
that bit is effectively just a cleanup and all this patch does is to
disable L0s.

Please rephrase to make this clear. This will also allow you to make the
Subject even shorter (no need to mention the SID bit in Subject).

Also say something about how L0s is broken so that it is more clear what
the effect of this patch is. On sc8280xp enabling L0s lead to
correctable errors for example.

> Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support")
> Cc: stable@vger.kernel.org

Johan

  reply	other threads:[~2024-10-18 14:06 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-17  3:04 [PATCH v7 0/7] Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-17  3:04 ` [PATCH v7 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-10-17  3:04 ` [PATCH v7 2/7] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Qiang Yu
2024-10-17  3:04 ` [PATCH v7 3/7] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt Qiang Yu
2024-10-17  7:58   ` Krzysztof Kozlowski
2024-10-17  3:04 ` [PATCH v7 4/7] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-10-17  3:04 ` [PATCH v7 5/7] PCI: qcom: Remove BDF2SID mapping config for SC8280X family SoC Qiang Yu
2024-10-18 13:51   ` Johan Hovold
2024-10-24  6:39     ` Qiang Yu
2024-10-17  3:04 ` [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for X1E80100 SoC Qiang Yu
2024-10-18 14:06   ` Johan Hovold [this message]
2024-10-24  6:42     ` Qiang Yu
2024-10-30  5:54       ` Qiang Yu
2024-10-30  7:15         ` Johan Hovold
2024-10-30  7:18           ` Manivannan Sadhasivam
2024-10-30  7:42             ` Johan Hovold
2024-10-30  7:56               ` Qiang Yu
2024-10-18 14:25   ` Bjorn Andersson
2024-10-24  6:46     ` Qiang Yu
2024-10-17  3:04 ` [PATCH v7 7/7] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-18 14:08   ` Johan Hovold
2024-10-17 15:35 ` (subset) [PATCH v7 0/7] " Vinod Koul

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