From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: webgeek1234@gmail.com, Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Georgi Djakov <djakov@kernel.org>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes
Date: Thu, 19 Feb 2026 10:29:33 +0100 [thread overview]
Message-ID: <aa5f536a-41f2-47e7-b80c-8559c13a69b3@oss.qualcomm.com> (raw)
In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-2-43a2b6d47e70@gmail.com>
On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Add the OSC L3 Cache controller node.
>
> Also add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
This should still be squashed with patch 3, as while you wire up the
CPUs as interconnect consumers, they cast no vote, leading to the
situation Krzysztof mentioned where the performance actually majorly
goes *down*, since the icc core sees no users present and assumes it can
send a zero-vote (which probably translates to F_MIN for the cache)
Konrad
next prev parent reply other threads:[~2026-02-19 9:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-18 18:16 [PATCH v2 0/3] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
2026-02-18 18:16 ` [PATCH v2 1/3] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Aaron Kling via B4 Relay
2026-02-19 7:52 ` Krzysztof Kozlowski
2026-02-20 2:59 ` Aaron Kling
2026-02-18 18:16 ` [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes Aaron Kling via B4 Relay
2026-02-19 9:29 ` Konrad Dybcio [this message]
2026-02-19 9:53 ` Imran Shaik
2026-02-18 18:16 ` [PATCH v2 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-02-19 9:57 ` Konrad Dybcio
2026-02-19 9:58 ` Konrad Dybcio
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