From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: webgeek1234@gmail.com, Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Georgi Djakov <djakov@kernel.org>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH v2 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
Date: Thu, 19 Feb 2026 10:58:48 +0100 [thread overview]
Message-ID: <1c43591f-ffc3-433e-94b2-8cc7bdb3ec62@oss.qualcomm.com> (raw)
In-Reply-To: <f8c2fe29-9e38-487c-b32e-7ce151403a7a@oss.qualcomm.com>
On 2/19/26 10:57 AM, Konrad Dybcio wrote:
> On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote:
>> From: Aaron Kling <webgeek1234@gmail.com>
>>
>> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
>> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
>> frequency by aggregating bandwidth requests of all CPU core with referenc
>> to the current OPP they are configured in by the LMH/EPSS hardware.
>>
>> The effect is a proper caches & DDR frequency scaling when CPU cores
>> changes frequency.
>>
>> The OPP tables were built using the downstream memlat ddr, llcc & l3
>> tables for each cluster types with the actual EPSS cpufreq LUT tables
>> from running a QCS8550 device.
>>
>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
>> ---
>
> Once squashed:
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
FYI I did notice a couple of "trip points" in the downstream DT that
refer to higher than described (i.e. >3 GHz) OPPs, but I can't find data
about them internally. Anyway, this is good and if someone has a "very
fast 8550", we can always extend that
Konrad
prev parent reply other threads:[~2026-02-19 9:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-18 18:16 [PATCH v2 0/3] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
2026-02-18 18:16 ` [PATCH v2 1/3] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Aaron Kling via B4 Relay
2026-02-19 7:52 ` Krzysztof Kozlowski
2026-02-20 2:59 ` Aaron Kling
2026-02-18 18:16 ` [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes Aaron Kling via B4 Relay
2026-02-19 9:29 ` Konrad Dybcio
2026-02-19 9:53 ` Imran Shaik
2026-02-18 18:16 ` [PATCH v2 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-02-19 9:57 ` Konrad Dybcio
2026-02-19 9:58 ` Konrad Dybcio [this message]
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