[PATCH] PCI: qcom: Disable ASPM L0s for SA8775P

[PATCH] PCI: qcom: Disable ASPM L0s for SA8775P

[Shawn Guo]

Commit f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port
if iMSI-RX is used as MSI controller") removed MSI/MSI-X capabilities
from the Root Port on platforms using iMSI-RX (including SA8775P, which
has no msi-parent/msi-map in DT).  This causes PME and AER service
drivers to fall back from MSI to INTx.

With INTx-based PME active, the QCN9100 modem endpoint sends PME messages
during D-state transitions early in boot.  The level-triggered INTx
assertion coincides with ASPM L0s exit sequencing on SA8775P hardware,
causing Data Link Layer Replay Timer Timeout errors on both sides of the
link.

[   13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332
[   13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332
[   13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0
[   13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
[   13.111281] pci 0000:01:00.0:   device [17cb:1103] error status/mask=00001000/0000e000
[   13.111284] pci 0000:01:00.0:    [12] Timeout
[   13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0
[   13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
[   13.130514] pcieport 0000:00:00.0:   device [17cb:0115] error status/mask=00001000/0000e000
[   13.130516] pcieport 0000:00:00.0:    [12] Timeout

Fix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true
to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from
the Root Port and ASPM L0s is prevented from being negotiated.

Fixes: f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller")
Assisted-by: Claude:claude-4-6-sonnet
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index af6bf5cce65b..6a14b5091338 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1473,6 +1473,7 @@ static const struct qcom_pcie_cfg cfg_1_9_0 = {
 static const struct qcom_pcie_cfg cfg_1_34_0 = {
 	.ops = &ops_1_9_0,
 	.override_no_snoop = true,
+	.no_l0s = true,
 };
 
 static const struct qcom_pcie_cfg cfg_2_1_0 = {
-- 
2.43.0

Re: [PATCH] PCI: qcom: Disable ASPM L0s for SA8775P

[Manivannan Sadhasivam]

On Sun, Apr 19, 2026 at 05:39:34PM +0800, Shawn Guo wrote:
> Commit f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port
> if iMSI-RX is used as MSI controller") removed MSI/MSI-X capabilities
> from the Root Port on platforms using iMSI-RX (including SA8775P, which
> has no msi-parent/msi-map in DT).  This causes PME and AER service
> drivers to fall back from MSI to INTx.
> 
> With INTx-based PME active, the QCN9100 modem endpoint sends PME messages
> during D-state transitions early in boot.  The level-triggered INTx
> assertion coincides with ASPM L0s exit sequencing on SA8775P hardware,
> causing Data Link Layer Replay Timer Timeout errors on both sides of the
> link.
> 

How did you conclude that INTx collides with ASPM L0s exit sequence? Also,
AFAIK, L0s is supported and work well on this chipset.

What we are dealing with could be the board specific issue.

> [   13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332
> [   13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332
> [   13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0
> [   13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
> [   13.111281] pci 0000:01:00.0:   device [17cb:1103] error status/mask=00001000/0000e000
> [   13.111284] pci 0000:01:00.0:    [12] Timeout
> [   13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0
> [   13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
> [   13.130514] pcieport 0000:00:00.0:   device [17cb:0115] error status/mask=00001000/0000e000
> [   13.130516] pcieport 0000:00:00.0:    [12] Timeout
> 
> Fix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true
> to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from
> the Root Port and ASPM L0s is prevented from being negotiated.
> 

No. This is not the correct fix. If we identify if this is a board issue, we
need to disable L0s selectively using 'pcie,no-aspm-l0s' DT property defined in
the Root Port DT node.

> Fixes: f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller")
> Assisted-by: Claude:claude-4-6-sonnet

Ok, this seems to be an AI slop. INTx is triggered through in-band messages and
the link should be in L0 so that an endpoint can transmit these. So there is no
way it could collide with L0s exit sequence as the link being in L0 is the
pre-requisite for triggering INTx.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH] PCI: qcom: Disable ASPM L0s for SA8775P

[Shawn Guo]

On Mon, Apr 20, 2026 at 12:08:25PM +0530, Manivannan Sadhasivam wrote:
> On Sun, Apr 19, 2026 at 05:39:34PM +0800, Shawn Guo wrote:
> > Commit f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port
> > if iMSI-RX is used as MSI controller") removed MSI/MSI-X capabilities
> > from the Root Port on platforms using iMSI-RX (including SA8775P, which
> > has no msi-parent/msi-map in DT).  This causes PME and AER service
> > drivers to fall back from MSI to INTx.
> > 
> > With INTx-based PME active, the QCN9100 modem endpoint sends PME messages
> > during D-state transitions early in boot.  The level-triggered INTx
> > assertion coincides with ASPM L0s exit sequencing on SA8775P hardware,
> > causing Data Link Layer Replay Timer Timeout errors on both sides of the
> > link.
> > 
> 
> How did you conclude that INTx collides with ASPM L0s exit sequence? Also,
> AFAIK, L0s is supported and work well on this chipset.
> 
> What we are dealing with could be the board specific issue.

I just got looped into an internal discussion.  The issue seems to
be refgen voting related, so likely affects all Lemans (and Monaco)
boards with PCIe enabled.

Before a proper fix is available, 'pcie_aspm=off' on kernel cmdline is
suggested as a temporary workaround.

> > [   13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332
> > [   13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332
> > [   13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0
> > [   13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
> > [   13.111281] pci 0000:01:00.0:   device [17cb:1103] error status/mask=00001000/0000e000
> > [   13.111284] pci 0000:01:00.0:    [12] Timeout
> > [   13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0
> > [   13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
> > [   13.130514] pcieport 0000:00:00.0:   device [17cb:0115] error status/mask=00001000/0000e000
> > [   13.130516] pcieport 0000:00:00.0:    [12] Timeout
> > 
> > Fix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true
> > to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from
> > the Root Port and ASPM L0s is prevented from being negotiated.
> > 
> 
> No. This is not the correct fix. If we identify if this is a board issue, we
> need to disable L0s selectively using 'pcie,no-aspm-l0s' DT property defined in
> the Root Port DT node.
> 
> > Fixes: f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller")
> > Assisted-by: Claude:claude-4-6-sonnet
> 
> Ok, this seems to be an AI slop. INTx is triggered through in-band messages and
> the link should be in L0 so that an endpoint can transmit these. So there is no
> way it could collide with L0s exit sequence as the link being in L0 is the
> pre-requisite for triggering INTx.

Thank you for the insight!  Indeed, I was asking help from AI as I do not
have too much expertise on PCIe ;)

Shawn