Re: [PATCH 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Mon, Apr 20, 2026 at 10:22:59AM +0200, Konrad Dybcio wrote:
> On 4/20/26 5:49 AM, Shawn Guo wrote:
> > From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> > 
> > The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on
> > x1e80100. The existing driver hardcodes the channel count via a
> > compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it
> > impossible to support hardware with a different number of channels.
> > 
> > Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that
> > carries the channel count, and retrieve it via of_device_get_match_data()
> > at probe time. Switch the channel array from a fixed-size member to a
> > dynamically allocated buffer sized from the hardware data. Update the
> > x1e80100 entry to supply its own data struct, and add a new Nord entry
> > with num_chans = 16.
> > 
> > Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> 
> [...]
> 
> >  /**
> >   * struct qcom_cpucp_mbox - Holder for the mailbox driver
> > - * @chans:			The mailbox channel
> > + * @chans:			The mailbox channels (dynamically allocated)
> 
> I don't think this line is a valuable change

Indeed!  I will drop the change.  Thanks!

Shawn