From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>,
Jassi Brar <jassisinghbrar@gmail.com>
Cc: Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>,
Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC
Date: Mon, 20 Apr 2026 10:23:20 +0200 [thread overview]
Message-ID: <0c2425dd-0ba4-49ac-853b-b157eec1fdfd@oss.qualcomm.com> (raw)
In-Reply-To: <20260420034932.1247344-1-shengchao.guo@oss.qualcomm.com>
On 4/20/26 5:49 AM, Shawn Guo wrote:
> This series adds CPUCP mailbox controller support for Qualcomm Nord SoC.
>
> The Nord CPUCP mailbox is functionally identical to the existing x1e80100
> implementation, except it exposes 16 IPC channels instead of 3. Patch 1
> adds the Nord compatible string to the DT binding. Patch 2 refactors
> the channel count from a hardcoded compile-time constant into
> a per-hardware configuration struct populated via the device tree
> match data.
What are these channels used for?
Konrad
next prev parent reply other threads:[~2026-04-20 8:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 3:49 [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC Shawn Guo
2026-04-20 3:49 ` [PATCH 1/2] dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller Shawn Guo
2026-04-21 10:30 ` Krzysztof Kozlowski
2026-04-20 3:49 ` [PATCH 2/2] mailbox: qcom-cpucp: Add support for " Shawn Guo
2026-04-20 8:22 ` Konrad Dybcio
2026-04-21 7:39 ` Shawn Guo
2026-04-20 8:23 ` Konrad Dybcio [this message]
2026-04-21 7:38 ` [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC Shawn Guo
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