[PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC

[PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC

[Shawn Guo]

This series adds CPUCP mailbox controller support for Qualcomm Nord SoC.

The Nord CPUCP mailbox is functionally identical to the existing x1e80100
implementation, except it exposes 16 IPC channels instead of 3.  Patch 1
adds the Nord compatible string to the DT binding.  Patch 2 refactors
the channel count from a hardcoded compile-time constant into
a per-hardware configuration struct populated via the device tree
match data.

Deepti Jaggi (2):
  dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller
  mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller

 .../bindings/mailbox/qcom,cpucp-mbox.yaml     |  1 +
 drivers/mailbox/qcom-cpucp-mbox.c             | 37 ++++++++++++++++---
 2 files changed, 32 insertions(+), 6 deletions(-)

-- 
2.43.0

[PATCH 1/2] dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller

[Shawn Guo]

From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>

Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Nord SoC.  It has 16 IPC channels, compared to 3 on X1E80100 CPUCP.

Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
index 90bfde66cc4a..2dd66a88c186 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
@@ -23,6 +23,7 @@ properties:
               - qcom,sm8750-cpucp-mbox
           - const: qcom,x1e80100-cpucp-mbox
       - enum:
+          - qcom,nord-cpucp-mbox
           - qcom,x1e80100-cpucp-mbox
 
   reg:
-- 
2.43.0

Re: [PATCH 1/2] dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller

[Krzysztof Kozlowski]

On Mon, Apr 20, 2026 at 11:49:31AM +0800, Shawn Guo wrote:
> From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> 
> Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
> Nord SoC.  It has 16 IPC channels, compared to 3 on X1E80100 CPUCP.

And more channels does not make it incompatible (see writing bindings or
DTS101 slides). Please provide explanation why devices are not
compatible.

Best regards,
Krzysztof

[PATCH 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller

[Shawn Guo]

From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>

The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on
x1e80100. The existing driver hardcodes the channel count via a
compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it
impossible to support hardware with a different number of channels.

Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that
carries the channel count, and retrieve it via of_device_get_match_data()
at probe time. Switch the channel array from a fixed-size member to a
dynamically allocated buffer sized from the hardware data. Update the
x1e80100 entry to supply its own data struct, and add a new Nord entry
with num_chans = 16.

Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 drivers/mailbox/qcom-cpucp-mbox.c | 37 ++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c
index 44f4ed15f818..624a4e9eb6c6 100644
--- a/drivers/mailbox/qcom-cpucp-mbox.c
+++ b/drivers/mailbox/qcom-cpucp-mbox.c
@@ -12,7 +12,6 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#define APSS_CPUCP_IPC_CHAN_SUPPORTED		3
 #define APSS_CPUCP_MBOX_CMD_OFF			0x4
 
 /* Tx Registers */
@@ -26,15 +25,23 @@
 #define APSS_CPUCP_RX_MBOX_EN			0x4c00
 #define APSS_CPUCP_RX_MBOX_CMD_MASK		GENMASK_ULL(63, 0)
 
+/**
+ * struct qcom_cpucp_mbox_data - Per-hardware mailbox configuration data
+ * @num_chans:			Number of IPC channels supported by this hardware
+ */
+struct qcom_cpucp_mbox_data {
+	int num_chans;
+};
+
 /**
  * struct qcom_cpucp_mbox - Holder for the mailbox driver
- * @chans:			The mailbox channel
+ * @chans:			The mailbox channels (dynamically allocated)
  * @mbox:			The mailbox controller
  * @tx_base:			Base address of the CPUCP tx registers
  * @rx_base:			Base address of the CPUCP rx registers
  */
 struct qcom_cpucp_mbox {
-	struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED];
+	struct mbox_chan *chans;
 	struct mbox_controller mbox;
 	void __iomem *tx_base;
 	void __iomem *rx_base;
@@ -53,7 +60,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data)
 
 	status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
 
-	for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORTED) {
+	for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) {
 		u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF);
 		struct mbox_chan *chan = &cpucp->chans[i];
 		unsigned long flags;
@@ -112,15 +119,24 @@ static const struct mbox_chan_ops qcom_cpucp_mbox_chan_ops = {
 
 static int qcom_cpucp_mbox_probe(struct platform_device *pdev)
 {
+	const struct qcom_cpucp_mbox_data *data;
 	struct device *dev = &pdev->dev;
 	struct qcom_cpucp_mbox *cpucp;
 	struct mbox_controller *mbox;
 	int irq, ret;
 
+	data = of_device_get_match_data(dev);
+	if (!data)
+		return dev_err_probe(dev, -EINVAL, "No match data found\n");
+
 	cpucp = devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL);
 	if (!cpucp)
 		return -ENOMEM;
 
+	cpucp->chans = devm_kcalloc(dev, data->num_chans, sizeof(*cpucp->chans), GFP_KERNEL);
+	if (!cpucp->chans)
+		return -ENOMEM;
+
 	cpucp->rx_base = devm_of_iomap(dev, dev->of_node, 0, NULL);
 	if (IS_ERR(cpucp->rx_base))
 		return PTR_ERR(cpucp->rx_base);
@@ -146,7 +162,7 @@ static int qcom_cpucp_mbox_probe(struct platform_device *pdev)
 
 	mbox = &cpucp->mbox;
 	mbox->dev = dev;
-	mbox->num_chans = APSS_CPUCP_IPC_CHAN_SUPPORTED;
+	mbox->num_chans = data->num_chans;
 	mbox->chans = cpucp->chans;
 	mbox->ops = &qcom_cpucp_mbox_chan_ops;
 
@@ -157,8 +173,17 @@ static int qcom_cpucp_mbox_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct qcom_cpucp_mbox_data qcom_x1e80100_mbox_data = {
+	.num_chans = 3,
+};
+
+static const struct qcom_cpucp_mbox_data qcom_nord_mbox_data = {
+	.num_chans = 16,
+};
+
 static const struct of_device_id qcom_cpucp_mbox_of_match[] = {
-	{ .compatible = "qcom,x1e80100-cpucp-mbox" },
+	{ .compatible = "qcom,nord-cpucp-mbox", .data = &qcom_nord_mbox_data },
+	{ .compatible = "qcom,x1e80100-cpucp-mbox", .data = &qcom_x1e80100_mbox_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_cpucp_mbox_of_match);
-- 
2.43.0

Re: [PATCH 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller

[Konrad Dybcio]

On 4/20/26 5:49 AM, Shawn Guo wrote:
> From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> 
> The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on
> x1e80100. The existing driver hardcodes the channel count via a
> compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it
> impossible to support hardware with a different number of channels.
> 
> Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that
> carries the channel count, and retrieve it via of_device_get_match_data()
> at probe time. Switch the channel array from a fixed-size member to a
> dynamically allocated buffer sized from the hardware data. Update the
> x1e80100 entry to supply its own data struct, and add a new Nord entry
> with num_chans = 16.
> 
> Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---

[...]

>  /**
>   * struct qcom_cpucp_mbox - Holder for the mailbox driver
> - * @chans:			The mailbox channel
> + * @chans:			The mailbox channels (dynamically allocated)

I don't think this line is a valuable change

The rest of the patch looks good

Konrad

Re: [PATCH 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller

[Shawn Guo]

On Mon, Apr 20, 2026 at 10:22:59AM +0200, Konrad Dybcio wrote:
> On 4/20/26 5:49 AM, Shawn Guo wrote:
> > From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> > 
> > The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on
> > x1e80100. The existing driver hardcodes the channel count via a
> > compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it
> > impossible to support hardware with a different number of channels.
> > 
> > Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that
> > carries the channel count, and retrieve it via of_device_get_match_data()
> > at probe time. Switch the channel array from a fixed-size member to a
> > dynamically allocated buffer sized from the hardware data. Update the
> > x1e80100 entry to supply its own data struct, and add a new Nord entry
> > with num_chans = 16.
> > 
> > Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> 
> [...]
> 
> >  /**
> >   * struct qcom_cpucp_mbox - Holder for the mailbox driver
> > - * @chans:			The mailbox channel
> > + * @chans:			The mailbox channels (dynamically allocated)
> 
> I don't think this line is a valuable change

Indeed!  I will drop the change.  Thanks!

Shawn

Re: [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC

[Konrad Dybcio]

On 4/20/26 5:49 AM, Shawn Guo wrote:
> This series adds CPUCP mailbox controller support for Qualcomm Nord SoC.
> 
> The Nord CPUCP mailbox is functionally identical to the existing x1e80100
> implementation, except it exposes 16 IPC channels instead of 3.  Patch 1
> adds the Nord compatible string to the DT binding.  Patch 2 refactors
> the channel count from a hardcoded compile-time constant into
> a per-hardware configuration struct populated via the device tree
> match data.

What are these channels used for?

Konrad

Re: [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC

[Shawn Guo]

On Mon, Apr 20, 2026 at 10:23:20AM +0200, Konrad Dybcio wrote:
> On 4/20/26 5:49 AM, Shawn Guo wrote:
> > This series adds CPUCP mailbox controller support for Qualcomm Nord SoC.
> > 
> > The Nord CPUCP mailbox is functionally identical to the existing x1e80100
> > implementation, except it exposes 16 IPC channels instead of 3.  Patch 1
> > adds the Nord compatible string to the DT binding.  Patch 2 refactors
> > the channel count from a hardcoded compile-time constant into
> > a per-hardware configuration struct populated via the device tree
> > match data.
> 
> What are these channels used for?

Per my search on internal documents, it says that more channels are added
to support following communications:

 - Between Hypervisor software and CPUCP firmware
 - Between TZ software and CPUCP firmware
 - IPC between CPUCPs (Nord chiplet design)

Deepti,

Correct me or add anything as needed.

Shawn