* [DPU PATCH 1/5] drm/msm/dpu: remove smart dma support
[not found] ` <1529499020-8499-1-git-send-email-skolluku-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
@ 2018-06-20 12:50 ` Sravanthi Kollukuduru
2018-06-20 12:50 ` [DPU PATCH 3/5] drm/msm/dpu: remove static binding of hw pipe to plane Sravanthi Kollukuduru
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Sravanthi Kollukuduru @ 2018-06-20 12:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: robdclark-Re5JQEeQqe8AvxtiuMwx3w, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, Sravanthi Kollukuduru
Removing the smart dma feature implementation as it is
currently not enabled on dpu driver.
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 51 +----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 19 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 76 ++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 159 +++------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 56 +-----
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 26 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 265 ++-----------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 38 +---
drivers/gpu/drm/msm/msm_drv.h | 2 +-
11 files changed, 84 insertions(+), 637 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 6c78c11c3..f0aafec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -230,12 +230,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
stage_idx = zpos_cnt[pstate->stage]++;
stage_cfg->stage[pstate->stage][stage_idx] =
dpu_plane_pipe(plane);
- stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->multirect_index;
DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- pstate->multirect_index, pstate->multirect_mode,
format->base.pixel_format, fb ? fb->modifier : 0);
/* blend config update */
@@ -1334,14 +1331,13 @@ struct plane_state {
struct dpu_plane_state *dpu_pstate;
const struct drm_plane_state *drm_pstate;
int stage;
- u32 pipe_id;
};
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct dpu_crtc *dpu_crtc;
- struct plane_state pstates[DPU_STAGE_MAX * 4];
+ struct plane_state pstates[DPU_STAGE_MAX * 2];
struct dpu_crtc_state *cstate;
const struct drm_plane_state *pstate;
@@ -1351,10 +1347,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct dpu_private_state *dpu_priv_state;
int cnt = 0, rc = 0, mixer_width, i, z_pos;
-
- struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
- int multirect_count = 0;
- const struct drm_plane_state *pipe_staged[SSPP_MAX];
int left_zpos_cnt = 0, right_zpos_cnt = 0;
if (!crtc) {
@@ -1378,8 +1370,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (state->active_changed)
state->mode_changed = true;
- memset(pipe_staged, 0, sizeof(pipe_staged));
-
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
_dpu_crtc_setup_lm_bounds(crtc, state);
@@ -1398,18 +1388,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = dpu_plane_pipe(plane);
-
- if (pipe_staged[pstates[cnt].pipe_id]) {
- multirect_plane[multirect_count].r0 =
- pipe_staged[pstates[cnt].pipe_id];
- multirect_plane[multirect_count].r1 = pstate;
- multirect_count++;
-
- pipe_staged[pstates[cnt].pipe_id] = NULL;
- } else {
- pipe_staged[pstates[cnt].pipe_id] = pstate;
- }
cnt++;
@@ -1426,20 +1404,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
}
- for (i = 1; i < SSPP_MAX; i++) {
- if (pipe_staged[i]) {
- dpu_plane_clear_multirect(pipe_staged[i]);
-
- if (is_dpu_plane_virtual(pipe_staged[i]->plane)) {
- DPU_ERROR(
- "r1 only virt plane:%d not supported\n",
- pipe_staged[i]->plane->base.id);
- rc = -EINVAL;
- goto end;
- }
- }
- }
-
z_pos = -1;
for (i = 0; i < cnt; i++) {
/* reset counts at every new blend stage */
@@ -1478,17 +1442,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos);
}
- for (i = 0; i < multirect_count; i++) {
- if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) {
- DPU_ERROR(
- "multirect validation failed for planes (%d - %d)\n",
- multirect_plane[i].r0->plane->base.id,
- multirect_plane[i].r1->plane->base.id);
- rc = -EINVAL;
- goto end;
- }
- }
-
rc = dpu_core_perf_crtc_check(crtc, state);
if (rc) {
DPU_ERROR("crtc%d failed performance check %d\n",
@@ -1708,8 +1661,6 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h);
- seq_printf(s, "\tmultirect: mode: %d index: %d\n",
- pstate->multirect_mode, pstate->multirect_index);
seq_puts(s, "\n");
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index ab46bf6..f0c2881 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -58,7 +58,6 @@
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.qseed_type = DPU_SSPP_SCALER_QSEED3,
- .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_src_split = true,
.has_dim_layer = true,
@@ -134,12 +133,11 @@
.maxvdeciexp = MAX_VERT_DECIMATION,
};
-#define _VIG_SBLK(num, sdma_pri) \
+#define _VIG_SBLK(num) \
{ \
.common = &sdm845_sspp_common, \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
- .smart_dma_priority = sdma_pri, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
@@ -149,30 +147,27 @@
.id = DPU_SSPP_CSC_10BIT, \
.base = 0x1a00, .len = 0x100,}, \
.format_list = plane_formats_yuv, \
- .virt_format_list = plane_formats, \
}
-#define _DMA_SBLK(num, sdma_pri) \
+#define _DMA_SBLK(num) \
{ \
.common = &sdm845_sspp_common, \
.maxdwnscale = SSPP_UNITY_SCALE, \
.maxupscale = SSPP_UNITY_SCALE, \
- .smart_dma_priority = sdma_pri, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
.format_list = plane_formats, \
- .virt_format_list = plane_formats, \
}
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5);
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1", 6);
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2", 7);
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8);
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0");
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1");
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2");
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3");
-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
+static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8");
+static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9");
+static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10");
+static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11");
#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
{ \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f0cb0d4..1b04448 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -108,8 +108,6 @@ enum {
* @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
* @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
* @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
- * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
- * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
* @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper
* @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
* @DPU_SSPP_CDP Supports client driven prefetch
@@ -126,8 +124,6 @@ enum {
DPU_SSPP_QOS,
DPU_SSPP_QOS_8LVL,
DPU_SSPP_EXCL_RECT,
- DPU_SSPP_SMART_DMA_V1,
- DPU_SSPP_SMART_DMA_V2,
DPU_SSPP_TS_PREFILL,
DPU_SSPP_TS_PREFILL_REC1,
DPU_SSPP_CDP,
@@ -298,7 +294,6 @@ struct dpu_qos_lut_tbl {
* @max_mixer_blendstages max layer mixer blend stages or
* supported z order
* @qseed_type qseed2 or qseed3 support.
- * @smart_dma_rev Supported version of SmartDMA feature.
* @ubwc_version UBWC feature version (0x0 for not supported)
* @has_src_split source split feature status
* @has_dim_layer dim layer feature status
@@ -308,7 +303,6 @@ struct dpu_caps {
u32 max_mixer_width;
u32 max_mixer_blendstages;
u32 qseed_type;
- u32 smart_dma_rev;
u32 ubwc_version;
bool has_src_split;
bool has_dim_layer;
@@ -338,7 +332,6 @@ struct dpu_sspp_blks_common {
* @danger_vblank: danger priority during vertical blanking
* @maxdwnscale: max downscale ratio supported(without DECIMATION)
* @maxupscale: maxupscale ratio supported
- * @smart_dma_priority: hw priority of rect1 of multirect pipe
* @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
* @src_blk:
* @scaler_blk:
@@ -348,7 +341,6 @@ struct dpu_sspp_blks_common {
* @pcc_blk:
* @igc_blk:
* @format_list: Pointer to list of supported formats
- * @virt_format_list: Pointer to list of supported formats for virtual planes
*/
struct dpu_sspp_sub_blks {
const struct dpu_sspp_blks_common *common;
@@ -356,7 +348,6 @@ struct dpu_sspp_sub_blks {
u32 danger_vblank;
u32 maxdwnscale;
u32 maxupscale;
- u32 smart_dma_priority;
u32 max_per_pipe_bw;
struct dpu_src_blk src_blk;
struct dpu_scaler_blk scaler_blk;
@@ -367,7 +358,6 @@ struct dpu_sspp_sub_blks {
struct dpu_pp_blk igc_blk;
const struct dpu_format_extended *format_list;
- const struct dpu_format_extended *virt_format_list;
};
/**
@@ -792,13 +782,4 @@ struct dpu_mdss_hw_cfg_handler {
*/
void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
-/**
- * dpu_hw_sspp_multirect_enabled - check multirect enabled for the sspp
- * @cfg: pointer to sspp cfg
- */
-static inline bool dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg *cfg)
-{
- return test_bit(DPU_SSPP_SMART_DMA_V1, &cfg->features) ||
- test_bit(DPU_SSPP_SMART_DMA_V2, &cfg->features);
-}
#endif /* _DPU_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index ad02316..1b9f41f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -22,8 +22,7 @@
(0x40 + (((lm) - LM_0) * 0x004))
#define CTL_LAYER_EXT2(lm) \
(0x70 + (((lm) - LM_0) * 0x004))
-#define CTL_LAYER_EXT3(lm) \
- (0xA0 + (((lm) - LM_0) * 0x004))
+
#define CTL_TOP 0x014
#define CTL_FLUSH 0x018
#define CTL_START 0x01C
@@ -299,7 +298,6 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx)
DPU_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0);
DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0);
DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0);
- DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0);
}
}
@@ -307,8 +305,8 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
- u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
- u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
+ u32 mixercfg = 0, mixercfg_ext = 0, mixercfg_ext2 = 0;
+ u32 mix, ext;
int i, j;
u8 stages;
int pipes_per_stage;
@@ -334,41 +332,22 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
ext = i >= 7;
for (j = 0 ; j < pipes_per_stage; j++) {
- enum dpu_sspp_multirect_index rect_index =
- stage_cfg->multirect_index[i][j];
-
switch (stage_cfg->stage[i][j]) {
case SSPP_VIG0:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext3 |= ((i + 1) & 0xF) << 0;
- } else {
- mixercfg |= mix << 0;
- mixercfg_ext |= ext << 0;
- }
+ mixercfg |= mix << 0;
+ mixercfg_ext |= ext << 0;
break;
case SSPP_VIG1:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext3 |= ((i + 1) & 0xF) << 4;
- } else {
- mixercfg |= mix << 3;
- mixercfg_ext |= ext << 2;
- }
+ mixercfg |= mix << 3;
+ mixercfg_ext |= ext << 2;
break;
case SSPP_VIG2:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext3 |= ((i + 1) & 0xF) << 8;
- } else {
- mixercfg |= mix << 6;
- mixercfg_ext |= ext << 4;
- }
+ mixercfg |= mix << 6;
+ mixercfg_ext |= ext << 4;
break;
case SSPP_VIG3:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext3 |= ((i + 1) & 0xF) << 12;
- } else {
- mixercfg |= mix << 26;
- mixercfg_ext |= ext << 6;
- }
+ mixercfg |= mix << 26;
+ mixercfg_ext |= ext << 6;
break;
case SSPP_RGB0:
mixercfg |= mix << 9;
@@ -387,36 +366,20 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
mixercfg_ext |= ext << 14;
break;
case SSPP_DMA0:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext2 |= ((i + 1) & 0xF) << 8;
- } else {
- mixercfg |= mix << 18;
- mixercfg_ext |= ext << 16;
- }
+ mixercfg |= mix << 18;
+ mixercfg_ext |= ext << 16;
break;
case SSPP_DMA1:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext2 |= ((i + 1) & 0xF) << 12;
- } else {
- mixercfg |= mix << 21;
- mixercfg_ext |= ext << 18;
- }
+ mixercfg |= mix << 21;
+ mixercfg_ext |= ext << 18;
break;
case SSPP_DMA2:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext2 |= ((i + 1) & 0xF) << 16;
- } else {
- mix |= (i + 1) & 0xF;
- mixercfg_ext2 |= mix << 0;
- }
+ mix |= (i + 1) & 0xF;
+ mixercfg_ext2 |= mix << 0;
break;
case SSPP_DMA3:
- if (rect_index == DPU_SSPP_RECT_1) {
- mixercfg_ext2 |= ((i + 1) & 0xF) << 20;
- } else {
- mix |= (i + 1) & 0xF;
- mixercfg_ext2 |= mix << 4;
- }
+ mix |= (i + 1) & 0xF;
+ mixercfg_ext2 |= mix << 4;
break;
case SSPP_CURSOR0:
mixercfg_ext |= ((i + 1) & 0xF) << 20;
@@ -434,7 +397,6 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
- DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index c66a71f..729fc10 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -16,7 +16,6 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_util.h"
#include "dpu_hw_catalog.h"
-#include "dpu_hw_sspp.h"
#include "dpu_hw_blk.h"
/**
@@ -33,12 +32,9 @@ enum dpu_ctl_mode_sel {
/**
* struct dpu_hw_stage_cfg - blending stage cfg
* @stage : SSPP_ID at each stage
- * @multirect_index: index of the rectangle of SSPP.
*/
struct dpu_hw_stage_cfg {
enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
- enum dpu_sspp_multirect_index multirect_index
- [DPU_STAGE_MAX][PIPES_PER_STAGE];
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 6640906..197fed1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -34,19 +34,6 @@
#define SSPP_SRC_UNPACK_PATTERN 0x34
#define SSPP_SRC_OP_MODE 0x38
-/* SSPP_MULTIRECT*/
-#define SSPP_SRC_SIZE_REC1 0x16C
-#define SSPP_SRC_XY_REC1 0x168
-#define SSPP_OUT_SIZE_REC1 0x160
-#define SSPP_OUT_XY_REC1 0x164
-#define SSPP_SRC_FORMAT_REC1 0x174
-#define SSPP_SRC_UNPACK_PATTERN_REC1 0x178
-#define SSPP_SRC_OP_MODE_REC1 0x17C
-#define SSPP_MULTIRECT_OPMODE 0x170
-#define SSPP_SRC_CONSTANT_COLOR_REC1 0x180
-#define SSPP_EXCL_REC_SIZE_REC1 0x184
-#define SSPP_EXCL_REC_XY_REC1 0x188
-
#define MDSS_MDP_OP_DEINTERLACE BIT(22)
#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23)
#define MDSS_MDP_OP_IGC_ROM_1 BIT(18)
@@ -171,35 +158,6 @@ static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
return rc;
}
-static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
- enum dpu_sspp_multirect_index index,
- enum dpu_sspp_multirect_mode mode)
-{
- u32 mode_mask;
- u32 idx;
-
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
- return;
-
- if (index == DPU_SSPP_RECT_SOLO) {
- /**
- * if rect index is RECT_SOLO, we cannot expect a
- * virtual plane sharing the same SSPP id. So we go
- * and disable multirect
- */
- mode_mask = 0;
- } else {
- mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
- mode_mask |= index;
- if (mode == DPU_SSPP_MULTIRECT_TIME_MX)
- mode_mask |= BIT(2);
- else
- mode_mask &= ~BIT(2);
- }
-
- DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
-}
-
static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
u32 mask, u8 en)
{
@@ -243,31 +201,19 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
* Setup source pixel format, flip,
*/
static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
- const struct dpu_format *fmt, u32 flags,
- enum dpu_sspp_multirect_index rect_mode)
+ const struct dpu_format *fmt, u32 flags)
{
struct dpu_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode = 0;
u32 fast_clear = 0;
- u32 op_mode_off, unpack_pat_off, format_off;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt)
return;
- if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) {
- op_mode_off = SSPP_SRC_OP_MODE;
- unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
- format_off = SSPP_SRC_FORMAT;
- } else {
- op_mode_off = SSPP_SRC_OP_MODE_REC1;
- unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
- format_off = SSPP_SRC_FORMAT_REC1;
- }
-
c = &ctx->hw;
- opmode = DPU_REG_READ(c, op_mode_off + idx);
+ opmode = DPU_REG_READ(c, SSPP_SRC_OP_MODE + idx);
opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
@@ -337,9 +283,9 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
DPU_FORMAT_IS_YUV(fmt));
- DPU_REG_WRITE(c, format_off + idx, src_format);
- DPU_REG_WRITE(c, unpack_pat_off + idx, unpack);
- DPU_REG_WRITE(c, op_mode_off + idx, opmode);
+ DPU_REG_WRITE(c, SSPP_SRC_FORMAT + idx, src_format);
+ DPU_REG_WRITE(c, SSPP_SRC_UNPACK_PATTERN + idx, unpack);
+ DPU_REG_WRITE(c, SSPP_SRC_OP_MODE + idx, opmode);
/* clear previous UBWC error */
DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
@@ -435,12 +381,10 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
* dpu_hw_sspp_setup_rects()
*/
static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index rect_index)
+ struct dpu_hw_pipe_cfg *cfg)
{
struct dpu_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
- u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg)
@@ -448,62 +392,29 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
c = &ctx->hw;
- if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
- src_size_off = SSPP_SRC_SIZE;
- src_xy_off = SSPP_SRC_XY;
- out_size_off = SSPP_OUT_SIZE;
- out_xy_off = SSPP_OUT_XY;
- } else {
- src_size_off = SSPP_SRC_SIZE_REC1;
- src_xy_off = SSPP_SRC_XY_REC1;
- out_size_off = SSPP_OUT_SIZE_REC1;
- out_xy_off = SSPP_OUT_XY_REC1;
- }
-
-
/* src and dest rect programming */
src_xy = (cfg->src_rect.y << 16) | (cfg->src_rect.x);
src_size = (cfg->src_rect.h << 16) | (cfg->src_rect.w);
dst_xy = (cfg->dst_rect.y << 16) | (cfg->dst_rect.x);
dst_size = (cfg->dst_rect.h << 16) | (cfg->dst_rect.w);
- if (rect_index == DPU_SSPP_RECT_SOLO) {
- ystride0 = (cfg->layout.plane_pitch[0]) |
+ ystride0 = (cfg->layout.plane_pitch[0]) |
(cfg->layout.plane_pitch[1] << 16);
- ystride1 = (cfg->layout.plane_pitch[2]) |
+ ystride1 = (cfg->layout.plane_pitch[2]) |
(cfg->layout.plane_pitch[3] << 16);
- } else {
- ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
- ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
-
- if (rect_index == DPU_SSPP_RECT_0) {
- ystride0 = (ystride0 & 0xFFFF0000) |
- (cfg->layout.plane_pitch[0] & 0x0000FFFF);
- ystride1 = (ystride1 & 0xFFFF0000)|
- (cfg->layout.plane_pitch[2] & 0x0000FFFF);
- } else {
- ystride0 = (ystride0 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[0] << 16) &
- 0xFFFF0000);
- ystride1 = (ystride1 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[2] << 16) &
- 0xFFFF0000);
- }
- }
/* rectangle register programming */
- DPU_REG_WRITE(c, src_size_off + idx, src_size);
- DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
- DPU_REG_WRITE(c, out_size_off + idx, dst_size);
- DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
+ DPU_REG_WRITE(c, SSPP_SRC_SIZE + idx, src_size);
+ DPU_REG_WRITE(c, SSPP_SRC_XY + idx, src_xy);
+ DPU_REG_WRITE(c, SSPP_OUT_SIZE + idx, dst_size);
+ DPU_REG_WRITE(c, SSPP_OUT_XY + idx, dst_xy);
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index rect_mode)
+ struct dpu_hw_pipe_cfg *cfg)
{
int i;
u32 idx;
@@ -511,21 +422,9 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (rect_mode == DPU_SSPP_RECT_SOLO) {
- for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
- cfg->layout.plane_addr[i]);
- } else if (rect_mode == DPU_SSPP_RECT_0) {
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
- cfg->layout.plane_addr[0]);
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
- cfg->layout.plane_addr[2]);
- } else {
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
- cfg->layout.plane_addr[0]);
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
- cfg->layout.plane_addr[2]);
- }
+ for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
+ DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
+ cfg->layout.plane_addr[i]);
}
static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
@@ -545,19 +444,14 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
}
-static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
- dpu_sspp_multirect_index rect_index)
+static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color)
{
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0)
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
- else
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx,
- color);
+ DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
}
static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
@@ -660,9 +554,6 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
test_bit(DPU_SSPP_CSC_10BIT, &features))
c->ops.setup_csc = dpu_hw_sspp_setup_csc;
- if (dpu_hw_sspp_multirect_enabled(c->cap))
- c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
-
if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) {
c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
@@ -701,8 +592,7 @@ static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
};
struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
- void __iomem *addr, struct dpu_mdss_cfg *catalog,
- bool is_virtual_pipe)
+ void __iomem *addr, struct dpu_mdss_cfg *catalog)
{
struct dpu_hw_pipe *hw_pipe;
struct dpu_sspp_cfg *cfg;
@@ -734,13 +624,12 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
goto blk_init_error;
}
- if (!is_virtual_pipe)
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name,
- hw_pipe->hw.blk_off,
- hw_pipe->hw.blk_off + hw_pipe->hw.length,
- hw_pipe->hw.xin_id);
+ dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name,
+ hw_pipe->hw.blk_off,
+ hw_pipe->hw.blk_off + hw_pipe->hw.length,
+ hw_pipe->hw.xin_id);
- if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
+ if (cfg->sblk->scaler_blk.len)
dpu_dbg_reg_register_dump_range(DPU_DBG_NAME,
cfg->sblk->scaler_blk.name,
hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 0bb5ecb..b11a9d86 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -49,28 +49,6 @@ enum {
DPU_SSPP_COMP_MAX
};
-/**
- * DPU_SSPP_RECT_SOLO - multirect disabled
- * DPU_SSPP_RECT_0 - rect0 of a multirect pipe
- * DPU_SSPP_RECT_1 - rect1 of a multirect pipe
- *
- * Note: HW supports multirect with either RECT0 or
- * RECT1. Considering no benefit of such configs over
- * SOLO mode and to keep the plane management simple,
- * we dont support single rect multirect configs.
- */
-enum dpu_sspp_multirect_index {
- DPU_SSPP_RECT_SOLO = 0,
- DPU_SSPP_RECT_0,
- DPU_SSPP_RECT_1,
-};
-
-enum dpu_sspp_multirect_mode {
- DPU_SSPP_MULTIRECT_NONE = 0,
- DPU_SSPP_MULTIRECT_PARALLEL,
- DPU_SSPP_MULTIRECT_TIME_MX,
-};
-
enum {
DPU_FRAME_LINEAR,
DPU_FRAME_TILE_A4X,
@@ -159,15 +137,11 @@ struct dpu_hw_pixel_ext {
* @src_rect: src ROI, caller takes into account the different operations
* such as decimation, flip etc to program this field
* @dest_rect: destination ROI.
- * @index: index of the rectangle of SSPP
- * @mode: parallel or time multiplex multirect mode
*/
struct dpu_hw_pipe_cfg {
struct dpu_hw_fmt_layout layout;
struct dpu_rect src_rect;
struct dpu_rect dst_rect;
- enum dpu_sspp_multirect_index index;
- enum dpu_sspp_multirect_mode mode;
};
/**
@@ -235,21 +209,17 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @cfg: Pointer to pipe config structure
* @flags: Extra flags for format config
- * @index: rectangle index in multirect
*/
void (*setup_format)(struct dpu_hw_pipe *ctx,
- const struct dpu_format *fmt, u32 flags,
- enum dpu_sspp_multirect_index index);
+ const struct dpu_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
* @ctx: Pointer to pipe context
* @cfg: Pointer to pipe config structure
- * @index: rectangle index in multirect
*/
void (*setup_rects)(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ struct dpu_hw_pipe_cfg *cfg);
/**
* setup_pe - setup pipe pixel extension
@@ -263,11 +233,9 @@ struct dpu_hw_sspp_ops {
* setup_sourceaddress - setup pipe source addresses
* @ctx: Pointer to pipe context
* @cfg: Pointer to pipe config structure
- * @index: rectangle index in multirect
*/
void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ struct dpu_hw_pipe_cfg *cfg);
/**
* setup_csc - setup color space coversion
@@ -281,21 +249,8 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @const_color: Fill color value
* @flags: Pipe flags
- * @index: rectangle index in multirect
- */
- void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
- enum dpu_sspp_multirect_index index);
-
- /**
- * setup_multirect - setup multirect configuration
- * @ctx: Pointer to pipe context
- * @index: rectangle index in multirect
- * @mode: parallel fetch / time multiplex multirect mode
*/
-
- void (*setup_multirect)(struct dpu_hw_pipe *ctx,
- enum dpu_sspp_multirect_index index,
- enum dpu_sspp_multirect_mode mode);
+ void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color);
/**
* setup_sharpening - setup sharpening
@@ -410,8 +365,7 @@ static inline struct dpu_hw_pipe *to_dpu_hw_pipe(struct dpu_hw_blk *hw)
* @is_virtual_pipe: is this pipe virtual pipe
*/
struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
- void __iomem *addr, struct dpu_mdss_cfg *catalog,
- bool is_virtual_pipe);
+ void __iomem *addr, struct dpu_mdss_cfg *catalog);
/**
* dpu_hw_sspp_destroy(): Destroys SSPP driver context
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8bd1224..3b17a02 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -596,10 +596,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
int primary_planes_idx = 0, i, ret;
int max_crtc_count;
- u32 sspp_id[MAX_PLANES];
- u32 master_plane_id[MAX_PLANES];
- u32 num_virt_planes = 0;
-
if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) {
DPU_ERROR("invalid dpu_kms\n");
return -EINVAL;
@@ -626,7 +622,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
primary = false;
plane = dpu_plane_init(dev, catalog->sspp[i].id, primary,
- (1UL << max_crtc_count) - 1, 0);
+ (1UL << max_crtc_count) - 1);
if (IS_ERR(plane)) {
DPU_ERROR("dpu_plane_init failed\n");
ret = PTR_ERR(plane);
@@ -637,26 +633,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
if (primary)
primary_planes[primary_planes_idx++] = plane;
- if (dpu_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
- dpu_is_custom_client()) {
- int priority =
- catalog->sspp[i].sblk->smart_dma_priority;
- sspp_id[priority - 1] = catalog->sspp[i].id;
- master_plane_id[priority - 1] = plane->base.id;
- num_virt_planes++;
- }
- }
-
- /* Initialize smart DMA virtual planes */
- for (i = 0; i < num_virt_planes; i++) {
- plane = dpu_plane_init(dev, sspp_id[i], false,
- (1UL << max_crtc_count) - 1, master_plane_id[i]);
- if (IS_ERR(plane)) {
- DPU_ERROR("dpu_plane for virtual SSPP init failed\n");
- ret = PTR_ERR(plane);
- goto fail;
- }
- priv->planes[priv->num_planes++] = plane;
}
max_crtc_count = min(max_crtc_count, primary_planes_idx);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 6090ace..0fd05de 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -60,13 +60,6 @@
#define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
#define DPU_ZPOS_MAX 255
-/* multirect rect index */
-enum {
- R0,
- R1,
- R_MAX
-};
-
#define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
#define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
@@ -90,7 +83,6 @@ enum dpu_plane_qos {
* struct dpu_plane - local dpu plane structure
* @aspace: address space pointer
* @csc_ptr: Points to dpu_csc_cfg structure to use for current
- * @mplane_list: List of multirect planes of the same pipe
* @catalog: Points to dpu catalog structure
* @revalidate: force revalidation of all the plane properties
*/
@@ -110,8 +102,6 @@ struct dpu_plane {
uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
- bool is_virtual;
- struct list_head mplane_list;
struct dpu_mdss_cfg *catalog;
struct dpu_csc_cfg *csc_ptr;
@@ -161,7 +151,7 @@ static bool dpu_plane_sspp_enabled(struct drm_plane_state *state)
static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
const struct dpu_format *fmt, u32 src_width)
{
- struct dpu_plane *pdpu, *tmp;
+ struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
u32 fixed_buff_size;
u32 total_fl;
@@ -175,15 +165,6 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
pstate = to_dpu_plane_state(plane->state);
fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
- list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
- if (!dpu_plane_enabled(tmp->base.state))
- continue;
- DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
- pdpu->base.base.id, tmp->base.base.id,
- src_width, tmp->pipe_cfg.src_rect.w);
- src_width = max_t(u32, src_width, tmp->pipe_cfg.src_rect.w);
- }
-
if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
if (fmt->chroma_sample == DPU_CHROMA_420) {
/* NV12 */
@@ -195,13 +176,8 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
((src_width + 32) * fmt->bpp);
}
} else {
- if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
- total_fl = (fixed_buff_size / 2) * 2 /
- ((src_width + 32) * fmt->bpp);
- } else {
total_fl = (fixed_buff_size) * 2 /
((src_width + 32) * fmt->bpp);
- }
}
DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
@@ -619,10 +595,8 @@ static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
pipe_cfg->layout.plane_addr[2],
pipe_cfg->layout.plane_size[2],
pipe_cfg->layout.plane_addr[3],
- pipe_cfg->layout.plane_size[3],
- pstate->multirect_index);
- pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
- pstate->multirect_index);
+ pipe_cfg->layout.plane_size[3]);
+ pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg);
}
}
@@ -812,8 +786,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
/* update sspp */
if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
- pstate->multirect_index);
+ (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
/* override scaler/decimation if solid fill */
pdpu->pipe_cfg.src_rect.x = 0;
@@ -824,20 +797,17 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
if (pdpu->pipe_hw->ops.setup_format)
pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
- fmt, DPU_SSPP_SOLID_FILL,
- pstate->multirect_index);
+ fmt, DPU_SSPP_SOLID_FILL);
if (pdpu->pipe_hw->ops.setup_rects)
pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
- &pdpu->pipe_cfg,
- pstate->multirect_index);
+ &pdpu->pipe_cfg);
if (pdpu->pipe_hw->ops.setup_pe)
pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
&pstate->pixel_ext);
- if (pdpu->pipe_hw->ops.setup_scaler &&
- pstate->multirect_index != DPU_SSPP_RECT_1)
+ if (pdpu->pipe_hw->ops.setup_scaler)
pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
&pdpu->pipe_cfg, &pstate->pixel_ext,
&pstate->scaler3_cfg);
@@ -846,133 +816,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
return 0;
}
-void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
-{
- struct dpu_plane_state *pstate;
-
- if (!drm_state)
- return;
-
- pstate = to_dpu_plane_state(drm_state);
-
- pstate->multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
-}
-
-int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
-{
- struct dpu_plane_state *pstate[R_MAX];
- const struct drm_plane_state *drm_state[R_MAX];
- struct dpu_rect src[R_MAX], dst[R_MAX];
- struct dpu_plane *dpu_plane[R_MAX];
- const struct dpu_format *fmt[R_MAX];
- bool q16_data = true;
- int i, buffer_lines;
- unsigned int max_tile_height = 1;
- bool parallel_fetch_qualified = true;
- bool has_tiled_rect = false;
-
- for (i = 0; i < R_MAX; i++) {
- const struct msm_format *msm_fmt;
-
- drm_state[i] = i ? plane->r1 : plane->r0;
- msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
- fmt[i] = to_dpu_format(msm_fmt);
-
- if (DPU_FORMAT_IS_UBWC(fmt[i])) {
- has_tiled_rect = true;
- if (fmt[i]->tile_height > max_tile_height)
- max_tile_height = fmt[i]->tile_height;
- }
- }
-
- for (i = 0; i < R_MAX; i++) {
- int width_threshold;
-
- pstate[i] = to_dpu_plane_state(drm_state[i]);
- dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
-
- if (pstate[i] == NULL) {
- DPU_ERROR("DPU plane state of plane id %d is NULL\n",
- drm_state[i]->plane->base.id);
- return -EINVAL;
- }
-
- POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
- drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
- POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
- drm_state[i]->crtc_y, drm_state[i]->crtc_w,
- drm_state[i]->crtc_h, !q16_data);
-
- if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
- DPU_ERROR_PLANE(dpu_plane[i],
- "scaling is not supported in multirect mode\n");
- return -EINVAL;
- }
-
- if (DPU_FORMAT_IS_YUV(fmt[i])) {
- DPU_ERROR_PLANE(dpu_plane[i],
- "Unsupported format for multirect mode\n");
- return -EINVAL;
- }
-
- /**
- * SSPP PD_MEM is split half - one for each RECT.
- * Tiled formats need 5 lines of buffering while fetching
- * whereas linear formats need only 2 lines.
- * So we cannot support more than half of the supported SSPP
- * width for tiled formats.
- */
- width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
- if (has_tiled_rect)
- width_threshold /= 2;
-
- if (parallel_fetch_qualified && src[i].w > width_threshold)
- parallel_fetch_qualified = false;
-
- }
-
- /* Validate RECT's and set the mode */
-
- /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
- if (parallel_fetch_qualified) {
- pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
- pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
-
- goto done;
- }
-
- /* TIME_MX Mode */
- buffer_lines = 2 * max_tile_height;
-
- if ((dst[R1].y >= dst[R0].y + dst[R0].h + buffer_lines) ||
- (dst[R0].y >= dst[R1].y + dst[R1].h + buffer_lines)) {
- pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
- pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
- } else {
- DPU_ERROR(
- "No multirect mode possible for the planes (%d - %d)\n",
- drm_state[R0]->plane->base.id,
- drm_state[R1]->plane->base.id);
- return -EINVAL;
- }
-
-done:
- if (dpu_plane[R0]->is_virtual) {
- pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
- pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
- } else {
- pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
- pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
- };
-
- DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
- pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
- DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
- pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
- return 0;
-}
-
/**
* dpu_plane_get_ctl_flush - get control flush for the given plane
* @plane: Pointer to drm plane structure
@@ -1329,38 +1172,23 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
if (pdpu->pipe_hw->ops.setup_rects) {
pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
- &pdpu->pipe_cfg,
- pstate->multirect_index);
+ &pdpu->pipe_cfg);
}
- if (pdpu->pipe_hw->ops.setup_pe &&
- (pstate->multirect_index != DPU_SSPP_RECT_1))
+ if (pdpu->pipe_hw->ops.setup_pe)
pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
&pstate->pixel_ext);
- /**
- * when programmed in multirect mode, scalar block will be
- * bypassed. Still we need to update alpha and bitwidth
- * ONLY for RECT0
- */
- if (pdpu->pipe_hw->ops.setup_scaler &&
- pstate->multirect_index != DPU_SSPP_RECT_1)
+ if (pdpu->pipe_hw->ops.setup_scaler)
pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
&pdpu->pipe_cfg, &pstate->pixel_ext,
&pstate->scaler3_cfg);
- if (pdpu->pipe_hw->ops.setup_multirect)
- pdpu->pipe_hw->ops.setup_multirect(
- pdpu->pipe_hw,
- pstate->multirect_index,
- pstate->multirect_mode);
-
if (pdpu->pipe_hw->ops.setup_format) {
src_flags = 0x0;
/* update format */
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
- pstate->multirect_index);
+ pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags);
if (pdpu->pipe_hw->ops.setup_cdp) {
struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
@@ -1398,44 +1226,12 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
return 0;
}
-static void _dpu_plane_atomic_disable(struct drm_plane *plane,
- struct drm_plane_state *old_state)
-{
- struct dpu_plane *pdpu;
- struct drm_plane_state *state;
- struct dpu_plane_state *pstate;
-
- if (!plane) {
- DPU_ERROR("invalid plane\n");
- return;
- } else if (!plane->state) {
- DPU_ERROR("invalid plane state\n");
- return;
- } else if (!old_state) {
- DPU_ERROR("invalid old state\n");
- return;
- }
-
- pdpu = to_dpu_plane(plane);
- state = plane->state;
- pstate = to_dpu_plane_state(state);
-
- DPU_EVT32(DRMID(plane), is_dpu_plane_virtual(plane),
- pstate->multirect_mode);
-
- pstate->pending = true;
-
- if (is_dpu_plane_virtual(plane) &&
- pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
- pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
- DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE);
-}
-
static void dpu_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct dpu_plane *pdpu;
struct drm_plane_state *state;
+ struct dpu_plane_state *pstate;
if (!plane) {
DPU_ERROR("invalid plane\n");
@@ -1448,11 +1244,12 @@ static void dpu_plane_atomic_update(struct drm_plane *plane,
pdpu = to_dpu_plane(plane);
pdpu->is_error = false;
state = plane->state;
+ pstate = to_dpu_plane_state(state);
DPU_DEBUG_PLANE(pdpu, "\n");
if (!dpu_plane_sspp_enabled(state)) {
- _dpu_plane_atomic_disable(plane, old_state);
+ pstate->pending = true;
} else {
int ret;
@@ -1830,18 +1627,12 @@ enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
}
-bool is_dpu_plane_virtual(struct drm_plane *plane)
-{
- return plane ? to_dpu_plane(plane)->is_virtual : false;
-}
-
/* initialize plane */
struct drm_plane *dpu_plane_init(struct drm_device *dev,
uint32_t pipe, bool primary_plane,
- unsigned long possible_crtcs, u32 master_plane_id)
+ unsigned long possible_crtcs)
{
- struct drm_plane *plane = NULL, *master_plane = NULL;
- const struct dpu_format_extended *format_list;
+ struct drm_plane *plane = NULL;
struct dpu_plane *pdpu;
struct msm_drm_private *priv;
struct dpu_kms *kms;
@@ -1882,18 +1673,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
/* cache local stuff for later */
plane = &pdpu->base;
pdpu->pipe = pipe;
- pdpu->is_virtual = (master_plane_id != 0);
- INIT_LIST_HEAD(&pdpu->mplane_list);
- master_plane = drm_plane_find(dev, NULL, master_plane_id);
- if (master_plane) {
- struct dpu_plane *mpdpu = to_dpu_plane(master_plane);
-
- list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
- }
/* initialize underlying h/w driver */
- pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
- master_plane_id != 0);
+ pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
+
if (IS_ERR(pdpu->pipe_hw)) {
DPU_ERROR("[%u]SSPP init failed\n", pipe);
ret = PTR_ERR(pdpu->pipe_hw);
@@ -1911,12 +1694,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
goto clean_sspp;
}
- if (!master_plane_id)
- format_list = pdpu->pipe_sblk->format_list;
- else
- format_list = pdpu->pipe_sblk->virt_format_list;
-
- pdpu->nformats = dpu_populate_formats(format_list,
+ pdpu->nformats = dpu_populate_formats(
+ pdpu->pipe_sblk->format_list,
pdpu->formats,
0,
ARRAY_SIZE(pdpu->formats));
@@ -1959,8 +1738,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
mutex_init(&pdpu->lock);
- DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
- pipe, plane->base.id, master_plane_id);
+ DPU_DEBUG("%s created for pipe:%u id:%u\n", pdpu->pipe_name,
+ pipe, plane->base.id);
return plane;
clean_sspp:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index f6fe6dd..3795a336 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -46,8 +46,6 @@ struct dpu_plane_state {
struct msm_gem_address_space *aspace;
void *input_fence;
enum dpu_stage stage;
- uint32_t multirect_index;
- uint32_t multirect_mode;
bool pending;
/* scaler configuration */
@@ -57,16 +55,6 @@ struct dpu_plane_state {
struct dpu_hw_pipe_cdp_cfg cdp_cfg;
};
-/**
- * struct dpu_multirect_plane_states: Defines multirect pair of drm plane states
- * @r0: drm plane configured on rect 0
- * @r1: drm plane configured on rect 1
- */
-struct dpu_multirect_plane_states {
- const struct drm_plane_state *r0;
- const struct drm_plane_state *r1;
-};
-
#define to_dpu_plane_state(x) \
container_of(x, struct dpu_plane_state, base)
@@ -78,14 +66,6 @@ struct dpu_multirect_plane_states {
enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane);
/**
- * is_dpu_plane_virtual - check for virtual plane
- * @plane: Pointer to DRM plane object
- * returns: true - if the plane is virtual
- * false - if the plane is primary
- */
-bool is_dpu_plane_virtual(struct drm_plane *plane);
-
-/**
* dpu_plane_get_ctl_flush - get control flush mask
* @plane: Pointer to DRM plane object
* @ctl: Pointer to control hardware
@@ -124,27 +104,11 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
* @pipe: dpu hardware pipe identifier
* @primary_plane: true if this pipe is primary plane for crtc
* @possible_crtcs: bitmask of crtc that can be attached to the given pipe
- * @master_plane_id: primary plane id of a multirect pipe. 0 value passed for
- * a regular plane initialization. A non-zero primary plane
- * id will be passed for a virtual pipe initialization.
*
*/
struct drm_plane *dpu_plane_init(struct drm_device *dev,
uint32_t pipe, bool primary_plane,
- unsigned long possible_crtcs, u32 master_plane_id);
-
-/**
- * dpu_plane_validate_multirecti_v2 - validate the multirect planes
- * against hw limitations
- * @plane: drm plate states of the multirect pair
- */
-int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane);
-
-/**
- * dpu_plane_clear_multirect - clear multirect bits for the given pipe
- * @drm_state: Pointer to DRM plane state
- */
-void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state);
+ unsigned long possible_crtcs);
/**
* dpu_plane_wait_input_fence - wait for input fence object
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 1affc7f..3958994 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -62,7 +62,7 @@
#define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */
#define MAX_CRTCS 8
-#define MAX_PLANES 20
+#define MAX_PLANES 12
#define MAX_ENCODERS 8
#define MAX_BRIDGES 8
#define MAX_CONNECTORS 8
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 9+ messages in thread* [DPU PATCH 3/5] drm/msm/dpu: remove static binding of hw pipe to plane
[not found] ` <1529499020-8499-1-git-send-email-skolluku-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-06-20 12:50 ` [DPU PATCH 1/5] drm/msm/dpu: remove smart dma support Sravanthi Kollukuduru
@ 2018-06-20 12:50 ` Sravanthi Kollukuduru
2018-06-20 12:50 ` [DPU PATCH 4/5] drm/msm/dpu: introduce state based plane resource management Sravanthi Kollukuduru
2018-06-20 12:50 ` [DPU PATCH 5/5] drm/msm/dpu: dynamic assignment of hw pipe to plane Sravanthi Kollukuduru
3 siblings, 0 replies; 9+ messages in thread
From: Sravanthi Kollukuduru @ 2018-06-20 12:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: robdclark-Re5JQEeQqe8AvxtiuMwx3w, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, Sravanthi Kollukuduru
Expose all planes with superset of formats and with no
hw pipe static binding. Accordingly, remove checks from
atomic_check reflecting the decoupling.
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 26 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 50 +++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 17 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 158 ++++---------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 5 +-
5 files changed, 56 insertions(+), 200 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c0b8116..c2a7c64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -44,13 +44,6 @@
#define DEFAULT_DPU_LINE_WIDTH 2048
#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
-#define MAX_HORZ_DECIMATION 4
-#define MAX_VERT_DECIMATION 4
-
-#define MAX_UPSCALE_RATIO 20
-#define MAX_DOWNSCALE_RATIO 4
-#define SSPP_UNITY_SCALE 1
-
#define STRCAT(X, Y) (X Y)
/*************************************************************
@@ -58,9 +51,12 @@
*************************************************************/
/* DPU top level caps */
static const struct dpu_caps sdm845_dpu_caps = {
+ .max_sspp_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_sspp_pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .csc_type = DPU_SSPP_CSC_10BIT,
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_src_split = true,
.has_dim_layer = true,
@@ -128,19 +124,8 @@
* SSPP sub blocks config
*************************************************************/
-/* SSPP common configuration */
-static const struct dpu_sspp_blks_common sdm845_sspp_common = {
- .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
- .maxhdeciexp = MAX_HORZ_DECIMATION,
- .maxvdeciexp = MAX_VERT_DECIMATION,
-};
-
#define _VIG_SBLK(num) \
{ \
- .common = &sdm845_sspp_common, \
- .maxdwnscale = MAX_DOWNSCALE_RATIO, \
- .maxupscale = MAX_UPSCALE_RATIO, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
@@ -149,17 +134,12 @@
.csc_blk = {.name = STRCAT("sspp_csc", num), \
.id = DPU_SSPP_CSC_10BIT, \
.base = 0x1a00, .len = 0x100,}, \
- .format_list = plane_formats_yuv, \
}
#define _DMA_SBLK(num) \
{ \
- .common = &sdm845_sspp_common, \
- .maxdwnscale = SSPP_UNITY_SCALE, \
- .maxupscale = SSPP_UNITY_SCALE, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
- .format_list = plane_formats, \
}
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1b04448..68644db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -63,6 +63,10 @@
#define CRTC_DUAL_MIXERS 2
+#define MAX_UPSCALE_RATIO 20
+#define MAX_DOWNSCALE_RATIO 4
+#define SSPP_UNITY_SCALE 1
+
#define MAX_XIN_COUNT 16
/**
@@ -290,19 +294,26 @@ struct dpu_qos_lut_tbl {
/**
* struct dpu_caps - define DPU capabilities
- * @max_mixer_width max layer mixer line width support.
- * @max_mixer_blendstages max layer mixer blend stages or
+ * @max_sspp_width max: pixelwidth supported by this pipe
+ * @max_sspp_pixel_ram_size: size of latency hiding and
+ * de-tiling buffer in bytes
+ * @max_mixer_width: max layer mixer line width support
+ * @max_mixer_blendstages: max layer mixer blend stages or
* supported z order
- * @qseed_type qseed2 or qseed3 support.
- * @ubwc_version UBWC feature version (0x0 for not supported)
- * @has_src_split source split feature status
- * @has_dim_layer dim layer feature status
- * @has_idle_pc indicate if idle power collapse feature is supported
+ * @qseed_type: qseed2 or qseed3 support
+ * @csc_type: csc or csc_10bit support
+ * @ubwc_version: UBWC feature version (0x0 for not supported)
+ * @has_src_split: source split feature status
+ * @has_dim_layer: dim layer feature status
+ * @has_idle_pc: indicate if idle power collapse feature is supported
*/
struct dpu_caps {
+ u32 max_sspp_width;
+ u32 max_sspp_pixel_ram_size;
u32 max_mixer_width;
u32 max_mixer_blendstages;
u32 qseed_type;
+ u32 csc_type;
u32 ubwc_version;
bool has_src_split;
bool has_dim_layer;
@@ -310,28 +321,9 @@ struct dpu_caps {
};
/**
- * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
- * @maxwidth: max pixelwidth supported by this pipe
- * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
- * @maxhdeciexp: max horizontal decimation supported by this pipe
- * (max is 2^value)
- * @maxvdeciexp: max vertical decimation supported by this pipe
- * (max is 2^value)
- */
-struct dpu_sspp_blks_common {
- u32 maxlinewidth;
- u32 pixel_ram_size;
- u32 maxhdeciexp;
- u32 maxvdeciexp;
-};
-
-/**
* struct dpu_sspp_sub_blks : SSPP sub-blocks
- * common: Pointer to common configurations shared by sub blocks
* @creq_vblank: creq priority during vertical blanking
* @danger_vblank: danger priority during vertical blanking
- * @maxdwnscale: max downscale ratio supported(without DECIMATION)
- * @maxupscale: maxupscale ratio supported
* @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
* @src_blk:
* @scaler_blk:
@@ -340,14 +332,10 @@ struct dpu_sspp_blks_common {
* @memcolor:
* @pcc_blk:
* @igc_blk:
- * @format_list: Pointer to list of supported formats
*/
struct dpu_sspp_sub_blks {
- const struct dpu_sspp_blks_common *common;
u32 creq_vblank;
u32 danger_vblank;
- u32 maxdwnscale;
- u32 maxupscale;
u32 max_per_pipe_bw;
struct dpu_src_blk src_blk;
struct dpu_scaler_blk scaler_blk;
@@ -356,8 +344,6 @@ struct dpu_sspp_sub_blks {
struct dpu_pp_blk memcolor_blk;
struct dpu_pp_blk pcc_blk;
struct dpu_pp_blk igc_blk;
-
- const struct dpu_format_extended *format_list;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8e2e582..bef4e71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -616,13 +616,16 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
/* Create the planes */
for (i = 0; i < catalog->sspp_count; i++) {
- bool primary = true;
+ enum drm_plane_type type;
- if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)
- || primary_planes_idx >= max_crtc_count)
- primary = false;
+ if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
+ type = DRM_PLANE_TYPE_CURSOR;
+ else if (primary_planes_idx < max_crtc_count)
+ type = DRM_PLANE_TYPE_PRIMARY;
+ else
+ type = DRM_PLANE_TYPE_OVERLAY;
- plane = dpu_plane_init(dev, catalog->sspp[i].id, primary,
+ plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
(1UL << max_crtc_count) - 1);
if (IS_ERR(plane)) {
DPU_ERROR("dpu_plane_init failed\n");
@@ -631,9 +634,9 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
}
priv->planes[priv->num_planes++] = plane;
- if (primary)
+ if (type == DRM_PLANE_TYPE_PRIMARY)
primary_planes[primary_planes_idx++] = plane;
- if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
+ if (type == DRM_PLANE_TYPE_CURSOR)
cursor_planes[cursor_planes_idx++] = plane;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 0fd05de..be40a2c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -151,6 +151,7 @@ static bool dpu_plane_sspp_enabled(struct drm_plane_state *state)
static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
const struct dpu_format *fmt, u32 src_width)
{
+ struct dpu_kms *kms;
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
u32 fixed_buff_size;
@@ -163,7 +164,9 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
pdpu = to_dpu_plane(plane);
pstate = to_dpu_plane_state(plane->state);
- fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
+
+ kms = _dpu_plane_get_kms(&pdpu->base);
+ fixed_buff_size = kms->catalog->caps->max_sspp_pixel_ram_size;
if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
if (fmt->chroma_sample == DPU_CHROMA_420) {
@@ -915,12 +918,14 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
int ret = 0;
+ struct dpu_kms *kms;
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
const struct dpu_format *fmt;
struct dpu_rect src, dst;
uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
bool q16_data = true;
+ uint32_t caps = 0;
if (!plane || !state) {
DPU_ERROR("invalid arg(s), plane %d state %d\n",
@@ -932,11 +937,8 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
pdpu = to_dpu_plane(plane);
pstate = to_dpu_plane_state(state);
- if (!pdpu->pipe_sblk) {
- DPU_ERROR_PLANE(pdpu, "invalid catalog\n");
- ret = -EINVAL;
- goto exit;
- }
+ kms = _dpu_plane_get_kms(&pdpu->base);
+ max_linewidth = kms->catalog->caps->max_sspp_width;
/* src values are in Q16 fixed point, convert to integer */
POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
@@ -944,10 +946,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h, !q16_data);
- max_upscale = pdpu->pipe_sblk->maxupscale;
- max_downscale = pdpu->pipe_sblk->maxdwnscale;
- max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
-
DPU_DEBUG_PLANE(pdpu, "check %d -> %d\n",
dpu_plane_enabled(plane->state), dpu_plane_enabled(state));
@@ -956,18 +954,19 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
fmt = to_dpu_format(msm_framebuffer_format(state->fb));
- min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
+ if (DPU_FORMAT_IS_YUV(fmt))
+ caps |= BIT(kms->catalog->caps->qseed_type) |
+ BIT(kms->catalog->caps->csc_type);
- if (DPU_FORMAT_IS_YUV(fmt) &&
- (!(pdpu->features & DPU_SSPP_SCALER) ||
- !(pdpu->features & (BIT(DPU_SSPP_CSC)
- | BIT(DPU_SSPP_CSC_10BIT))))) {
- DPU_ERROR_PLANE(pdpu,
- "plane doesn't have scaler/csc for yuv\n");
- ret = -EINVAL;
+ if ((src.w != dst.w) || (src.h != dst.h))
+ caps |= BIT(kms->catalog->caps->qseed_type);
+
+ max_upscale = (caps & DPU_SSPP_SCALER) ? MAX_UPSCALE_RATIO : 1;
+ max_downscale = (caps & DPU_SSPP_SCALER) ? MAX_DOWNSCALE_RATIO : 1;
+ min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
/* check src bounds */
- } else if (state->fb->width > MAX_IMG_WIDTH ||
+ if (state->fb->width > MAX_IMG_WIDTH ||
state->fb->height > MAX_IMG_HEIGHT ||
src.w < min_src_size || src.h < min_src_size ||
CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
@@ -989,14 +988,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
dst.x, dst.y, dst.w, dst.h);
ret = -EINVAL;
- /* decimation validation */
- } else if (!(pdpu->features & DPU_SSPP_SCALER) &&
- ((src.w != dst.w) || (src.h != dst.h))) {
- DPU_ERROR_PLANE(pdpu,
- "pipe doesn't support scaling %ux%u->%ux%u\n",
- src.w, src.h, dst.w, dst.h);
- ret = -EINVAL;
-
/* check decimated source width */
} else if (src.w > max_linewidth) {
DPU_ERROR_PLANE(pdpu,
@@ -1292,9 +1283,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
/* this will destroy the states as well */
drm_plane_cleanup(plane);
- if (pdpu->pipe_hw)
- dpu_hw_sspp_destroy(pdpu->pipe_hw);
-
kfree(pdpu);
}
}
@@ -1479,8 +1467,6 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
struct dpu_plane *pdpu;
struct dpu_kms *kms;
struct msm_drm_private *priv;
- const struct dpu_sspp_sub_blks *sblk = 0;
- const struct dpu_sspp_cfg *cfg = 0;
if (!plane || !plane->dev) {
DPU_ERROR("invalid arguments\n");
@@ -1496,14 +1482,6 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
kms = to_dpu_kms(priv->kms);
pdpu = to_dpu_plane(plane);
- if (pdpu && pdpu->pipe_hw)
- cfg = pdpu->pipe_hw->cap;
- if (cfg)
- sblk = cfg->sblk;
-
- if (!sblk)
- return 0;
-
/* create overall sub-directory for the pipe */
pdpu->debugfs_root =
debugfs_create_dir(pdpu->pipe_name,
@@ -1512,60 +1490,6 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
if (!pdpu->debugfs_root)
return -ENOMEM;
- /* don't error check these */
- debugfs_create_x32("features", 0600,
- pdpu->debugfs_root, &pdpu->features);
-
- /* add register dump support */
- dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
- sblk->src_blk.base + cfg->base,
- sblk->src_blk.len,
- kms);
- dpu_debugfs_create_regset32("src_blk", 0400,
- pdpu->debugfs_root, &pdpu->debugfs_src);
-
- if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
- cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) {
- dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
- sblk->scaler_blk.base + cfg->base,
- sblk->scaler_blk.len,
- kms);
- dpu_debugfs_create_regset32("scaler_blk", 0400,
- pdpu->debugfs_root,
- &pdpu->debugfs_scaler);
- debugfs_create_bool("default_scaling",
- 0600,
- pdpu->debugfs_root,
- &pdpu->debugfs_default_scale);
- }
-
- if (cfg->features & BIT(DPU_SSPP_CSC) ||
- cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
- dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
- sblk->csc_blk.base + cfg->base,
- sblk->csc_blk.len,
- kms);
- dpu_debugfs_create_regset32("csc_blk", 0400,
- pdpu->debugfs_root, &pdpu->debugfs_csc);
- }
-
- debugfs_create_u32("xin_id",
- 0400,
- pdpu->debugfs_root,
- (u32 *) &cfg->xin_id);
- debugfs_create_u32("clk_ctrl",
- 0400,
- pdpu->debugfs_root,
- (u32 *) &cfg->clk_ctrl);
- debugfs_create_x32("creq_vblank",
- 0600,
- pdpu->debugfs_root,
- (u32 *) &sblk->creq_vblank);
- debugfs_create_x32("danger_vblank",
- 0600,
- pdpu->debugfs_root,
- (u32 *) &sblk->danger_vblank);
-
debugfs_create_file("disable_danger",
0600,
pdpu->debugfs_root,
@@ -1629,14 +1553,13 @@ enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
/* initialize plane */
struct drm_plane *dpu_plane_init(struct drm_device *dev,
- uint32_t pipe, bool primary_plane,
+ uint32_t pipe, enum drm_plane_type type,
unsigned long possible_crtcs)
{
struct drm_plane *plane = NULL;
struct dpu_plane *pdpu;
struct msm_drm_private *priv;
struct dpu_kms *kms;
- enum drm_plane_type type;
int zpos_max = DPU_ZPOS_MAX;
int ret = -EINVAL;
@@ -1670,54 +1593,22 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
goto exit;
}
- /* cache local stuff for later */
plane = &pdpu->base;
- pdpu->pipe = pipe;
-
- /* initialize underlying h/w driver */
- pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
- if (IS_ERR(pdpu->pipe_hw)) {
- DPU_ERROR("[%u]SSPP init failed\n", pipe);
- ret = PTR_ERR(pdpu->pipe_hw);
- goto clean_plane;
- } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
- DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
- goto clean_sspp;
- }
-
- /* cache features mask for later */
- pdpu->features = pdpu->pipe_hw->cap->features;
- pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
- if (!pdpu->pipe_sblk) {
- DPU_ERROR("[%u]invalid sblk\n", pipe);
- goto clean_sspp;
- }
-
- pdpu->nformats = dpu_populate_formats(
- pdpu->pipe_sblk->format_list,
- pdpu->formats,
- 0,
+ pdpu->nformats = dpu_populate_formats(plane_formats_yuv,
+ pdpu->formats, 0,
ARRAY_SIZE(pdpu->formats));
if (!pdpu->nformats) {
DPU_ERROR("[%u]no valid formats for plane\n", pipe);
- goto clean_sspp;
+ goto clean_plane;
}
- if (pdpu->features & BIT(DPU_SSPP_CURSOR))
- type = DRM_PLANE_TYPE_CURSOR;
- else if (primary_plane)
- type = DRM_PLANE_TYPE_PRIMARY;
- else
- type = DRM_PLANE_TYPE_OVERLAY;
ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
pdpu->formats, pdpu->nformats,
NULL, type, NULL);
if (ret)
- goto clean_sspp;
-
- pdpu->catalog = kms->catalog;
+ goto clean_plane;
if (kms->catalog->mixer_count &&
kms->catalog->mixer[0].sblk->maxblendstages) {
@@ -1742,9 +1633,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pipe, plane->base.id);
return plane;
-clean_sspp:
- if (pdpu && pdpu->pipe_hw)
- dpu_hw_sspp_destroy(pdpu->pipe_hw);
clean_plane:
kfree(pdpu);
exit:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 3795a336..e0688895 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -102,12 +102,11 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
* dpu_plane_init - create new dpu plane for the given pipe
* @dev: Pointer to DRM device
* @pipe: dpu hardware pipe identifier
- * @primary_plane: true if this pipe is primary plane for crtc
+ * @type: plane type - PRIMARY/CURSOR/OVERLAY
* @possible_crtcs: bitmask of crtc that can be attached to the given pipe
- *
*/
struct drm_plane *dpu_plane_init(struct drm_device *dev,
- uint32_t pipe, bool primary_plane,
+ uint32_t pipe, enum drm_plane_type type,
unsigned long possible_crtcs);
/**
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 9+ messages in thread* [DPU PATCH 4/5] drm/msm/dpu: introduce state based plane resource management
[not found] ` <1529499020-8499-1-git-send-email-skolluku-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-06-20 12:50 ` [DPU PATCH 1/5] drm/msm/dpu: remove smart dma support Sravanthi Kollukuduru
2018-06-20 12:50 ` [DPU PATCH 3/5] drm/msm/dpu: remove static binding of hw pipe to plane Sravanthi Kollukuduru
@ 2018-06-20 12:50 ` Sravanthi Kollukuduru
2018-06-20 12:50 ` [DPU PATCH 5/5] drm/msm/dpu: dynamic assignment of hw pipe to plane Sravanthi Kollukuduru
3 siblings, 0 replies; 9+ messages in thread
From: Sravanthi Kollukuduru @ 2018-06-20 12:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: robdclark-Re5JQEeQqe8AvxtiuMwx3w, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, Sravanthi Kollukuduru
A plane can be attached to a maximum of two hw pipes
in case of wide resolution greater than pipe's max width limit.
This mapping of hw pipe(s) to plane and number of pipes will be
maintained in the plane state.
Resource manager (RM) will handle the SSPP blocks reservation
for a given plane.
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 11 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 156 +++++++++++++++++++++++++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 20 ++++
3 files changed, 172 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index e0688895..4eb929b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -25,6 +25,8 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_sspp.h"
+#define PLANE_DUAL_PIPES 2
+
/**
* struct dpu_plane_state: Define dpu extension of drm plane state object
* @base: base drm plane state object
@@ -36,6 +38,8 @@
* @multirect_index: index of the rectangle of SSPP
* @multirect_mode: parallel or time multiplex multirect mode
* @pending: whether the current update is still pending
+ * @num_pipes: number of pipes attached to plane
+ * @pipe_hw: array of pointers to hardware pipes reserved for plane
* @scaler3_cfg: configuration data for scaler3
* @pixel_ext: configuration data for pixel extensions
* @scaler_check_state: indicates status of user provided pixel extension data
@@ -48,6 +52,10 @@ struct dpu_plane_state {
enum dpu_stage stage;
bool pending;
+ /* HW pipe config */
+ u32 num_pipes;
+ struct dpu_hw_pipe *pipe_hw[PLANE_DUAL_PIPES];
+
/* scaler configuration */
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
@@ -58,6 +66,9 @@ struct dpu_plane_state {
#define to_dpu_plane_state(x) \
container_of(x, struct dpu_plane_state, base)
+/* get plane id from dpu plane state */
+#define get_plane_id(x) ((x->base.plane)->base.id)
+
/**
* dpu_plane_pipe - return sspp identifier for the given plane
* @plane: Pointer to DRM plane object
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 018d01a..5387600 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -14,6 +14,7 @@
#define pr_fmt(fmt) "[drm:%s] " fmt, __func__
#include "dpu_kms.h"
+#include "dpu_hw_sspp.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_cdm.h"
@@ -22,10 +23,13 @@
#include "dpu_encoder.h"
#include "dpu_rm.h"
+#define RESERVED_BY_OTHER(drm_map_id, drm_id) \
+ (drm_map_id && (drm_map_id != drm_id))
+
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @type: Type of hardware block this structure tracks
- * @drm_id: DRM component ID associated with the HW block
+ * @rm_id: DRM component ID associated with the HW block
* @id: Hardware ID number, within it's own space, ie. LM_X
* @hw: Pointer to the hardware register access object for this block
*/
@@ -157,7 +161,8 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
dpu_hw_intf_destroy(hw);
break;
case DPU_HW_BLK_SSPP:
- /* SSPPs are not managed by the resource manager */
+ dpu_hw_sspp_destroy(hw);
+ break;
case DPU_HW_BLK_TOP:
/* Top is a singleton, not managed in hw_blks list */
case DPU_HW_BLK_MAX:
@@ -229,7 +234,8 @@ static int _dpu_rm_hw_blk_create(
hw = dpu_hw_intf_init(id, mmio, cat);
break;
case DPU_HW_BLK_SSPP:
- /* SSPPs are not managed by the resource manager */
+ hw = dpu_hw_sspp_init(id, mmio, cat);
+ break;
case DPU_HW_BLK_TOP:
/* Top is a singleton, not managed in hw_blks list */
case DPU_HW_BLK_MAX:
@@ -281,6 +287,15 @@ int dpu_rm_init(struct dpu_rm *rm,
}
/* Interrogate HW catalog and create tracking items for hw blocks */
+ for (i = 0; i < cat->sspp_count; i++) {
+ rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_SSPP,
+ cat->sspp[i].id, &cat->sspp[i]);
+ if (rc) {
+ DPU_ERROR("failed: sspp hw not available\n");
+ goto fail;
+ }
+ }
+
for (i = 0; i < cat->mixer_count; i++) {
struct dpu_lm_cfg *lm = &cat->mixer[i];
@@ -570,12 +585,10 @@ static int _dpu_rm_reserve_intf_related_hw(
}
static int _dpu_rm_release_hw_blk(
- struct dpu_rm *rm,
- struct dpu_crtc_state *state,
+ struct dpu_rm *rm, int drm_id,
enum dpu_hw_blk_type type)
{
struct dpu_rm_hw_iter iter;
- int drm_id = get_crtc_id(state);
int num_released = 0;
int *drm_map = rm->hw_drm_map[type];
@@ -590,15 +603,15 @@ static int _dpu_rm_release_hw_blk(
return num_released;
}
-static int _dpu_rm_release_lms(struct dpu_rm *rm, struct dpu_crtc_state *state)
+static int _dpu_rm_release_lms(struct dpu_rm *rm, int drm_id)
{
int num_lm, num_pp;
/* Release LM blocks */
- num_lm = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_LM);
+ num_lm = _dpu_rm_release_hw_blk(rm, drm_id, DPU_HW_BLK_LM);
/* Rlease ping pong blocks */
- num_pp = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_PINGPONG);
+ num_pp = _dpu_rm_release_hw_blk(rm, drm_id, DPU_HW_BLK_PINGPONG);
if (num_pp != num_lm) {
DPU_ERROR("lm chain count mismatch lm: %d pp:%d\n",
num_lm, num_pp);
@@ -639,26 +652,28 @@ int dpu_rm_reserve_crtc_res(struct dpu_rm *rm, struct dpu_crtc_state *state,
int dpu_rm_release_crtc_res(struct dpu_rm *rm, struct dpu_crtc_state *state)
{
int rc = 0, num_released;
+ int drm_id = get_crtc_id(state);
mutex_lock(&rm->rm_lock);
- num_released = _dpu_rm_release_lms(rm, state);
+ num_released = _dpu_rm_release_lms(rm, drm_id);
if (num_released != state->num_mixers) {
DPU_ERROR(
"lm release count doesn't match for crtc: %d (%d != %d)\n",
- get_crtc_id(state), num_released, state->num_mixers);
+ drm_id, num_released, state->num_mixers);
rc = -EINVAL;
goto release_done;
}
- num_released = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_CTL);
+ num_released = _dpu_rm_release_hw_blk(rm, drm_id, DPU_HW_BLK_CTL);
if (num_released != state->num_ctls) {
DPU_ERROR(
"lm release count doesn't match for crtc: %d (%d != %d)\n",
- get_crtc_id(state), num_released, state->num_ctls);
+ drm_id, num_released, state->num_ctls);
rc = -EINVAL;
goto release_done;
}
+
release_done:
mutex_unlock(&rm->rm_lock);
@@ -692,14 +707,15 @@ int dpu_rm_release_encoder_res(struct dpu_rm *rm, struct dpu_crtc_state *state)
{
int num_released;
int rc = 0;
+ int drm_id = get_crtc_id(state);
mutex_lock(&rm->rm_lock);
- num_released = _dpu_rm_release_hw_blk(rm, state, DPU_HW_BLK_INTF);
+ num_released = _dpu_rm_release_hw_blk(rm, drm_id, DPU_HW_BLK_INTF);
if (num_released != state->num_intfs) {
DPU_ERROR(
"intf release count doesn't match for crtc: %d (%d != %d)\n",
- get_crtc_id(state), num_released, state->num_intfs);
+ drm_id, num_released, state->num_intfs);
rc = -EINVAL;
}
@@ -711,3 +727,113 @@ int dpu_rm_release_encoder_res(struct dpu_rm *rm, struct dpu_crtc_state *state)
return rc;
}
+static int _dpu_rm_reserve_sspp(struct dpu_rm *rm,
+ struct dpu_plane_state *state, u32 num_pipes, u32 caps)
+{
+ struct dpu_rm_hw_blk *sspp[MAX_BLOCKS];
+ struct dpu_rm_hw_iter iter_i, iter_j;
+ const struct dpu_sspp_cfg *lpipe_cfg, *rpipe_cfg;
+ int sspp_count = 0, i;
+ int drm_id = get_plane_id(state);
+ int *sspp_drm_map = rm->hw_drm_map[DPU_HW_BLK_SSPP];
+
+ dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_SSPP);
+
+ while ((sspp_count != num_pipes) &&
+ _dpu_rm_get_hw_locked(rm, &iter_i)) {
+ sspp_count = 0;
+
+ /* skip if pipe has been reserved by different plane */
+ if (RESERVED_BY_OTHER(sspp_drm_map[iter_i.blk->rm_id], drm_id))
+ continue;
+
+ /* skip if pipe doesn't support the required caps */
+ lpipe_cfg = to_dpu_hw_pipe(iter_i.blk->hw)->cap;
+ if (caps & ~lpipe_cfg->features)
+ continue;
+
+ /* skip cursor pipe assignment to non cursor plane type */
+ if ((caps & DPU_SSPP_CURSOR) &&
+ (state->base.plane)->type != DRM_PLANE_TYPE_CURSOR)
+ continue;
+
+ sspp[sspp_count++] = iter_i.blk;
+
+ /**
+ * Find another sspp of same type and honoring
+ * priority - VIG0 > VIG1
+ */
+ dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_SSPP);
+
+ while (sspp_count != num_pipes &&
+ _dpu_rm_get_hw_locked(rm, &iter_j)) {
+ if ((iter_i.blk == iter_j.blk) || RESERVED_BY_OTHER(
+ sspp_drm_map[iter_j.blk->rm_id], drm_id))
+ continue;
+
+ rpipe_cfg = to_dpu_hw_pipe(iter_j.blk->hw)->cap;
+ if ((rpipe_cfg->features != lpipe_cfg->features)
+ || (lpipe_cfg->id > rpipe_cfg->id))
+ continue;
+
+ sspp[sspp_count++] = iter_j.blk;
+ break;
+ }
+ }
+
+ if (sspp_count != num_pipes) {
+ DPU_DEBUG("unable to find appropriate hw pipes\n");
+ return -ENAVAIL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sspp) && i < num_pipes; i++) {
+ sspp_drm_map[sspp[i]->rm_id] = drm_id;
+
+ state->pipe_hw[i] = to_dpu_hw_pipe(sspp[i]->hw);
+ DPU_DEBUG("%d : sspp %d reserved for plane id %d\n",
+ i, sspp[i]->id, drm_id);
+ }
+
+ state->num_pipes = num_pipes;
+ return 0;
+}
+
+int dpu_rm_reserve_plane_res(struct dpu_rm *rm,
+ struct dpu_plane_state *state, u32 num_pipes, u32 caps)
+{
+ int rc = 0;
+
+ mutex_lock(&rm->rm_lock);
+
+ rc = _dpu_rm_reserve_sspp(rm, state, num_pipes, caps);
+ if (rc)
+ DPU_ERROR("unable to allocate %d sspp for plane: %d\n",
+ num_pipes, get_plane_id(state));
+
+ mutex_unlock(&rm->rm_lock);
+ return rc;
+}
+
+int dpu_rm_release_plane_res(struct dpu_rm *rm, struct dpu_plane_state *state)
+{
+ int num_released;
+ int rc = 0;
+ int drm_id = get_plane_id(state);
+
+ mutex_lock(&rm->rm_lock);
+
+ num_released = _dpu_rm_release_hw_blk(rm, drm_id, DPU_HW_BLK_SSPP);
+ if (num_released != state->num_pipes) {
+ DPU_ERROR(
+ "sspp release count doesn't match for plane: %d (%d != %d)\n",
+ drm_id, num_released, state->num_pipes);
+ rc = -EINVAL;
+ }
+
+ mutex_unlock(&rm->rm_lock);
+
+ state->num_pipes = 0;
+ memset(&state->pipe_hw, 0, sizeof(state->pipe_hw));
+
+ return rc;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index fa2cd70..b43e19a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -20,6 +20,7 @@
#include "dpu_hw_top.h"
#include "dpu_crtc.h"
#include "dpu_encoder.h"
+#include "dpu_plane.h"
/**
* struct dpu_rm - DPU dynamic hardware resource manager
@@ -86,6 +87,25 @@ int dpu_rm_init(struct dpu_rm *rm,
int dpu_rm_destroy(struct dpu_rm *rm);
/**
+ * dpu_rm_reserve_plane_res - Reserve HW blocks for PLANE
+ * @rm: DPU Resource Manager handle
+ * @state: DPU PLANE state to cache HW block handles
+ * @num_pipes: Number of pipes to be reserved for the plane
+ * @caps: Reserve hw blocks with matching capabilities
+ * @Return: 0 on Success otherwise -ERROR
+ */
+int dpu_rm_reserve_plane_res(struct dpu_rm *rm, struct dpu_plane_state *state,
+ u32 num_pipes, u32 caps);
+
+/**
+ * dpu_rm_release_plane_res - Release HW blocks of PLANE
+ * @rm: DPU Resource Manager handle
+ * @state: DPU PLANE state to cache HW block handles
+ * @plane_id: Release reservation for given plane id
+ */
+int dpu_rm_release_plane_res(struct dpu_rm *rm, struct dpu_plane_state *state);
+
+/**
* dpu_rm_reserve_crtc_res - Reserve HW blocks for CRTC
* @rm: DPU Resource Manager handle
* @state: DPU CRTC state to cache HW block handles
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 9+ messages in thread* [DPU PATCH 5/5] drm/msm/dpu: dynamic assignment of hw pipe to plane
[not found] ` <1529499020-8499-1-git-send-email-skolluku-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
` (2 preceding siblings ...)
2018-06-20 12:50 ` [DPU PATCH 4/5] drm/msm/dpu: introduce state based plane resource management Sravanthi Kollukuduru
@ 2018-06-20 12:50 ` Sravanthi Kollukuduru
3 siblings, 0 replies; 9+ messages in thread
From: Sravanthi Kollukuduru @ 2018-06-20 12:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: robdclark-Re5JQEeQqe8AvxtiuMwx3w, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, Sravanthi Kollukuduru
Currently, there exists a static binding of hw pipe to
plane. This restricts wide plane support where plane width
exceeds the pipe's maximum width.
To enable such use cases, the hw pipes are dynamically
(re)allocated to a plane during atomic check based on the
plane capabilities.
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 45 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 670 +++++++++++++++++-------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
3 files changed, 414 insertions(+), 305 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 56f6576..afb8c79 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -175,7 +175,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct dpu_rect plane_crtc_roi;
u32 flush_mask;
- uint32_t stage_idx, lm_idx;
+ uint32_t stage_idx = 0, lm_idx;
+ int i;
int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
bool bg_alpha_enable = false;
@@ -204,11 +205,11 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
- DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
- crtc->base.id,
- pstate->stage,
- plane->base.id,
- dpu_plane_pipe(plane) - SSPP_VIG0,
+ DPU_DEBUG("crtc %d stage%d: plane%d ssppmode%d[%d %d] fb%d\n",
+ crtc->base.id, pstate->stage,
+ plane->base.id, pstate->num_pipes,
+ dpu_plane_pipe(pstate->pipe_hw[0]) - SSPP_VIG0,
+ dpu_plane_pipe(pstate->pipe_hw[1]) - SSPP_VIG0,
state->fb ? state->fb->base.id : -1);
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
@@ -221,19 +222,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
bg_alpha_enable = true;
DPU_EVT32(DRMID(crtc), DRMID(plane),
- state->fb ? state->fb->base.id : -1,
- state->src_x >> 16, state->src_y >> 16,
- state->src_w >> 16, state->src_h >> 16,
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h);
-
- stage_idx = zpos_cnt[pstate->stage]++;
- stage_cfg->stage[pstate->stage][stage_idx] =
- dpu_plane_pipe(plane);
-
- DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
- dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- format->base.pixel_format, fb ? fb->modifier : 0);
+ state->fb ? state->fb->base.id : -1,
+ state->src_x >> 16, state->src_y >> 16,
+ state->src_w >> 16, state->src_h >> 16,
+ state->crtc_x, state->crtc_y,
+ state->crtc_w, state->crtc_h);
+
+ for (i = 0; i < pstate->num_pipes; i++) {
+ stage_idx = zpos_cnt[pstate->stage]++;
+ if (stage_idx >= PIPES_PER_STAGE)
+ break;
+
+ stage_cfg->stage[pstate->stage][stage_idx] =
+ dpu_plane_pipe(pstate->pipe_hw[i]);
+
+ DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
+ dpu_plane_pipe(pstate->pipe_hw[i]) - SSPP_VIG0,
+ pstate->stage, format->base.pixel_format,
+ fb ? fb->modifier : 0);
+ }
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index be40a2c..2c6960e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -81,40 +81,26 @@ enum dpu_plane_qos {
/*
* struct dpu_plane - local dpu plane structure
- * @aspace: address space pointer
* @csc_ptr: Points to dpu_csc_cfg structure to use for current
- * @catalog: Points to dpu catalog structure
- * @revalidate: force revalidation of all the plane properties
*/
struct dpu_plane {
struct drm_plane base;
struct mutex lock;
- enum dpu_sspp pipe;
- uint32_t features; /* capabilities from catalog */
uint32_t nformats;
uint32_t formats[64];
- struct dpu_hw_pipe *pipe_hw;
- struct dpu_hw_pipe_cfg pipe_cfg;
- struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
uint32_t color_fill;
bool is_error;
- bool is_rt_pipe;
- struct dpu_mdss_cfg *catalog;
+ bool is_rt_client;
struct dpu_csc_cfg *csc_ptr;
-
- const struct dpu_sspp_sub_blks *pipe_sblk;
- char pipe_name[DPU_NAME_SIZE];
+ char name[DPU_NAME_SIZE];
/* debugfs related stuff */
struct dentry *debugfs_root;
- struct dpu_debugfs_regset32 debugfs_src;
- struct dpu_debugfs_regset32 debugfs_scaler;
- struct dpu_debugfs_regset32 debugfs_csc;
- bool debugfs_default_scale;
+
};
#define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
@@ -141,14 +127,46 @@ static bool dpu_plane_sspp_enabled(struct drm_plane_state *state)
return state && state->crtc;
}
+void _dpu_plane_get_roi_config(struct drm_plane_state *state,
+ struct dpu_rect *src, struct dpu_rect *dst)
+{
+ struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ bool q16_data = true;
+ int div = (pstate->num_pipes == PLANE_DUAL_PIPES) ? 2 : 1;
+
+ DPU_DEBUG("plane %d:", state->plane->base.id);
+
+ if (src) {
+ POPULATE_RECT(src, state->src_x, state->src_y,
+ state->src_w, state->src_h, q16_data);
+
+ DPU_DEBUG("src_rect: %u,%u,(%u/%d)x%u\n",
+ src->x, src->y, src->w, div, src->h);
+
+ src->w /= div;
+ }
+
+ if (dst) {
+ POPULATE_RECT(dst, state->crtc_x, state->crtc_y,
+ state->crtc_w, state->crtc_h, !q16_data);
+
+ DPU_DEBUG("dst_rect: %d,%d,(%u/%d)x%u\n",
+ dst->x, dst->y, dst->w, div, dst->h);
+
+ dst->w /= div;
+ }
+}
+
/**
* _dpu_plane_calc_fill_level - calculate fill level of the given source format
* @plane: Pointer to drm plane
+ * @pipe_hw: Pointer to hardware pipe
* @fmt: Pointer to source buffer format
* @src_wdith: width of source buffer
* Return: fill level corresponding to the source buffer/format or 0 if error
*/
static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
+ struct dpu_hw_pipe *pipe_hw,
const struct dpu_format *fmt, u32 src_width)
{
struct dpu_kms *kms;
@@ -179,12 +197,12 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
((src_width + 32) * fmt->bpp);
}
} else {
- total_fl = (fixed_buff_size) * 2 /
+ total_fl = (fixed_buff_size) * 2 /
((src_width + 32) * fmt->bpp);
}
- DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
- plane->base.id, pdpu->pipe - SSPP_VIG0,
+ DPU_DEBUG("plane%d: pnum:%d fmt:%4.4s w:%u fl:%u\n",
+ plane->base.id, pipe_hw->idx - SSPP_VIG0,
(char *)&fmt->base.pixel_format,
src_width, total_fl);
@@ -219,39 +237,38 @@ static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
/**
* _dpu_plane_set_qos_lut - set QoS LUT of the given plane
* @plane: Pointer to drm plane
+ * @pipe_hw: Pointer to hardware pipe
+ * @pipe_cfg: Pointer to hardware pipe config
* @fb: Pointer to framebuffer associated with the given plane
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
- struct drm_framebuffer *fb)
+ struct dpu_hw_pipe *pipe_hw, struct dpu_hw_pipe_cfg *pipe_cfg,
+ struct drm_framebuffer *fb)
{
+ struct dpu_kms *kms;
struct dpu_plane *pdpu;
const struct dpu_format *fmt = NULL;
u64 qos_lut;
u32 total_fl = 0, lut_usage;
+ struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
- if (!plane || !fb) {
- DPU_ERROR("invalid arguments plane %d fb %d\n",
- plane != 0, fb != 0);
+ if (!plane || !pipe_hw || !pipe_cfg || !fb ||
+ !pipe_hw->ops.setup_creq_lut) {
+ DPU_ERROR("invalid arguments plane %d hw %d cfg %d fb %d\n",
+ plane != 0, pipe_hw != 0, pipe_cfg != 0, fb != 0);
return;
}
pdpu = to_dpu_plane(plane);
+ kms = _dpu_plane_get_kms(&pdpu->base);
- if (!pdpu->pipe_hw || !pdpu->pipe_sblk || !pdpu->catalog) {
- DPU_ERROR("invalid arguments\n");
- return;
- } else if (!pdpu->pipe_hw->ops.setup_creq_lut) {
- return;
- }
-
- if (!pdpu->is_rt_pipe) {
+ if (!pdpu->is_rt_client) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
- fmt = dpu_get_dpu_format_ext(
- fb->format->format,
- fb->modifier);
- total_fl = _dpu_plane_calc_fill_level(plane, fmt,
- pdpu->pipe_cfg.src_rect.w);
+ fmt = dpu_get_dpu_format_ext(fb->format->format,
+ fb->modifier);
+ total_fl = _dpu_plane_calc_fill_level(plane, pipe_hw,
+ fmt, pipe_cfg->src_rect.w);
if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
@@ -260,53 +277,52 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
}
qos_lut = _dpu_plane_get_qos_lut(
- &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
+ &kms->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
- pdpu->pipe_qos_cfg.creq_lut = qos_lut;
+ memset(&pipe_qos_cfg, 0, sizeof(struct dpu_hw_pipe_qos_cfg));
+ pipe_qos_cfg.creq_lut = qos_lut;
- trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
- pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
+ trace_dpu_perf_set_qos_luts(pipe_hw->idx - SSPP_VIG0,
+ (fmt) ? fmt->base.pixel_format : 0,
+ pdpu->is_rt_client, total_fl, qos_lut, lut_usage);
DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
- plane->base.id,
- pdpu->pipe - SSPP_VIG0,
- fmt ? (char *)&fmt->base.pixel_format : NULL,
- pdpu->is_rt_pipe, total_fl, qos_lut);
+ plane->base.id, pipe_hw->idx - SSPP_VIG0,
+ fmt ? (char *)&fmt->base.pixel_format : NULL,
+ pdpu->is_rt_client, total_fl, qos_lut);
- pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
+ pipe_hw->ops.setup_creq_lut(pipe_hw, &pipe_qos_cfg);
}
/**
- * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
+ * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
* @plane: Pointer to drm plane
- * @fb: Pointer to framebuffer associated with the given plane
+ * @pipe_hw: Pointer to hardware pipe
+ * @fb: Pointer to framebuffer associated with the given plane
*/
static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
- struct drm_framebuffer *fb)
+ struct dpu_hw_pipe *pipe_hw, struct drm_framebuffer *fb)
{
+ struct dpu_kms *kms;
struct dpu_plane *pdpu;
const struct dpu_format *fmt = NULL;
u32 danger_lut, safe_lut;
+ struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
- if (!plane || !fb) {
- DPU_ERROR("invalid arguments\n");
+ if (!plane || !pipe_hw || !fb ||
+ !pipe_hw->ops.setup_danger_safe_lut) {
+ DPU_ERROR("invalid arguments plane %d hw %d fb %d\n",
+ plane != 0, pipe_hw != 0, fb != 0);
return;
}
pdpu = to_dpu_plane(plane);
+ kms = _dpu_plane_get_kms(&pdpu->base);
- if (!pdpu->pipe_hw || !pdpu->pipe_sblk || !pdpu->catalog) {
- DPU_ERROR("invalid arguments\n");
- return;
- } else if (!pdpu->pipe_hw->ops.setup_danger_safe_lut) {
- return;
- }
-
- if (!pdpu->is_rt_pipe) {
- danger_lut = pdpu->catalog->perf.danger_lut_tbl
+ if (!pdpu->is_rt_client) {
+ danger_lut = kms->catalog->perf.danger_lut_tbl
[DPU_QOS_LUT_USAGE_NRT];
- safe_lut = pdpu->catalog->perf.safe_lut_tbl
+ safe_lut = kms->catalog->perf.safe_lut_tbl
[DPU_QOS_LUT_USAGE_NRT];
} else {
fmt = dpu_get_dpu_format_ext(
@@ -314,105 +330,101 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
fb->modifier);
if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
- danger_lut = pdpu->catalog->perf.danger_lut_tbl
+ danger_lut = kms->catalog->perf.danger_lut_tbl
[DPU_QOS_LUT_USAGE_LINEAR];
- safe_lut = pdpu->catalog->perf.safe_lut_tbl
+ safe_lut = kms->catalog->perf.safe_lut_tbl
[DPU_QOS_LUT_USAGE_LINEAR];
} else {
- danger_lut = pdpu->catalog->perf.danger_lut_tbl
+ danger_lut = kms->catalog->perf.danger_lut_tbl
[DPU_QOS_LUT_USAGE_MACROTILE];
- safe_lut = pdpu->catalog->perf.safe_lut_tbl
+ safe_lut = kms->catalog->perf.safe_lut_tbl
[DPU_QOS_LUT_USAGE_MACROTILE];
}
}
- pdpu->pipe_qos_cfg.danger_lut = danger_lut;
- pdpu->pipe_qos_cfg.safe_lut = safe_lut;
+ memset(&pipe_qos_cfg, 0, sizeof(struct dpu_hw_pipe_qos_cfg));
+ pipe_qos_cfg.danger_lut = danger_lut;
+ pipe_qos_cfg.safe_lut = safe_lut;
- trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
- (fmt) ? fmt->fetch_mode : 0,
- pdpu->pipe_qos_cfg.danger_lut,
- pdpu->pipe_qos_cfg.safe_lut);
+ trace_dpu_perf_set_danger_luts(pipe_hw->idx - SSPP_VIG0,
+ (fmt) ? fmt->base.pixel_format : 0,
+ (fmt) ? fmt->fetch_mode : 0,
+ pipe_qos_cfg.danger_lut, pipe_qos_cfg.safe_lut);
- DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
- plane->base.id,
- pdpu->pipe - SSPP_VIG0,
+ DPU_DEBUG("plane%u:pnum:%d fmt:%4.4s mode:%d luts[0x%x,0x%x]\n",
+ plane->base.id, pipe_hw->idx - SSPP_VIG0,
fmt ? (char *)&fmt->base.pixel_format : NULL,
- fmt ? fmt->fetch_mode : -1,
- pdpu->pipe_qos_cfg.danger_lut,
- pdpu->pipe_qos_cfg.safe_lut);
+ fmt ? fmt->fetch_mode : -1, pipe_qos_cfg.danger_lut,
+ pipe_qos_cfg.safe_lut);
+
+ pipe_hw->ops.setup_danger_safe_lut(pipe_hw, &pipe_qos_cfg);
- pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
- &pdpu->pipe_qos_cfg);
}
/**
* _dpu_plane_set_qos_ctrl - set QoS control of the given plane
* @plane: Pointer to drm plane
+ * @pipe_hw: Pointer to hardware pipe
* @enable: true to enable QoS control
* @flags: QoS control mode (enum dpu_plane_qos)
*/
static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
- bool enable, u32 flags)
+ struct dpu_hw_pipe *pipe_hw, bool enable, u32 flags)
{
struct dpu_plane *pdpu;
+ struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
- if (!plane) {
+ if (!plane || !pipe_hw || !pipe_hw->cap->sblk ||
+ !pipe_hw->ops.setup_qos_ctrl) {
DPU_ERROR("invalid arguments\n");
return;
}
pdpu = to_dpu_plane(plane);
-
- if (!pdpu->pipe_hw || !pdpu->pipe_sblk) {
- DPU_ERROR("invalid arguments\n");
- return;
- } else if (!pdpu->pipe_hw->ops.setup_qos_ctrl) {
- return;
- }
+ memset(&pipe_qos_cfg, 0, sizeof(struct dpu_hw_pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
- pdpu->pipe_qos_cfg.danger_vblank =
- pdpu->pipe_sblk->danger_vblank;
- pdpu->pipe_qos_cfg.vblank_en = enable;
+ pipe_qos_cfg.creq_vblank =
+ pipe_hw->cap->sblk->creq_vblank;
+ pipe_qos_cfg.danger_vblank =
+ pipe_hw->cap->sblk->danger_vblank;
+ pipe_qos_cfg.vblank_en = enable;
}
if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
/* this feature overrules previous VBLANK_CTRL */
- pdpu->pipe_qos_cfg.vblank_en = false;
- pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
+ pipe_qos_cfg.vblank_en = false;
+ /* clear vblank bits */
+ pipe_qos_cfg.creq_vblank = 0;
}
if (flags & DPU_PLANE_QOS_PANIC_CTRL)
- pdpu->pipe_qos_cfg.danger_safe_en = enable;
+ pipe_qos_cfg.danger_safe_en = enable;
- if (!pdpu->is_rt_pipe) {
- pdpu->pipe_qos_cfg.vblank_en = false;
- pdpu->pipe_qos_cfg.danger_safe_en = false;
+ if (!pdpu->is_rt_client) {
+ pipe_qos_cfg.vblank_en = false;
+ pipe_qos_cfg.danger_safe_en = false;
}
- DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
- plane->base.id,
- pdpu->pipe - SSPP_VIG0,
- pdpu->pipe_qos_cfg.danger_safe_en,
- pdpu->pipe_qos_cfg.vblank_en,
- pdpu->pipe_qos_cfg.creq_vblank,
- pdpu->pipe_qos_cfg.danger_vblank,
- pdpu->is_rt_pipe);
+ DPU_DEBUG("plane%u:pnum:%d ds:%d vb:%d pr[0x%x,0x%x]is_rt:%d\n",
+ plane->base.id, pipe_hw->idx - SSPP_VIG0,
+ pipe_qos_cfg.danger_safe_en, pipe_qos_cfg.vblank_en,
+ pipe_qos_cfg.creq_vblank, pipe_qos_cfg.danger_vblank,
+ pdpu->is_rt_client);
+
+ pipe_hw->ops.setup_qos_ctrl(pipe_hw, &pipe_qos_cfg);
- pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
- &pdpu->pipe_qos_cfg);
}
int dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
{
struct dpu_plane *pdpu;
+ struct dpu_plane_state *pstate;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
+ int i;
- if (!plane || !plane->dev) {
+ if (!plane || !plane->dev || !plane->state) {
DPU_ERROR("invalid arguments\n");
return -EINVAL;
}
@@ -425,12 +437,15 @@ int dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
dpu_kms = to_dpu_kms(priv->kms);
pdpu = to_dpu_plane(plane);
+ pstate = to_dpu_plane_state(plane->state);
- if (!pdpu->is_rt_pipe)
+ if (!pdpu->is_rt_client)
goto end;
pm_runtime_get_sync(&dpu_kms->pdev->dev);
- _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
+ for (i = 0; i < pstate->num_pipes; i++)
+ _dpu_plane_set_qos_ctrl(plane, pstate->pipe_hw[i],
+ enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
end:
@@ -440,19 +455,22 @@ int dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
/**
* _dpu_plane_set_ot_limit - set OT limit for the given plane
* @plane: Pointer to drm plane
+ * @pipe_hw: Pointer to hardware pipe
+ * @pipe_cfg: Pointer to hardware pipe config
* @crtc: Pointer to drm crtc
*/
static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
- struct drm_crtc *crtc)
+ struct dpu_hw_pipe *pipe_hw, struct dpu_hw_pipe_cfg *pipe_cfg,
+ struct drm_crtc *crtc)
{
struct dpu_plane *pdpu;
struct dpu_vbif_set_ot_params ot_params;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
- if (!plane || !plane->dev || !crtc) {
- DPU_ERROR("invalid arguments plane %d crtc %d\n",
- plane != 0, crtc != 0);
+ if (!plane || !plane->dev || !pipe_hw || !pipe_cfg || !crtc) {
+ DPU_ERROR("invalid arguments plane %d hw %d cfg %d crtc %d\n",
+ plane != 0, pipe_hw != 0, pipe_cfg != 0, crtc != 0);
return;
}
@@ -463,38 +481,38 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
}
dpu_kms = to_dpu_kms(priv->kms);
+
pdpu = to_dpu_plane(plane);
- if (!pdpu->pipe_hw) {
- DPU_ERROR("invalid pipe reference\n");
- return;
- }
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
- ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
- ot_params.width = pdpu->pipe_cfg.src_rect.w;
- ot_params.height = pdpu->pipe_cfg.src_rect.h;
- ot_params.is_wfd = !pdpu->is_rt_pipe;
+ ot_params.xin_id = pipe_hw->cap->xin_id;
+ ot_params.num = pipe_hw->idx - SSPP_NONE;
+ ot_params.width = pipe_cfg->src_rect.w;
+ ot_params.height = pipe_cfg->src_rect.h;
+ ot_params.is_wfd = !pdpu->is_rt_client;
ot_params.frame_rate = crtc->mode.vrefresh;
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
+ ot_params.clk_ctrl = pipe_hw->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
+
}
/**
* _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
* @plane: Pointer to drm plane
+ * @pipe_hw: Pointer to hardware pipe
*/
-static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
+static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
+ struct dpu_hw_pipe *pipe_hw)
{
struct dpu_plane *pdpu;
struct dpu_vbif_set_qos_params qos_params;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
- if (!plane || !plane->dev) {
+ if (!plane || !plane->dev || !pipe_hw) {
DPU_ERROR("invalid arguments\n");
return;
}
@@ -507,23 +525,17 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
dpu_kms = to_dpu_kms(priv->kms);
pdpu = to_dpu_plane(plane);
- if (!pdpu->pipe_hw) {
- DPU_ERROR("invalid pipe reference\n");
- return;
- }
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
- qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
- qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
- qos_params.is_rt = pdpu->is_rt_pipe;
+ qos_params.clk_ctrl = pipe_hw->cap->clk_ctrl;
+ qos_params.xin_id = pipe_hw->cap->xin_id;
+ qos_params.num = pipe_hw->idx - SSPP_VIG0;
+ qos_params.is_rt = pdpu->is_rt_client;
DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
- plane->base.id, qos_params.num,
- qos_params.vbif_idx,
- qos_params.xin_id, qos_params.is_rt,
- qos_params.clk_ctrl);
+ plane->base.id, qos_params.num, qos_params.vbif_idx,
+ qos_params.xin_id, qos_params.is_rt, qos_params.clk_ctrl);
dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
}
@@ -554,25 +566,16 @@ static int _dpu_plane_get_aspace(
return 0;
}
-static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
- struct dpu_plane_state *pstate,
- struct dpu_hw_pipe_cfg *pipe_cfg,
- struct drm_framebuffer *fb)
+static inline void _dpu_plane_set_scanout(struct dpu_plane *pdpu,
+ struct dpu_plane_state *pstate, struct dpu_hw_pipe *pipe_hw,
+ struct dpu_hw_pipe_cfg *pipe_cfg, struct drm_framebuffer *fb)
{
- struct dpu_plane *pdpu;
struct msm_gem_address_space *aspace = NULL;
int ret;
- if (!plane || !pstate || !pipe_cfg || !fb) {
- DPU_ERROR(
- "invalid arg(s), plane %d state %d cfg %d fb %d\n",
- plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
- return;
- }
-
- pdpu = to_dpu_plane(plane);
- if (!pdpu->pipe_hw) {
- DPU_ERROR_PLANE(pdpu, "invalid pipe_hw\n");
+ if (!pdpu || !pstate || !pipe_hw || !pipe_cfg || !fb) {
+ DPU_ERROR("invalid: plane %d state %d hw %d cfg %d fb %d\n",
+ pdpu != 0, pstate != 0, pipe_hw != 0, pipe_cfg != 0, fb != 0);
return;
}
@@ -587,8 +590,8 @@ static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
else if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
- DPU_EVT32_VERBOSE(pdpu->pipe_hw->idx,
+ else if (pipe_hw->ops.setup_sourceaddress) {
+ DPU_EVT32_VERBOSE(pipe_hw->idx,
pipe_cfg->layout.width,
pipe_cfg->layout.height,
pipe_cfg->layout.plane_addr[0],
@@ -599,11 +602,11 @@ static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
pipe_cfg->layout.plane_size[2],
pipe_cfg->layout.plane_addr[3],
pipe_cfg->layout.plane_size[3]);
- pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg);
+ pipe_hw->ops.setup_sourceaddress(pipe_hw, pipe_cfg);
}
}
-static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
+static void _dpu_plane_setup_scaler3(
struct dpu_plane_state *pstate,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
@@ -612,12 +615,12 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
{
uint32_t i;
- if (!pdpu || !pstate || !scale_cfg || !fmt || !chroma_subsmpl_h ||
- !chroma_subsmpl_v) {
+ if (!pstate || !scale_cfg || !fmt ||
+ !chroma_subsmpl_h || !chroma_subsmpl_v) {
DPU_ERROR(
- "pdpu %d pstate %d scale_cfg %d fmt %d smp_h %d smp_v %d\n",
- !!pdpu, !!pstate, !!scale_cfg, !!fmt, chroma_subsmpl_h,
- chroma_subsmpl_v);
+ "pstate%d scale_cfg%d fmt%d smp_h%d smp_v%d\n",
+ !!pstate, !!scale_cfg, !!fmt, chroma_subsmpl_h,
+ chroma_subsmpl_v);
return;
}
@@ -673,7 +676,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->enable = 1;
}
-static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
+static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu, u32 features)
{
static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
{
@@ -709,7 +712,7 @@ static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
return;
}
- if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & features)
pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
else
pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
@@ -720,16 +723,18 @@ static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
pdpu->csc_ptr->csc_mv[2]);
}
-static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
+
+static void _dpu_plane_setup_scaler(
struct dpu_plane_state *pstate,
+ struct dpu_hw_pipe_cfg *pipe_cfg,
const struct dpu_format *fmt, bool color_fill)
{
struct dpu_hw_pixel_ext *pe;
uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
- if (!pdpu || !fmt || !pstate) {
- DPU_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
- pdpu != 0, fmt != 0, pstate != 0);
+ if (!fmt || !pstate) {
+ DPU_ERROR("invalid arg(s), fmt %d state %d\n",
+ fmt != 0, pstate != 0);
return;
}
@@ -742,11 +747,11 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
/* update scaler. calculate default config for QSEED3 */
- _dpu_plane_setup_scaler3(pdpu, pstate,
- pdpu->pipe_cfg.src_rect.w,
- pdpu->pipe_cfg.src_rect.h,
- pdpu->pipe_cfg.dst_rect.w,
- pdpu->pipe_cfg.dst_rect.h,
+ _dpu_plane_setup_scaler3(pstate,
+ pipe_cfg->src_rect.w,
+ pipe_cfg->src_rect.h,
+ pipe_cfg->dst_rect.w,
+ pipe_cfg->dst_rect.h,
&pstate->scaler3_cfg, fmt,
chroma_subsmpl_h, chroma_subsmpl_v);
}
@@ -764,17 +769,14 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
const struct dpu_format *fmt;
const struct drm_plane *plane;
struct dpu_plane_state *pstate;
+ struct dpu_hw_pipe_cfg pipe_cfg;
+ int i;
if (!pdpu || !pdpu->base.state) {
DPU_ERROR("invalid plane\n");
return -EINVAL;
}
- if (!pdpu->pipe_hw) {
- DPU_ERROR_PLANE(pdpu, "invalid plane h/w pointer\n");
- return -EINVAL;
- }
-
plane = &pdpu->base;
pstate = to_dpu_plane_state(plane->state);
@@ -786,34 +788,49 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
*/
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
- /* update sspp */
- if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
- pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
-
- /* override scaler/decimation if solid fill */
- pdpu->pipe_cfg.src_rect.x = 0;
- pdpu->pipe_cfg.src_rect.y = 0;
- pdpu->pipe_cfg.src_rect.w = pdpu->pipe_cfg.dst_rect.w;
- pdpu->pipe_cfg.src_rect.h = pdpu->pipe_cfg.dst_rect.h;
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
+ memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
- if (pdpu->pipe_hw->ops.setup_format)
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
- fmt, DPU_SSPP_SOLID_FILL);
+ _dpu_plane_get_roi_config(plane->state, NULL, &pipe_cfg.dst_rect);
- if (pdpu->pipe_hw->ops.setup_rects)
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
- &pdpu->pipe_cfg);
-
- if (pdpu->pipe_hw->ops.setup_pe)
- pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
- &pstate->pixel_ext);
+ /* update sspp */
+ for (i = 0; i < pstate->num_pipes; i++) {
+ if (fmt && pstate->pipe_hw[i] &&
+ pstate->pipe_hw[i]->ops.setup_solidfill) {
+ pstate->pipe_hw[i]->ops.setup_solidfill(
+ pstate->pipe_hw[i],
+ (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
- if (pdpu->pipe_hw->ops.setup_scaler)
- pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
- &pdpu->pipe_cfg, &pstate->pixel_ext,
+ /*
+ * override scaler/decimation if solid fill
+ * also, adjust the dst.x in case of dual pipe
+ */
+ pipe_cfg.dst_rect.x += pipe_cfg.dst_rect.w * i;
+ pipe_cfg.src_rect.x = 0;
+ pipe_cfg.src_rect.y = 0;
+ pipe_cfg.src_rect.w = pipe_cfg.dst_rect.w;
+ pipe_cfg.src_rect.h = pipe_cfg.dst_rect.h;
+
+ _dpu_plane_setup_scaler(pstate, &pipe_cfg, fmt, true);
+
+ if (pstate->pipe_hw[i]->ops.setup_format)
+ pstate->pipe_hw[i]->ops.setup_format(
+ pstate->pipe_hw[i], fmt,
+ DPU_SSPP_SOLID_FILL);
+
+ if (pstate->pipe_hw[i]->ops.setup_rects)
+ pstate->pipe_hw[i]->ops.setup_rects(
+ pstate->pipe_hw[i], &pipe_cfg);
+
+ if (pstate->pipe_hw[i]->ops.setup_pe)
+ pstate->pipe_hw[i]->ops.setup_pe(
+ pstate->pipe_hw[i], &pstate->pixel_ext);
+
+ if (pstate->pipe_hw[i]->ops.setup_scaler)
+ pstate->pipe_hw[i]->ops.setup_scaler(
+ pstate->pipe_hw[i], &pipe_cfg,
+ &pstate->pixel_ext,
&pstate->scaler3_cfg);
+ }
}
return 0;
@@ -829,6 +846,7 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
u32 *flush_sspp)
{
struct dpu_plane_state *pstate;
+ int i;
if (!plane || !flush_sspp) {
DPU_ERROR("invalid parameters\n");
@@ -837,7 +855,10 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
pstate = to_dpu_plane_state(plane->state);
- *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
+ for (i = 0; i < pstate->num_pipes; i++)
+ *flush_sspp |= ctl->ops.get_bitmask_sspp(ctl,
+ dpu_plane_pipe(pstate->pipe_hw[i]));
+
}
static int dpu_plane_prepare_fb(struct drm_plane *plane,
@@ -921,11 +942,12 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
struct dpu_kms *kms;
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
+ struct dpu_private_state *dpu_priv_state;
const struct dpu_format *fmt;
struct dpu_rect src, dst;
uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
bool q16_data = true;
- uint32_t caps = 0;
+ uint32_t caps = 0, req_num_pipes = 0;
if (!plane || !state) {
DPU_ERROR("invalid arg(s), plane %d state %d\n",
@@ -950,7 +972,20 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
dpu_plane_enabled(plane->state), dpu_plane_enabled(state));
if (!dpu_plane_enabled(state))
+ goto modeset_update;
+
+ /* With plane virtualization, a drm plane can be attached
+ * to maximum of two hw pipes, i.e. we can go up to 2x
+ * the pipe's max width.
+ */
+ if (src.w > 2 * max_linewidth) {
+ DPU_ERROR_PLANE(pdpu, "invalid src w:%u, line w * 2:%u\n",
+ src.w, max_linewidth * 2);
+ ret = -E2BIG;
goto exit;
+ }
+
+ req_num_pipes = (src.w > max_linewidth) ? 2 : 1;
fmt = to_dpu_format(msm_framebuffer_format(state->fb));
@@ -988,13 +1023,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
dst.x, dst.y, dst.w, dst.h);
ret = -EINVAL;
- /* check decimated source width */
- } else if (src.w > max_linewidth) {
- DPU_ERROR_PLANE(pdpu,
- "invalid src w:%u, line w:%u\n",
- src.w, max_linewidth);
- ret = -E2BIG;
-
/* check max scaler capability */
} else if (((src.w * max_upscale) < dst.w) ||
((src.h * max_upscale) < dst.h) ||
@@ -1006,6 +1034,44 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
ret = -E2BIG;
}
+modeset_update:
+ if (!ret) {
+ dpu_priv_state = dpu_get_private_state(state->state);
+ if (IS_ERR(dpu_priv_state))
+ goto exit;
+
+ /**
+ * (re)allocate hw pipes if mismatch in number of pipes
+ * or caps of allocated vs requested.
+ */
+ DPU_DEBUG_PLANE(pdpu, " num pipes %d -> %d caps %d\n",
+ pstate->num_pipes, req_num_pipes, caps);
+
+ if ((pstate->num_pipes != req_num_pipes) || (pstate->pipe_hw[0]
+ && (caps & ~pstate->pipe_hw[0]->cap->features))) {
+ /**
+ * Release called only for planes with pipes attached.
+ * New plane will have no resources to be released.
+ */
+ if (pstate->num_pipes)
+ dpu_rm_release_plane_res(&dpu_priv_state->rm,
+ pstate);
+
+ /**
+ * Reserve called only for planes that are enabled.
+ * Plane that is disabling will require no resources.
+ */
+ if (req_num_pipes) {
+ ret = dpu_rm_reserve_plane_res(
+ &dpu_priv_state->rm, pstate,
+ req_num_pipes, caps);
+ if (ret)
+ DPU_ERROR_PLANE(pdpu,
+ "failed to reserve resources\n");
+ }
+ }
+ }
+
exit:
return ret;
}
@@ -1039,6 +1105,7 @@ void dpu_plane_flush(struct drm_plane *plane)
{
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
+ int i;
if (!plane || !plane->state) {
DPU_ERROR("invalid plane\n");
@@ -1058,8 +1125,14 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
- pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
+ else {
+ for (i = 0; i < pstate->num_pipes; i++) {
+ if (pstate->pipe_hw[i] && pdpu->csc_ptr &&
+ pstate->pipe_hw[i]->ops.setup_csc)
+ pstate->pipe_hw[i]->ops.setup_csc(
+ pstate->pipe_hw[i], pdpu->csc_ptr);
+ }
+ }
/* force black color fill during suspend */
if (dpu_kms_is_suspend_state(plane->dev) && suspend_blank)
@@ -1089,6 +1162,7 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
uint32_t nplanes, src_flags;
+ struct dpu_kms *kms;
struct dpu_plane *pdpu;
struct drm_plane_state *state;
struct dpu_plane_state *pstate;
@@ -1097,7 +1171,8 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
struct drm_crtc *crtc;
struct drm_framebuffer *fb;
struct dpu_rect src, dst;
- bool q16_data = true;
+ struct dpu_hw_pipe_cfg pipe_cfg;
+ int i;
if (!plane) {
DPU_ERROR("invalid plane\n");
@@ -1124,96 +1199,115 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
crtc != 0, fb != 0);
return -EINVAL;
}
+
+ kms = _dpu_plane_get_kms(&pdpu->base);
+ if (!kms || !kms->catalog) {
+ DPU_ERROR("invalid kms catalog\n");
+ return -EINVAL;
+ }
+
fmt = to_dpu_format(msm_framebuffer_format(fb));
nplanes = fmt->num_planes;
- memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
-
- _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
+ DPU_DEBUG_PLANE(pdpu, "%4.4s ubwc %d\n",
+ (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
pstate->pending = true;
+ pdpu->is_rt_client = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
- pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_get_roi_config(state, &src, &dst);
- /* update roi config */
- POPULATE_RECT(&src, state->src_x, state->src_y,
- state->src_w, state->src_h, q16_data);
- POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h, !q16_data);
+ for (i = 0; i < pstate->num_pipes; i++) {
+ memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
- DPU_DEBUG_PLANE(pdpu,
- "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
- fb->base.id, src.x, src.y, src.w, src.h,
- crtc->base.id, dst.x, dst.y, dst.w, dst.h,
- (char *)&fmt->base.pixel_format,
- DPU_FORMAT_IS_UBWC(fmt));
+ _dpu_plane_set_scanout(pdpu, pstate, pstate->pipe_hw[i],
+ &pipe_cfg, fb);
+ _dpu_plane_set_qos_ctrl(plane, pstate->pipe_hw[i],
+ false, DPU_PLANE_QOS_PANIC_CTRL);
+ /*
+ * if the plane comprises of 2 hw pipes, assume that the width
+ * is split equally across them. The only parameters that varies
+ * between the 2 pipes are src_x and dst_x
+ */
+ src.x += src.w * i;
+ dst.x += dst.w * i;
- pdpu->pipe_cfg.src_rect = src;
- pdpu->pipe_cfg.dst_rect = dst;
+ pipe_cfg.src_rect = src;
+ pipe_cfg.dst_rect = dst;
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
+ _dpu_plane_setup_scaler(pstate, &pipe_cfg, fmt, false);
- /* override for color fill */
- if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
- /* skip remaining processing on color fill */
- return 0;
- }
+ /* override for color fill */
+ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
+ /* skip remaining processing on color fill */
+ return 0;
+ }
- if (pdpu->pipe_hw->ops.setup_rects) {
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
- &pdpu->pipe_cfg);
- }
+ if (pstate->pipe_hw[i]->ops.setup_rects) {
+ pstate->pipe_hw[i]->ops.setup_rects(pstate->pipe_hw[i],
+ &pipe_cfg);
+ }
- if (pdpu->pipe_hw->ops.setup_pe)
- pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
- &pstate->pixel_ext);
+ if (pstate->pipe_hw[i]->ops.setup_pe)
+ pstate->pipe_hw[i]->ops.setup_pe(pstate->pipe_hw[i],
+ &pstate->pixel_ext);
- if (pdpu->pipe_hw->ops.setup_scaler)
- pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
- &pdpu->pipe_cfg, &pstate->pixel_ext,
- &pstate->scaler3_cfg);
+ if (pstate->pipe_hw[i]->ops.setup_scaler)
+ pstate->pipe_hw[i]->ops.setup_scaler(pstate->pipe_hw[i],
+ &pipe_cfg, &pstate->pixel_ext,
+ &pstate->scaler3_cfg);
- if (pdpu->pipe_hw->ops.setup_format) {
- src_flags = 0x0;
+ if (pstate->pipe_hw[i]->ops.setup_format) {
+ src_flags = 0x0;
- /* update format */
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags);
+ /* update format */
+ pstate->pipe_hw[i]->ops.setup_format(
+ pstate->pipe_hw[i], fmt, src_flags);
- if (pdpu->pipe_hw->ops.setup_cdp) {
- struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
+ if (pstate->pipe_hw[i]->ops.setup_cdp) {
+ struct dpu_hw_pipe_cdp_cfg *cdp_cfg =
+ &pstate->cdp_cfg;
- memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
+ memset(cdp_cfg, 0,
+ sizeof(struct dpu_hw_pipe_cdp_cfg));
- cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
+ cdp_cfg->enable = kms->catalog->perf.cdp_cfg
[DPU_PERF_CDP_USAGE_RT].rd_enable;
- cdp_cfg->ubwc_meta_enable =
+ cdp_cfg->ubwc_meta_enable =
DPU_FORMAT_IS_UBWC(fmt);
- cdp_cfg->tile_amortize_enable =
+ cdp_cfg->tile_amortize_enable =
DPU_FORMAT_IS_UBWC(fmt) ||
DPU_FORMAT_IS_TILE(fmt);
- cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
-
- pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
+ cdp_cfg->preload_ahead =
+ DPU_SSPP_CDP_PRELOAD_AHEAD_64;
+
+ pstate->pipe_hw[i]->ops.setup_cdp(
+ pstate->pipe_hw[i], cdp_cfg);
+ }
+
+ /* update csc */
+ if (DPU_FORMAT_IS_YUV(fmt))
+ _dpu_plane_setup_csc(pdpu,
+ pstate->pipe_hw[i]->cap->features);
+ else
+ pdpu->csc_ptr = 0;
}
- /* update csc */
- if (DPU_FORMAT_IS_YUV(fmt))
- _dpu_plane_setup_csc(pdpu);
- else
- pdpu->csc_ptr = 0;
- }
+ _dpu_plane_set_qos_lut(plane, pstate->pipe_hw[i],
+ &pipe_cfg, fb);
+ _dpu_plane_set_danger_lut(plane, pstate->pipe_hw[i], fb);
- _dpu_plane_set_qos_lut(plane, fb);
- _dpu_plane_set_danger_lut(plane, fb);
+ if (plane->type != DRM_PLANE_TYPE_CURSOR) {
+ _dpu_plane_set_qos_ctrl(plane, pstate->pipe_hw[i],
+ true, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_ot_limit(plane, pstate->pipe_hw[i],
+ &pipe_cfg, crtc);
+ }
- if (plane->type != DRM_PLANE_TYPE_CURSOR) {
- _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, crtc);
+ _dpu_plane_set_qos_remap(plane, pstate->pipe_hw[i]);
}
- _dpu_plane_set_qos_remap(plane);
return 0;
}
@@ -1270,11 +1364,19 @@ void dpu_plane_restore(struct drm_plane *plane)
static void dpu_plane_destroy(struct drm_plane *plane)
{
struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
+ struct dpu_plane_state *pstate;
+ int i;
DPU_DEBUG_PLANE(pdpu, "\n");
if (pdpu) {
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
+ pstate = plane->state ? to_dpu_plane_state(plane->state) : NULL;
+ if (pstate) {
+ for (i = 0; i < pstate->num_pipes; i++)
+ _dpu_plane_set_qos_ctrl(plane,
+ pstate->pipe_hw[i], false,
+ DPU_PLANE_QOS_PANIC_CTRL);
+ }
mutex_destroy(&pdpu->lock);
@@ -1484,7 +1586,7 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
/* create overall sub-directory for the pipe */
pdpu->debugfs_root =
- debugfs_create_dir(pdpu->pipe_name,
+ debugfs_create_dir(pdpu->name,
plane->dev->primary->debugfs_root);
if (!pdpu->debugfs_root)
@@ -1546,9 +1648,9 @@ static void dpu_plane_early_unregister(struct drm_plane *plane)
.atomic_update = dpu_plane_atomic_update,
};
-enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
+enum dpu_sspp dpu_plane_pipe(struct dpu_hw_pipe *pipe_hw)
{
- return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
+ return pipe_hw ? pipe_hw->idx : SSPP_NONE;
}
/* initialize plane */
@@ -1578,8 +1680,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
DPU_ERROR("[%u]invalid KMS reference\n", pipe);
goto exit;
}
- kms = to_dpu_kms(priv->kms);
+ kms = to_dpu_kms(priv->kms);
if (!kms->catalog) {
DPU_ERROR("[%u]invalid catalog reference\n", pipe);
goto exit;
@@ -1625,11 +1727,11 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
/* save user friendly pipe name for later */
- snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
+ snprintf(pdpu->name, DPU_NAME_SIZE, "plane%u", plane->base.id);
mutex_init(&pdpu->lock);
- DPU_DEBUG("%s created for pipe:%u id:%u\n", pdpu->pipe_name,
+ DPU_DEBUG("%s created for pipe:%u id:%u\n", pdpu->name,
pipe, plane->base.id);
return plane;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 4eb929b..3ebc4c1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -71,10 +71,10 @@ struct dpu_plane_state {
/**
* dpu_plane_pipe - return sspp identifier for the given plane
- * @plane: Pointer to DRM plane object
+ * @pipe_hw: Pointer to DPU pipe hw
* Returns: sspp identifier of the given plane
*/
-enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane);
+enum dpu_sspp dpu_plane_pipe(struct dpu_hw_pipe *pipe_hw);
/**
* dpu_plane_get_ctl_flush - get control flush mask
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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