Re: [PATCH 2/3] arm64: dts: qcom: sm8550: Enable UHS-I SDR50 and SDR104 SD card modes

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 11/27/25 3:27 PM, Vladimir Zapolskiy wrote:
> Hi Konrad.
> 
> On 11/27/25 15:40, Konrad Dybcio wrote:
>> On 11/26/25 2:20 AM, Vladimir Zapolskiy wrote:
>>> The restriction on UHS-I speed modes was added to all SM8550 platforms
>>> by copying it from SM8450 dtsi file, and due to the overclocking of SD
>>> cards it was an actually reproducible problem. Since the latter issue
>>> has been fixed, UHS-I speed modes are working fine on SM8550 boards,
>>> below is the test performed on SM8550-HDK:
>>>
>>> SDR50 speed mode:
>>>
>>>      mmc0: new UHS-I speed SDR50 SDHC card at address 0001
>>>      mmcblk0: mmc0:0001 00000 14.6 GiB
>>>       mmcblk0: p1
>>>
>>>      % dd if=/dev/mmcblk0p1 of=/dev/null bs=1M count=1024
>>>      1024+0 records in
>>>      1024+0 records out
>>>      1073741824 bytes (1.1 GB, 1.0 GiB) copied, 23.5468 s, 45.6 MB/s
>>>
>>> SDR104 speed mode:
>>>
>>>      mmc0: new UHS-I speed SDR104 SDHC card at address 59b4
>>>      mmcblk0: mmc0:59b4 USDU1 28.3 GiB
>>>       mmcblk0: p1
>>>
>>>      % dd if=/dev/mmcblk0p1 of=/dev/null bs=1M count=1024
>>>      1024+0 records in
>>>      1024+0 records out
>>>      1073741824 bytes (1.1 GB, 1.0 GiB) copied, 11.9819 s, 89.6 MB/s
>>>
>>> Unset the UHS-I speed mode restrictions from the SM8550 platform dtsi
>>> file, there is no indication that the SDHC controller is broken.
>>>
>>> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>>> ---
>>
>> 8550 has additional limitations. One was addressed recently with
>> max-sd-hs-hz (HS mode can only run at 37.5 MHz), but when in SDR104,
>> the frequency must also be capped to 148 MHz. I don't know whether
>> the driver respects that today.
>>
> 
> This frequency cap tuning for SDR104 speed mode is not done. If I
> remember the story properly, the frequency cap for HS speed mode was
> implemented in dts instead of being a pure Qualcomm SDHC specific
> quirk, because it's possible to workaround the limitation by slightly
> changing a board PCB layout. Then should this new SDR104 quirk be
> considered due to a property in the dtb as well?

I think so.

> FWIW, comparing register dumps SD host controllers on SM8550 and SM8650
> SoCs are identical, should HS and SDR104 quirks be ported to SM8650 also?

A document says that in 8650 and 8750 (and hamoa) and newer, these issues
are not present, however the original author added the same limitation to
sm8750:

https://lore.kernel.org/linux-arm-msm/20251026111746.3195861-3-sarthak.garg@oss.qualcomm.com/

+Sarthak could you please remind us why it'd be necessary on !8550?

Konrad