* [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
@ 2025-10-31 10:02 Taniya Das
2025-10-31 10:14 ` Abel Vesa
2025-11-02 18:09 ` Bjorn Andersson
0 siblings, 2 replies; 4+ messages in thread
From: Taniya Das @ 2025-10-31 10:02 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Abel Vesa,
Dmitry Baryshkov
Cc: Rajendra Nayak, Ajit Pandey, Imran Shaik, Jagadeesh Kona,
linux-arm-msm, linux-clk, linux-kernel, Taniya Das
Update the register offsets for all the clock ref branches to match the
new address mapping in the TCSR subsystem.
Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
drivers/clk/qcom/tcsrcc-glymur.c | 54 ++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
index c1f8b6d10b7fd6eaef0149843594fc7eb6a620ec..215bc2ac548da83aec23921ef9a4bd59b6b307bc 100644
--- a/drivers/clk/qcom/tcsrcc-glymur.c
+++ b/drivers/clk/qcom/tcsrcc-glymur.c
@@ -28,10 +28,10 @@ enum {
};
static struct clk_branch tcsr_edp_clkref_en = {
- .halt_reg = 0x1c,
+ .halt_reg = 0x60,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x1c,
+ .enable_reg = 0x60,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
@@ -45,10 +45,10 @@ static struct clk_branch tcsr_edp_clkref_en = {
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
- .halt_reg = 0x4,
+ .halt_reg = 0x48,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x4,
+ .enable_reg = 0x48,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_1_clkref_en",
@@ -62,10 +62,10 @@ static struct clk_branch tcsr_pcie_1_clkref_en = {
};
static struct clk_branch tcsr_pcie_2_clkref_en = {
- .halt_reg = 0x8,
+ .halt_reg = 0x4c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x8,
+ .enable_reg = 0x4c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_2_clkref_en",
@@ -79,10 +79,10 @@ static struct clk_branch tcsr_pcie_2_clkref_en = {
};
static struct clk_branch tcsr_pcie_3_clkref_en = {
- .halt_reg = 0x10,
+ .halt_reg = 0x54,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x10,
+ .enable_reg = 0x54,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_3_clkref_en",
@@ -96,10 +96,10 @@ static struct clk_branch tcsr_pcie_3_clkref_en = {
};
static struct clk_branch tcsr_pcie_4_clkref_en = {
- .halt_reg = 0x14,
+ .halt_reg = 0x58,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x14,
+ .enable_reg = 0x58,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_4_clkref_en",
@@ -113,10 +113,10 @@ static struct clk_branch tcsr_pcie_4_clkref_en = {
};
static struct clk_branch tcsr_usb2_1_clkref_en = {
- .halt_reg = 0x28,
+ .halt_reg = 0x6c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x28,
+ .enable_reg = 0x6c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_1_clkref_en",
@@ -130,10 +130,10 @@ static struct clk_branch tcsr_usb2_1_clkref_en = {
};
static struct clk_branch tcsr_usb2_2_clkref_en = {
- .halt_reg = 0x2c,
+ .halt_reg = 0x70,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x2c,
+ .enable_reg = 0x70,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_2_clkref_en",
@@ -147,10 +147,10 @@ static struct clk_branch tcsr_usb2_2_clkref_en = {
};
static struct clk_branch tcsr_usb2_3_clkref_en = {
- .halt_reg = 0x30,
+ .halt_reg = 0x74,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x30,
+ .enable_reg = 0x74,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_3_clkref_en",
@@ -164,10 +164,10 @@ static struct clk_branch tcsr_usb2_3_clkref_en = {
};
static struct clk_branch tcsr_usb2_4_clkref_en = {
- .halt_reg = 0x44,
+ .halt_reg = 0x88,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x44,
+ .enable_reg = 0x88,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_4_clkref_en",
@@ -181,10 +181,10 @@ static struct clk_branch tcsr_usb2_4_clkref_en = {
};
static struct clk_branch tcsr_usb3_0_clkref_en = {
- .halt_reg = 0x20,
+ .halt_reg = 0x64,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x20,
+ .enable_reg = 0x64,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_0_clkref_en",
@@ -198,10 +198,10 @@ static struct clk_branch tcsr_usb3_0_clkref_en = {
};
static struct clk_branch tcsr_usb3_1_clkref_en = {
- .halt_reg = 0x24,
+ .halt_reg = 0x68,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x24,
+ .enable_reg = 0x68,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_1_clkref_en",
@@ -215,10 +215,10 @@ static struct clk_branch tcsr_usb3_1_clkref_en = {
};
static struct clk_branch tcsr_usb4_1_clkref_en = {
- .halt_reg = 0x0,
+ .halt_reg = 0x44,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x0,
+ .enable_reg = 0x44,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_1_clkref_en",
@@ -232,10 +232,10 @@ static struct clk_branch tcsr_usb4_1_clkref_en = {
};
static struct clk_branch tcsr_usb4_2_clkref_en = {
- .halt_reg = 0x18,
+ .halt_reg = 0x5c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x18,
+ .enable_reg = 0x5c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_2_clkref_en",
@@ -268,7 +268,7 @@ static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
- .max_register = 0x44,
+ .max_register = 0x94,
.fast_io = true,
};
---
base-commit: 131f3d9446a6075192cdd91f197989d98302faa6
change-id: 20251030-tcsrcc_glymur-dd081857db46
Best regards,
--
Taniya Das <taniya.das@oss.qualcomm.com>
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
2025-10-31 10:02 [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs Taniya Das
@ 2025-10-31 10:14 ` Abel Vesa
2025-10-31 10:29 ` Jagadeesh Kona
2025-11-02 18:09 ` Bjorn Andersson
1 sibling, 1 reply; 4+ messages in thread
From: Abel Vesa @ 2025-10-31 10:14 UTC (permalink / raw)
To: Taniya Das
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd,
Dmitry Baryshkov, Rajendra Nayak, Ajit Pandey, Imran Shaik,
Jagadeesh Kona, linux-arm-msm, linux-clk, linux-kernel
On 25-10-31 15:32:25, Taniya Das wrote:
> Update the register offsets for all the clock ref branches to match the
> new address mapping in the TCSR subsystem.
>
> Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
2025-10-31 10:14 ` Abel Vesa
@ 2025-10-31 10:29 ` Jagadeesh Kona
0 siblings, 0 replies; 4+ messages in thread
From: Jagadeesh Kona @ 2025-10-31 10:29 UTC (permalink / raw)
To: Abel Vesa, Taniya Das
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd,
Dmitry Baryshkov, Rajendra Nayak, Ajit Pandey, Imran Shaik,
linux-arm-msm, linux-clk, linux-kernel
On 10/31/2025 3:44 PM, Abel Vesa wrote:
> On 25-10-31 15:32:25, Taniya Das wrote:
>> Update the register offsets for all the clock ref branches to match the
>> new address mapping in the TCSR subsystem.
>>
>> Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>
> Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
2025-10-31 10:02 [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs Taniya Das
2025-10-31 10:14 ` Abel Vesa
@ 2025-11-02 18:09 ` Bjorn Andersson
1 sibling, 0 replies; 4+ messages in thread
From: Bjorn Andersson @ 2025-11-02 18:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Abel Vesa, Dmitry Baryshkov,
Taniya Das
Cc: Rajendra Nayak, Ajit Pandey, Imran Shaik, Jagadeesh Kona,
linux-arm-msm, linux-clk, linux-kernel
On Fri, 31 Oct 2025 15:32:25 +0530, Taniya Das wrote:
> Update the register offsets for all the clock ref branches to match the
> new address mapping in the TCSR subsystem.
>
>
Applied, thanks!
[1/1] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
commit: a4aa1ceb89f5c0d27a55671d88699cf5eae7331b
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2025-10-31 10:02 [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs Taniya Das
2025-10-31 10:14 ` Abel Vesa
2025-10-31 10:29 ` Jagadeesh Kona
2025-11-02 18:09 ` Bjorn Andersson
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