Re: [PATCH v3 2/4] dt-bindings: clock: update interconnect cells for ipq5424

[Manikanta Mylavarapu <quic_mmanikan@quicinc.com>]

On 1/27/2025 12:57 PM, Krzysztof Kozlowski wrote:
> On Sat, Jan 25, 2025 at 09:29:18AM +0530, Manikanta Mylavarapu wrote:
>> Interconnect cells differ between the IPQ5332 and IPQ5424.
>> Therefore, update the interconnect cells according to the SoC.
> 
> Why do they differ? Why they cannot be the same?
> 

Based on the comment received here [1], i updated interconnect cells to 2
to accommodate icc tags for IPQ5424.

[1]: https://lore.kernel.org/linux-arm-msm/20250119124551.nl5272bz36ozvlqu@thinkpad/

I will update interconnect cells to 2 for IPQ5332 as well.

>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>> ---
>>  .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml       | 8 ++++++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> index 1230183fc0a9..fac7922d2473 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> @@ -35,8 +35,6 @@ properties:
>>        - description: PCIE 2-lane PHY3 pipe clock source
>>  
>>    '#power-domain-cells': false
>> -  '#interconnect-cells':
>> -    const: 1
> 
> Properties are always defined top-level or in other schema.

I will define it in top-level and initialize with 2.

Thanks & Regards,
Manikanta.