* [PATCH] ARM: dts: aspeed-g4: Add all flash chips
@ 2019-09-05 0:02 Joel Stanley
2019-09-05 0:33 ` Andrew Jeffery
2019-09-05 6:43 ` Cédric Le Goater
0 siblings, 2 replies; 4+ messages in thread
From: Joel Stanley @ 2019-09-05 0:02 UTC (permalink / raw)
To: linux-aspeed
The FMC supports five chip selects, so describe the five possible flash
chips.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index e465cda40fe7..dffb595d30e4 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -67,6 +67,26 @@
compatible = "jedec,spi-nor";
status = "disabled";
};
+ flash at 1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 3 {
+ reg = < 3 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 4 {
+ reg = < 4 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
};
spi: spi at 1e630000 {
--
2.23.0.rc1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH] ARM: dts: aspeed-g4: Add all flash chips
2019-09-05 0:02 [PATCH] ARM: dts: aspeed-g4: Add all flash chips Joel Stanley
@ 2019-09-05 0:33 ` Andrew Jeffery
2019-09-05 6:45 ` Cédric Le Goater
2019-09-05 6:43 ` Cédric Le Goater
1 sibling, 1 reply; 4+ messages in thread
From: Andrew Jeffery @ 2019-09-05 0:33 UTC (permalink / raw)
To: linux-aspeed
On Thu, 5 Sep 2019, at 09:32, Joel Stanley wrote:
> The FMC supports five chip selects, so describe the five possible flash
> chips.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index e465cda40fe7..dffb595d30e4 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -67,6 +67,26 @@
> compatible = "jedec,spi-nor";
> status = "disabled";
> };
> + flash at 1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash at 2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash at 3 {
> + reg = < 3 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash at 4 {
> + reg = < 4 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
The FMC supports parallel NOR and NAND interfaces too, but so far no-one has
cared for these options, so if they ever do we'll fix it then.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH] ARM: dts: aspeed-g4: Add all flash chips
2019-09-05 0:33 ` Andrew Jeffery
@ 2019-09-05 6:45 ` Cédric Le Goater
0 siblings, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2019-09-05 6:45 UTC (permalink / raw)
To: linux-aspeed
On 05/09/2019 02:33, Andrew Jeffery wrote:
>
>
> On Thu, 5 Sep 2019, at 09:32, Joel Stanley wrote:
>> The FMC supports five chip selects, so describe the five possible flash
>> chips.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> ---
>> arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>> index e465cda40fe7..dffb595d30e4 100644
>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>> @@ -67,6 +67,26 @@
>> compatible = "jedec,spi-nor";
>> status = "disabled";
>> };
>> + flash at 1 {
>> + reg = < 1 >;
>> + compatible = "jedec,spi-nor";
>> + status = "disabled";
>> + };
>> + flash at 2 {
>> + reg = < 2 >;
>> + compatible = "jedec,spi-nor";
>> + status = "disabled";
>> + };
>> + flash at 3 {
>> + reg = < 3 >;
>> + compatible = "jedec,spi-nor";
>> + status = "disabled";
>> + };
>> + flash at 4 {
>> + reg = < 4 >;
>> + compatible = "jedec,spi-nor";
>> + status = "disabled";
>> + };
>
> The FMC supports parallel NOR and NAND interfaces too, but so far no-one has
> cared for these options, so if they ever do we'll fix it then.
New Aspeed SoCs only have SPI support. So I don't think the other interfaces
were ever used.
C.
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM: dts: aspeed-g4: Add all flash chips
2019-09-05 0:02 [PATCH] ARM: dts: aspeed-g4: Add all flash chips Joel Stanley
2019-09-05 0:33 ` Andrew Jeffery
@ 2019-09-05 6:43 ` Cédric Le Goater
1 sibling, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2019-09-05 6:43 UTC (permalink / raw)
To: linux-aspeed
On 05/09/2019 02:02, Joel Stanley wrote:
> The FMC supports five chip selects, so describe the five possible flash
> chips.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: C?dric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index e465cda40fe7..dffb595d30e4 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -67,6 +67,26 @@
> compatible = "jedec,spi-nor";
> status = "disabled";
> };
> + flash at 1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash at 2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash at 3 {
> + reg = < 3 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash at 4 {
> + reg = < 4 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> };
>
> spi: spi at 1e630000 {
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-09-05 0:02 [PATCH] ARM: dts: aspeed-g4: Add all flash chips Joel Stanley
2019-09-05 0:33 ` Andrew Jeffery
2019-09-05 6:45 ` Cédric Le Goater
2019-09-05 6:43 ` Cédric Le Goater
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