* [PATCH i2c-next v2 1/2] dt-bindings: i2c: aspeed: Add 'idle-wait-timeout-ms' property
From: Jae Hyun Yoo @ 2018-09-24 23:04 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180924230442.7732-1-jae.hyun.yoo@linux.intel.com>
This commit adds 'idle-wait-timeout-ms' property which can be used
for bus idle waiting logic in multi-master environment.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
Documentation/devicetree/bindings/i2c/i2c-aspeed.txt | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
index 8fbd8633a387..42ecaaf67172 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
@@ -13,9 +13,13 @@ Required Properties:
- interrupts : interrupt number
Optional Properties:
-- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
- specified
-- multi-master : states that there is another master active on this bus.
+- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz
+ when not specified
+- multi-master : states that there is another master active on this
+ bus.
+- idle-wait-timeout-ms : bus idle waiting timeout in milliseconds when
+ multi-master is set, defaults to 100 ms when not
+ specified.
Example:
--
2.18.0
^ permalink raw reply related
* [PATCH i2c-next v2 0/2] i2c: aspeed: Add bus idle waiting logic for multi-master use cases
From: Jae Hyun Yoo @ 2018-09-24 23:04 UTC (permalink / raw)
To: linux-aspeed
In multi-master environment, this driver's master cannot know
exactly when peer master sends data to this driver's slave so a
case can be happened that this master tries to send data through
the master_xfer function but slave data from peer master is still
being processed by this driver.
To prevent state corruption in the case, this patch adds checking
if any slave operation is ongoing and it waits up to the timeout
duration before starting a master_xfer operation.
Please review this patch set.
Thanks,
-Jae
Changes since v1:
- Changed define names of timeout related.
Jae Hyun Yoo (2):
dt-bindings: i2c: aspeed: Add 'idle-wait-timeout-ms' setting
i2c: aspeed: Add bus idle waiting logic for multi-master use cases
.../devicetree/bindings/i2c/i2c-aspeed.txt | 10 ++-
drivers/i2c/busses/i2c-aspeed.c | 70 +++++++++++++++----
2 files changed, 62 insertions(+), 18 deletions(-)
--
2.18.0
^ permalink raw reply
* [RFC PATCH i2c-next 1/2] dt-bindings: i2c: aspeed: Add 'idle-wait-timeout-ms' setting
From: Jae Hyun Yoo @ 2018-09-24 22:15 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180924215850.GD18592@kunai>
Hi Wolfram,
On 9/24/2018 2:58 PM, Wolfram Sang wrote:
> On Tue, Sep 18, 2018 at 11:02:54AM -0700, Jae Hyun Yoo wrote:
>> On 9/10/2018 2:45 PM, Jae Hyun Yoo wrote:
>>> +- idle-wait-timeout-ms : bus idle waiting timeout in milliseconds when
>>> + multi-master is set, defaults to 100 ms when not
>>> + specified.
>>
>> Will change it to 'aspeed,idle-wait-timeout-ms' as it's a non standard
>> property.
>
> No need. This binding is not a HW description, so not a DT property in
> my book. I still don't understand: Your IP core in master mode does not
> have a BUSY bit or similar which detects when a START was detected and
> clears after a STOP?
>
Okay, I'll keep this property as it is then.
Aspeed IP has the BUSY bit on the I2CD14 register and we are already
using the bit in the current code for single-master use cases.
Due to the bit doesn't cover well multi-master use cases so we need to
improve the current busy checking logic using the 'Transfer Mode State
Machine' bit fields on the same register through this patch set.
Thanks for the review!
Jae
^ permalink raw reply
* [RFC PATCH i2c-next 1/2] dt-bindings: i2c: aspeed: Add 'idle-wait-timeout-ms' setting
From: Wolfram Sang @ 2018-09-24 21:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <a81a6092-a9d0-78d5-3596-cddc5d6a0713@linux.intel.com>
On Tue, Sep 18, 2018 at 11:02:54AM -0700, Jae Hyun Yoo wrote:
> On 9/10/2018 2:45 PM, Jae Hyun Yoo wrote:
> > +- idle-wait-timeout-ms : bus idle waiting timeout in milliseconds when
> > + multi-master is set, defaults to 100 ms when not
> > + specified.
>
> Will change it to 'aspeed,idle-wait-timeout-ms' as it's a non standard
> property.
No need. This binding is not a HW description, so not a DT property in
my book. I still don't understand: Your IP core in master mode does not
have a BUSY bit or similar which detects when a START was detected and
clears after a STOP?
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* [PATCH v4] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Wolfram Sang @ 2018-09-24 21:51 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180921233050.121570-1-brendanhiggins@google.com>
On Fri, Sep 21, 2018 at 04:30:50PM -0700, Brendan Higgins wrote:
> The function that computes clock parameters from divisors did not
> respect the maximum size of the bitfields that the parameters were
> written to. This fixes the bug.
>
> This bug can be reproduced with (and this fix verified with) the test
> at: https://kunit-review.googlesource.com/c/linux/+/1035/
>
> Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
> Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Applied to for-next, thanks!
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* [PATCH] i2c: aspeed: Acknowledge most interrupts early in interrupt handler
From: Wolfram Sang @ 2018-09-24 21:45 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1536895810-28903-1-git-send-email-linux@roeck-us.net>
On Thu, Sep 13, 2018 at 08:30:10PM -0700, Guenter Roeck wrote:
> Commit 3e9efc3299dd ("i2c: aspeed: Handle master/slave combined irq events
> properly") moved interrupt acknowledgment to the end of the interrupt
> handler. In part this was done because the AST2500 datasheet says:
>
> I2CD10 Interrupt Status Register
> bit 2 Receive Done Interrupt status
> S/W needs to clear this status bit to allow next data receiving.
>
> Acknowledging Receive Done before receive data was handled resulted in
> receive errors on high speed I2C busses.
>
> However, interrupt acknowledgment was not only moved to the end of the
> interrupt handler for Receive Done Interrupt status, but for all interrupt
> status bits. This could result in race conditions if a second interrupt was
> received during interrupt handling and not handled but still acknowledged
> at the end of the interrupt handler.
>
> Acknowledge only "Receive Done Interrupt status" late in the interrupt
> handler to solve the problem.
>
> Fixes: 3e9efc3299dd ("i2c: aspeed: Handle master/slave combined irq events properly")
> Cc: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
> Cc: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Applied to for-next, thanks!
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* [GIT PULL] ARM: aspeed: dts changes for 4.20
From: Olof Johansson @ 2018-09-23 13:33 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XfwK85_os-Kjqvkwp-V8YqV3JDPZEepdgXNA+6ievOLSQ@mail.gmail.com>
Hi,
On Thu, Sep 20, 2018 at 06:18:09PM +0930, Joel Stanley wrote:
> Hello ARM Maintainers,
>
> Here's the ASPEED device tree changes for 4.20. Please pull if they
> look good. Thanks!
>
> The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:
>
> Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git \
> tags/aspeed-4.20-devicetree
>
> for you to fetch changes up to 3368e06e2a91a65cff59e520acc51b9adf4900bf:
>
> ARM: dts: aspeed: Adding Facebook TiogaPass BMC (2018-09-20 17:25:48 +0930)
>
> ----------------------------------------------------------------
> ASPEED device tree updates for 4.20
>
> - Two new ast2500-based machines:
>
> * Facebook TiogaPass (x86 server)
\o/ :-)
> * HXT StarDragon 4800 Reference Evaluation Platform 2 (arm64 server)
>
> - Updates for the Quanta q71l system
>
> - i2c device tree cleanups
Merged, thanks!
^ permalink raw reply
* [PATCH v2] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Joe Perches @ 2018-09-22 14:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAFd5g46==5HG2stvuVfOUtsSW37SvLN6cCmOhRSxibrUpxb8aA@mail.gmail.com>
On Fri, 2018-09-21 at 15:30 -0700, Brendan Higgins wrote:
> On Fri, Sep 21, 2018 at 3:26 PM Jae Hyun Yoo
[]
> > > + dev_err(dev,
> > > + "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.",
> >
> > Please put a newline character at the end of the string.
>
> I always forget to do that. I wonder if anyone has considered adding a
> warning for this to checkpatch?
Yes, but it's not possible to know when there
a pr_cont that follows so any checkpatch test
would be a false positive generator too.
^ permalink raw reply
* [PATCH v3] i2c: aspeed: fix invalid clock parameters for very large divisors
From: kbuild test robot @ 2018-09-22 6:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180921223446.82685-1-brendanhiggins@google.com>
Hi Brendan,
I love your patch! Yet something to improve:
[auto build test ERROR on wsa/i2c/for-next]
[also build test ERROR on v4.19-rc4 next-20180921]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Brendan-Higgins/i2c-aspeed-fix-invalid-clock-parameters-for-very-large-divisors/20180922-134643
base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=arm
All errors (new ones prefixed by >>):
drivers/i2c/busses/i2c-aspeed.c: In function 'aspeed_i2c_probe_bus':
>> drivers/i2c/busses/i2c-aspeed.c:920:24: error: assignment from incompatible pointer type [-Werror=incompatible-pointer-types]
bus->get_clk_reg_val = (u32 (*)(u32))match->data;
^
cc1: some warnings being treated as errors
vim +920 drivers/i2c/busses/i2c-aspeed.c
87b59ff8d Brendan Higgins 2017-07-28 875
f327c686d Brendan Higgins 2017-06-20 876 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
f327c686d Brendan Higgins 2017-06-20 877 {
87b59ff8d Brendan Higgins 2017-07-28 878 const struct of_device_id *match;
f327c686d Brendan Higgins 2017-06-20 879 struct aspeed_i2c_bus *bus;
f327c686d Brendan Higgins 2017-06-20 880 struct clk *parent_clk;
f327c686d Brendan Higgins 2017-06-20 881 struct resource *res;
f327c686d Brendan Higgins 2017-06-20 882 int irq, ret;
f327c686d Brendan Higgins 2017-06-20 883
f327c686d Brendan Higgins 2017-06-20 884 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
f327c686d Brendan Higgins 2017-06-20 885 if (!bus)
f327c686d Brendan Higgins 2017-06-20 886 return -ENOMEM;
f327c686d Brendan Higgins 2017-06-20 887
f327c686d Brendan Higgins 2017-06-20 888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f327c686d Brendan Higgins 2017-06-20 889 bus->base = devm_ioremap_resource(&pdev->dev, res);
f327c686d Brendan Higgins 2017-06-20 890 if (IS_ERR(bus->base))
f327c686d Brendan Higgins 2017-06-20 891 return PTR_ERR(bus->base);
f327c686d Brendan Higgins 2017-06-20 892
f327c686d Brendan Higgins 2017-06-20 893 parent_clk = devm_clk_get(&pdev->dev, NULL);
f327c686d Brendan Higgins 2017-06-20 894 if (IS_ERR(parent_clk))
f327c686d Brendan Higgins 2017-06-20 895 return PTR_ERR(parent_clk);
f327c686d Brendan Higgins 2017-06-20 896 bus->parent_clk_frequency = clk_get_rate(parent_clk);
f327c686d Brendan Higgins 2017-06-20 897 /* We just need the clock rate, we don't actually use the clk object. */
f327c686d Brendan Higgins 2017-06-20 898 devm_clk_put(&pdev->dev, parent_clk);
f327c686d Brendan Higgins 2017-06-20 899
edd20e95b Joel Stanley 2017-11-01 900 bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
edd20e95b Joel Stanley 2017-11-01 901 if (IS_ERR(bus->rst)) {
edd20e95b Joel Stanley 2017-11-01 902 dev_err(&pdev->dev,
6bc33c519 Jae Hyun Yoo 2018-07-02 903 "missing or invalid reset controller device tree entry\n");
edd20e95b Joel Stanley 2017-11-01 904 return PTR_ERR(bus->rst);
edd20e95b Joel Stanley 2017-11-01 905 }
edd20e95b Joel Stanley 2017-11-01 906 reset_control_deassert(bus->rst);
edd20e95b Joel Stanley 2017-11-01 907
f327c686d Brendan Higgins 2017-06-20 908 ret = of_property_read_u32(pdev->dev.of_node,
f327c686d Brendan Higgins 2017-06-20 909 "bus-frequency", &bus->bus_frequency);
f327c686d Brendan Higgins 2017-06-20 910 if (ret < 0) {
f327c686d Brendan Higgins 2017-06-20 911 dev_err(&pdev->dev,
f327c686d Brendan Higgins 2017-06-20 912 "Could not read bus-frequency property\n");
f327c686d Brendan Higgins 2017-06-20 913 bus->bus_frequency = 100000;
f327c686d Brendan Higgins 2017-06-20 914 }
f327c686d Brendan Higgins 2017-06-20 915
87b59ff8d Brendan Higgins 2017-07-28 916 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
87b59ff8d Brendan Higgins 2017-07-28 917 if (!match)
87b59ff8d Brendan Higgins 2017-07-28 918 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
87b59ff8d Brendan Higgins 2017-07-28 919 else
5799c4b2f Jae Hyun Yoo 2018-07-24 @920 bus->get_clk_reg_val = (u32 (*)(u32))match->data;
87b59ff8d Brendan Higgins 2017-07-28 921
f327c686d Brendan Higgins 2017-06-20 922 /* Initialize the I2C adapter */
f327c686d Brendan Higgins 2017-06-20 923 spin_lock_init(&bus->lock);
f327c686d Brendan Higgins 2017-06-20 924 init_completion(&bus->cmd_complete);
f327c686d Brendan Higgins 2017-06-20 925 bus->adap.owner = THIS_MODULE;
f327c686d Brendan Higgins 2017-06-20 926 bus->adap.retries = 0;
f327c686d Brendan Higgins 2017-06-20 927 bus->adap.timeout = 5 * HZ;
f327c686d Brendan Higgins 2017-06-20 928 bus->adap.algo = &aspeed_i2c_algo;
f327c686d Brendan Higgins 2017-06-20 929 bus->adap.dev.parent = &pdev->dev;
f327c686d Brendan Higgins 2017-06-20 930 bus->adap.dev.of_node = pdev->dev.of_node;
f327c686d Brendan Higgins 2017-06-20 931 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
f327c686d Brendan Higgins 2017-06-20 932 i2c_set_adapdata(&bus->adap, bus);
f327c686d Brendan Higgins 2017-06-20 933
f327c686d Brendan Higgins 2017-06-20 934 bus->dev = &pdev->dev;
f327c686d Brendan Higgins 2017-06-20 935
f327c686d Brendan Higgins 2017-06-20 936 /* Clean up any left over interrupt state. */
f327c686d Brendan Higgins 2017-06-20 937 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
f327c686d Brendan Higgins 2017-06-20 938 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
f327c686d Brendan Higgins 2017-06-20 939 /*
f327c686d Brendan Higgins 2017-06-20 940 * bus.lock does not need to be held because the interrupt handler has
f327c686d Brendan Higgins 2017-06-20 941 * not been enabled yet.
f327c686d Brendan Higgins 2017-06-20 942 */
f327c686d Brendan Higgins 2017-06-20 943 ret = aspeed_i2c_init(bus, pdev);
f327c686d Brendan Higgins 2017-06-20 944 if (ret < 0)
f327c686d Brendan Higgins 2017-06-20 945 return ret;
f327c686d Brendan Higgins 2017-06-20 946
f327c686d Brendan Higgins 2017-06-20 947 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
f327c686d Brendan Higgins 2017-06-20 948 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
f327c686d Brendan Higgins 2017-06-20 949 0, dev_name(&pdev->dev), bus);
f327c686d Brendan Higgins 2017-06-20 950 if (ret < 0)
f327c686d Brendan Higgins 2017-06-20 951 return ret;
f327c686d Brendan Higgins 2017-06-20 952
f327c686d Brendan Higgins 2017-06-20 953 ret = i2c_add_adapter(&bus->adap);
f327c686d Brendan Higgins 2017-06-20 954 if (ret < 0)
f327c686d Brendan Higgins 2017-06-20 955 return ret;
f327c686d Brendan Higgins 2017-06-20 956
f327c686d Brendan Higgins 2017-06-20 957 platform_set_drvdata(pdev, bus);
f327c686d Brendan Higgins 2017-06-20 958
f327c686d Brendan Higgins 2017-06-20 959 dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
f327c686d Brendan Higgins 2017-06-20 960 bus->adap.nr, irq);
f327c686d Brendan Higgins 2017-06-20 961
f327c686d Brendan Higgins 2017-06-20 962 return 0;
f327c686d Brendan Higgins 2017-06-20 963 }
f327c686d Brendan Higgins 2017-06-20 964
:::::: The code at line 920 was first introduced by commit
:::::: 5799c4b2f1dbc0166d9b1d94443deaafc6e7a070 i2c: aspeed: Add an explicit type casting for *get_clk_reg_val
:::::: TO: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
:::::: CC: Wolfram Sang <wsa@the-dreams.de>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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* [PATCH v4] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Brendan Higgins @ 2018-09-21 23:30 UTC (permalink / raw)
To: linux-aspeed
The function that computes clock parameters from divisors did not
respect the maximum size of the bitfields that the parameters were
written to. This fixes the bug.
This bug can be reproduced with (and this fix verified with) the test
at: https://kunit-review.googlesource.com/c/linux/+/1035/
Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
- v2 updates the title of the patch, renames a local variable, and
prints an error when the clock divider is clamped.
- v3 adds a missing newline character for the new logging statement.
- v4 fixes a cast that I forgot to update in v2.
---
drivers/i2c/busses/i2c-aspeed.c | 65 +++++++++++++++++++++++----------
1 file changed, 45 insertions(+), 20 deletions(-)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index c258c4d9a4c0..49e682f358e0 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -142,7 +142,8 @@ struct aspeed_i2c_bus {
/* Synchronizes I/O mem access to base. */
spinlock_t lock;
struct completion cmd_complete;
- u32 (*get_clk_reg_val)(u32 divisor);
+ u32 (*get_clk_reg_val)(struct device *dev,
+ u32 divisor);
unsigned long parent_clk_frequency;
u32 bus_frequency;
/* Transaction state. */
@@ -705,16 +706,27 @@ static const struct i2c_algorithm aspeed_i2c_algo = {
#endif /* CONFIG_I2C_SLAVE */
};
-static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
+static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
+ u32 clk_high_low_mask,
+ u32 divisor)
{
- u32 base_clk, clk_high, clk_low, tmp;
+ u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
+
+ /*
+ * SCL_high and SCL_low represent a value 1 greater than what is stored
+ * since a zero divider is meaningless. Thus, the max value each can
+ * store is every bit set + 1. Since SCL_high and SCL_low are added
+ * together (see below), the max value of both is the max value of one
+ * them times two.
+ */
+ clk_high_low_max = (clk_high_low_mask + 1) * 2;
/*
* The actual clock frequency of SCL is:
* SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
* = APB_freq / divisor
* where base_freq is a programmable clock divider; its value is
- * base_freq = 1 << base_clk
+ * base_freq = 1 << base_clk_divisor
* SCL_high is the number of base_freq clock cycles that SCL stays high
* and SCL_low is the number of base_freq clock cycles that SCL stays
* low for a period of SCL.
@@ -724,47 +736,59 @@ static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
* SCL_low = clk_low + 1
* Thus,
* SCL_freq = APB_freq /
- * ((1 << base_clk) * (clk_high + 1 + clk_low + 1))
+ * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
* The documentation recommends clk_high >= clk_high_max / 2 and
* clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
* gives us the following solution:
*/
- base_clk = divisor > clk_high_low_max ?
+ base_clk_divisor = divisor > clk_high_low_max ?
ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
- tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
- clk_low = tmp / 2;
- clk_high = tmp - clk_low;
- if (clk_high)
- clk_high--;
+ if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
+ base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
+ clk_low = clk_high_low_mask;
+ clk_high = clk_high_low_mask;
+ dev_err(dev,
+ "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
+ divisor, (1 << base_clk_divisor) * clk_high_low_max);
+ } else {
+ tmp = (divisor + (1 << base_clk_divisor) - 1)
+ >> base_clk_divisor;
+ clk_low = tmp / 2;
+ clk_high = tmp - clk_low;
+
+ if (clk_high)
+ clk_high--;
- if (clk_low)
- clk_low--;
+ if (clk_low)
+ clk_low--;
+ }
return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
& ASPEED_I2CD_TIME_SCL_HIGH_MASK)
| ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
& ASPEED_I2CD_TIME_SCL_LOW_MASK)
- | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
+ | (base_clk_divisor
+ & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
}
-static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)
+static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
{
/*
* clk_high and clk_low are each 3 bits wide, so each can hold a max
* value of 8 giving a clk_high_low_max of 16.
*/
- return aspeed_i2c_get_clk_reg_val(16, divisor);
+ return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
}
-static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
+static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
{
/*
* clk_high and clk_low are each 4 bits wide, so each can hold a max
* value of 16 giving a clk_high_low_max of 32.
*/
- return aspeed_i2c_get_clk_reg_val(32, divisor);
+ return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
}
/* precondition: bus.lock has been acquired. */
@@ -777,7 +801,7 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
ASPEED_I2CD_TIME_THDSTA_MASK |
ASPEED_I2CD_TIME_TACST_MASK);
- clk_reg_val |= bus->get_clk_reg_val(divisor);
+ clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
@@ -893,7 +917,8 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev)
if (!match)
bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
else
- bus->get_clk_reg_val = (u32 (*)(u32))match->data;
+ bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
+ match->data;
/* Initialize the I2C adapter */
spin_lock_init(&bus->lock);
--
2.19.0.444.g18242da7ef-goog
^ permalink raw reply related
* [PATCH v3] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Jae Hyun Yoo @ 2018-09-21 22:46 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180921223446.82685-1-brendanhiggins@google.com>
On 9/21/2018 3:34 PM, Brendan Higgins wrote:
> @@ -142,7 +142,8 @@ struct aspeed_i2c_bus {
> /* Synchronizes I/O mem access to base. */
> spinlock_t lock;
> struct completion cmd_complete;
> - u32 (*get_clk_reg_val)(u32 divisor);
> + u32 (*get_clk_reg_val)(struct device *dev,
> + u32 divisor);
I realized that you changed *get_clk_reg_val type in v2. You probably
need to fix below code in aspeed_i2c_probe_bus() as well to remove
a sparse warning.
bus->get_clk_reg_val = (u32 (*)(u32))match->data;
-Jae
^ permalink raw reply
* [PATCH v3] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Brendan Higgins @ 2018-09-21 22:34 UTC (permalink / raw)
To: linux-aspeed
The function that computes clock parameters from divisors did not
respect the maximum size of the bitfields that the parameters were
written to. This fixes the bug.
This bug can be reproduced with (and this fix verified with) the test
at: https://kunit-review.googlesource.com/c/linux/+/1035/
Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
- v2 updates the title of the patch, renames a local variable, and
prints an error when the clock divider is clamped.
- v3 adds a missing newline character for the new logging statement.
---
drivers/i2c/busses/i2c-aspeed.c | 62 +++++++++++++++++++++++----------
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index c258c4d9a4c0..a3bfec2c0694 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -142,7 +142,8 @@ struct aspeed_i2c_bus {
/* Synchronizes I/O mem access to base. */
spinlock_t lock;
struct completion cmd_complete;
- u32 (*get_clk_reg_val)(u32 divisor);
+ u32 (*get_clk_reg_val)(struct device *dev,
+ u32 divisor);
unsigned long parent_clk_frequency;
u32 bus_frequency;
/* Transaction state. */
@@ -705,16 +706,27 @@ static const struct i2c_algorithm aspeed_i2c_algo = {
#endif /* CONFIG_I2C_SLAVE */
};
-static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
+static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
+ u32 clk_high_low_mask,
+ u32 divisor)
{
- u32 base_clk, clk_high, clk_low, tmp;
+ u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
+
+ /*
+ * SCL_high and SCL_low represent a value 1 greater than what is stored
+ * since a zero divider is meaningless. Thus, the max value each can
+ * store is every bit set + 1. Since SCL_high and SCL_low are added
+ * together (see below), the max value of both is the max value of one
+ * them times two.
+ */
+ clk_high_low_max = (clk_high_low_mask + 1) * 2;
/*
* The actual clock frequency of SCL is:
* SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
* = APB_freq / divisor
* where base_freq is a programmable clock divider; its value is
- * base_freq = 1 << base_clk
+ * base_freq = 1 << base_clk_divisor
* SCL_high is the number of base_freq clock cycles that SCL stays high
* and SCL_low is the number of base_freq clock cycles that SCL stays
* low for a period of SCL.
@@ -724,47 +736,59 @@ static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
* SCL_low = clk_low + 1
* Thus,
* SCL_freq = APB_freq /
- * ((1 << base_clk) * (clk_high + 1 + clk_low + 1))
+ * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
* The documentation recommends clk_high >= clk_high_max / 2 and
* clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
* gives us the following solution:
*/
- base_clk = divisor > clk_high_low_max ?
+ base_clk_divisor = divisor > clk_high_low_max ?
ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
- tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
- clk_low = tmp / 2;
- clk_high = tmp - clk_low;
- if (clk_high)
- clk_high--;
+ if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
+ base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
+ clk_low = clk_high_low_mask;
+ clk_high = clk_high_low_mask;
+ dev_err(dev,
+ "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
+ divisor, (1 << base_clk_divisor) * clk_high_low_max);
+ } else {
+ tmp = (divisor + (1 << base_clk_divisor) - 1)
+ >> base_clk_divisor;
+ clk_low = tmp / 2;
+ clk_high = tmp - clk_low;
+
+ if (clk_high)
+ clk_high--;
- if (clk_low)
- clk_low--;
+ if (clk_low)
+ clk_low--;
+ }
return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
& ASPEED_I2CD_TIME_SCL_HIGH_MASK)
| ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
& ASPEED_I2CD_TIME_SCL_LOW_MASK)
- | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
+ | (base_clk_divisor
+ & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
}
-static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)
+static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
{
/*
* clk_high and clk_low are each 3 bits wide, so each can hold a max
* value of 8 giving a clk_high_low_max of 16.
*/
- return aspeed_i2c_get_clk_reg_val(16, divisor);
+ return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
}
-static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
+static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
{
/*
* clk_high and clk_low are each 4 bits wide, so each can hold a max
* value of 16 giving a clk_high_low_max of 32.
*/
- return aspeed_i2c_get_clk_reg_val(32, divisor);
+ return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
}
/* precondition: bus.lock has been acquired. */
@@ -777,7 +801,7 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
ASPEED_I2CD_TIME_THDSTA_MASK |
ASPEED_I2CD_TIME_TACST_MASK);
- clk_reg_val |= bus->get_clk_reg_val(divisor);
+ clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
--
2.19.0.444.g18242da7ef-goog
^ permalink raw reply related
* [PATCH v2] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Brendan Higgins @ 2018-09-21 22:30 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <f5943177-6f1b-9344-3821-2aac001ff45d@linux.intel.com>
On Fri, Sep 21, 2018 at 3:26 PM Jae Hyun Yoo
<jae.hyun.yoo@linux.intel.com> wrote:
>
<snip>
>
> > + if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
> > + base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
> > + clk_low = clk_high_low_mask;
> > + clk_high = clk_high_low_mask;
> > + dev_err(dev,
> > + "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.",
>
> Please put a newline character at the end of the string.
I always forget to do that. I wonder if anyone has considered adding a
warning for this to checkpatch?
>
> Thanks,
> Jae
>
> [....]
^ permalink raw reply
* [PATCH v2] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Jae Hyun Yoo @ 2018-09-21 22:26 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180921221025.75003-1-brendanhiggins@google.com>
Hi,
On 9/21/2018 3:10 PM, Brendan Higgins wrote:
> The function that computes clock parameters from divisors did not
> respect the maximum size of the bitfields that the parameters were
> written to. This fixes the bug.
>
> This bug can be reproduced with (and this fix verified with) the test
> at: https://kunit-review.googlesource.com/c/linux/+/1035/
>
> Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
> Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
> ---
> - v2 updates the title of the patch, renames a local variable, and
> prints an error when the clock divider is clamped.
> ---
[....]
> + if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
> + base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
> + clk_low = clk_high_low_mask;
> + clk_high = clk_high_low_mask;
> + dev_err(dev,
> + "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.",
Please put a newline character at the end of the string.
Thanks,
Jae
[....]
^ permalink raw reply
* [PATCH] i2c: aspeed: fixed invalid clock parameters for very large divisors
From: Brendan Higgins @ 2018-09-21 22:18 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <07af0253-1efc-2ae1-93fb-ebcc1996d768@linux.intel.com>
On Fri, Sep 21, 2018 at 10:46 AM Jae Hyun Yoo
<jae.hyun.yoo@linux.intel.com> wrote:
>
> Hi Brendan,
>
> nit:
> Title in imperative mood. I'd put 'fix' instead of 'fixed'.
>
<snip>
>
> One minor issue is, 'base_clk_divisor' instead of 'base_clk' could avoid
> misreading on this code.
>
> With that, it looks nice to me. Thanks!
>
> Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Thanks for the review!
^ permalink raw reply
* [PATCH v2] i2c: aspeed: fix invalid clock parameters for very large divisors
From: Brendan Higgins @ 2018-09-21 22:10 UTC (permalink / raw)
To: linux-aspeed
The function that computes clock parameters from divisors did not
respect the maximum size of the bitfields that the parameters were
written to. This fixes the bug.
This bug can be reproduced with (and this fix verified with) the test
at: https://kunit-review.googlesource.com/c/linux/+/1035/
Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
- v2 updates the title of the patch, renames a local variable, and
prints an error when the clock divider is clamped.
---
drivers/i2c/busses/i2c-aspeed.c | 62 +++++++++++++++++++++++----------
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index c258c4d9a4c0..4e946cbb7270 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -142,7 +142,8 @@ struct aspeed_i2c_bus {
/* Synchronizes I/O mem access to base. */
spinlock_t lock;
struct completion cmd_complete;
- u32 (*get_clk_reg_val)(u32 divisor);
+ u32 (*get_clk_reg_val)(struct device *dev,
+ u32 divisor);
unsigned long parent_clk_frequency;
u32 bus_frequency;
/* Transaction state. */
@@ -705,16 +706,27 @@ static const struct i2c_algorithm aspeed_i2c_algo = {
#endif /* CONFIG_I2C_SLAVE */
};
-static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
+static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
+ u32 clk_high_low_mask,
+ u32 divisor)
{
- u32 base_clk, clk_high, clk_low, tmp;
+ u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
+
+ /*
+ * SCL_high and SCL_low represent a value 1 greater than what is stored
+ * since a zero divider is meaningless. Thus, the max value each can
+ * store is every bit set + 1. Since SCL_high and SCL_low are added
+ * together (see below), the max value of both is the max value of one
+ * them times two.
+ */
+ clk_high_low_max = (clk_high_low_mask + 1) * 2;
/*
* The actual clock frequency of SCL is:
* SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
* = APB_freq / divisor
* where base_freq is a programmable clock divider; its value is
- * base_freq = 1 << base_clk
+ * base_freq = 1 << base_clk_divisor
* SCL_high is the number of base_freq clock cycles that SCL stays high
* and SCL_low is the number of base_freq clock cycles that SCL stays
* low for a period of SCL.
@@ -724,47 +736,59 @@ static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
* SCL_low = clk_low + 1
* Thus,
* SCL_freq = APB_freq /
- * ((1 << base_clk) * (clk_high + 1 + clk_low + 1))
+ * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
* The documentation recommends clk_high >= clk_high_max / 2 and
* clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
* gives us the following solution:
*/
- base_clk = divisor > clk_high_low_max ?
+ base_clk_divisor = divisor > clk_high_low_max ?
ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
- tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
- clk_low = tmp / 2;
- clk_high = tmp - clk_low;
- if (clk_high)
- clk_high--;
+ if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
+ base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
+ clk_low = clk_high_low_mask;
+ clk_high = clk_high_low_mask;
+ dev_err(dev,
+ "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.",
+ divisor, (1 << base_clk_divisor) * clk_high_low_max);
+ } else {
+ tmp = (divisor + (1 << base_clk_divisor) - 1)
+ >> base_clk_divisor;
+ clk_low = tmp / 2;
+ clk_high = tmp - clk_low;
+
+ if (clk_high)
+ clk_high--;
- if (clk_low)
- clk_low--;
+ if (clk_low)
+ clk_low--;
+ }
return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
& ASPEED_I2CD_TIME_SCL_HIGH_MASK)
| ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
& ASPEED_I2CD_TIME_SCL_LOW_MASK)
- | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
+ | (base_clk_divisor
+ & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
}
-static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)
+static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
{
/*
* clk_high and clk_low are each 3 bits wide, so each can hold a max
* value of 8 giving a clk_high_low_max of 16.
*/
- return aspeed_i2c_get_clk_reg_val(16, divisor);
+ return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
}
-static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
+static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
{
/*
* clk_high and clk_low are each 4 bits wide, so each can hold a max
* value of 16 giving a clk_high_low_max of 32.
*/
- return aspeed_i2c_get_clk_reg_val(32, divisor);
+ return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
}
/* precondition: bus.lock has been acquired. */
@@ -777,7 +801,7 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
ASPEED_I2CD_TIME_THDSTA_MASK |
ASPEED_I2CD_TIME_TACST_MASK);
- clk_reg_val |= bus->get_clk_reg_val(divisor);
+ clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
--
2.19.0.444.g18242da7ef-goog
^ permalink raw reply related
* [PATCH v2 2/2] media: platform: Add Aspeed Video Engine driver
From: Eddie James @ 2018-09-21 19:39 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <66a5fbcf-2b41-ffd5-ad32-f26af47f3cea@xs4all.nl>
On 09/14/2018 12:31 PM, Hans Verkuil wrote:
> On 09/14/2018 05:22 PM, Eddie James wrote:
>>>> +static int aspeed_video_allocate_cma(struct aspeed_video *video)
>>>>
<snip>
>>>> + if (rc) {
>>>> + v4l2_device_unregister(v4l2_dev);
>>>> + dev_err(video->dev, "Failed to register video device\n");
>>>> + return rc;
>>>> + }
>>>> +
>>>> + video->v4l2_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
>>>> + video->v4l2_fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG;
>>>> + video->v4l2_fmt.fmt.pix.field = V4L2_FIELD_NONE;
>>>> + video->v4l2_fmt.fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
>>> COLORSPACE_JPEG is deprecated. Use V4L2_COLORSPACE_SRGB for pix.colorspace
>>> and set pix.quantization to V4L2_QUANTIZATION_FULL_RANGE.
FYI I'm getting a v4l2-compliance failure using your suggestion:
Format ioctls:
??? ??? test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
??? ??? test VIDIOC_G/S_PARM: OK
??? ??? test VIDIOC_G_FBUF: OK (Not Supported)
??? ??? fail:
../../../v4l-utils-1.12.3/utils/v4l2-compliance/v4l2-test-formats.cpp(331):
pixelformat == V4L2_PIX_FMT_JPEG && colorspace != V4L2_COLORSPACE_JPEG
??? ??? fail:
../../../v4l-utils-1.12.3/utils/v4l2-compliance/v4l2-test-formats.cpp(436):
testColorspace(pix.pixelformat, pix.colorspace, pix.ycbcr_enc,
pix.quantization)
??????? test VIDIOC_G_FMT: FAIL
This is with v4l-utils commit d977e20a45a03543c4bdfeb3aef5211446de7398.
>>>
>>>> +
>>>> + /* Don't fail the probe if controls init fails */
>>>> + v4l2_ctrl_handler_init(&video->v4l2_ctrl, 2);
>>>> +
<snip>
>>>> ve,
>>>> +};
>>>> +
>>>> +module_platform_driver(aspeed_video_driver);
>>>> +
>>>> +MODULE_DESCRIPTION("ASPEED Video Engine Driver");
>>>> +MODULE_AUTHOR("Eddie James");
>>>> +MODULE_LICENSE("GPL v2");
>>>>
>>> I don't like the read() API here. It is not a real read() either since it assumes
>>> userspace reads full frames at a time. But if you read e.g. one byte at a time,
>>> then each byte is just the first byte of a different frame.
>> Yea...
>>
>>> I think we need to figure out how to make the stream I/O version just as fast
>>> if not faster as the read() API.
I do have the streaming API working with good performance now. Will get
another patch set up soon.
Thanks,
Eddie
>> OK, I'll see what I can do.
>>
>> Thanks for the review!
>> Eddie
>>
>>> Regards,
>>>
>>> Hans
>>>
> Regards,
>
> Hans
>
^ permalink raw reply
* [PATCH] i2c: aspeed: fixed invalid clock parameters for very large divisors
From: Jae Hyun Yoo @ 2018-09-21 17:46 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180920232820.243734-1-brendanhiggins@google.com>
Hi Brendan,
nit:
Title in imperative mood. I'd put 'fix' instead of 'fixed'.
On 9/20/2018 4:28 PM, Brendan Higgins wrote:
> The function that computes clock parameters from divisors did not
> respect the maximum size of the bitfields that the parameters were
> written to. This fixes the bug.
>
> This bug can be reproduced with (and this fix verified with) the test
> at: https://kunit-review.googlesource.com/c/linux/+/1035/
>
> Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
[....]
> + if (base_clk > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
> + base_clk = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
> + clk_low = clk_high_low_mask;
> + clk_high = clk_high_low_mask;
Yes, it fixes these parameters to the lowest bus speed setting with the
maximum base clock divisor value and the maximum SCL timing cycle value
when a low bus-frequency is requested which exceeds the range of this
H/W supports. This exceptional case handling is needed to prevent making
invalid settings on it. Nice fix!
One minor issue is, 'base_clk_divisor' instead of 'base_clk' could avoid
misreading on this code.
With that, it looks nice to me. Thanks!
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
^ permalink raw reply
* [PATCH 1/4] mtd: spi-nor: aspeed: use command mode for reads
From: Cédric Le Goater @ 2018-09-21 6:09 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XePSehmuYTtJFYuNqUz_CQ4cQ6s4gdZ2rKNKUpO46yZKQ@mail.gmail.com>
On 09/21/2018 04:39 AM, Joel Stanley wrote:
> Hello Mark,
>
> On Mon, 23 Jul 2018 at 21:42, Joel Stanley <joel@jms.id.au> wrote:
>>
>> On 22 June 2018 at 21:44, C?dric Le Goater <clg@kaod.org> wrote:
>>> When reading flash contents, try to use the "command mode" if the AHB
>>> window configured for the flash module is big enough. Else, just fall
>>> back to the "user mode" to perform the read.
>>>
>>> Signed-off-by: C?dric Le Goater <clg@kaod.org>
>>
>> Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> Are you waiting on anything from Cedric or myself for this series. If
> not, can we please get them queued for 4.20?
There is one typo on the definition of the timing register of the AST2400
SPI controller we should fix. It can come later. Apart from that, I don't
see any changes I would like to do. May be a couple of variable renames to
clarify the loop on the hclk cycles and delays to fit the U-Boot driver
which was proposed recently. Please tell me :)
Thanks,
C.
^ permalink raw reply
* [PATCH 1/4] mtd: spi-nor: aspeed: use command mode for reads
From: Joel Stanley @ 2018-09-21 2:39 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8Xf-XfxMVMewC5T6u1XzDX3idqk+FeGRLMC+xrKDqtWggg@mail.gmail.com>
Hello Mark,
On Mon, 23 Jul 2018 at 21:42, Joel Stanley <joel@jms.id.au> wrote:
>
> On 22 June 2018 at 21:44, C?dric Le Goater <clg@kaod.org> wrote:
> > When reading flash contents, try to use the "command mode" if the AHB
> > window configured for the flash module is big enough. Else, just fall
> > back to the "user mode" to perform the read.
> >
> > Signed-off-by: C?dric Le Goater <clg@kaod.org>
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
Are you waiting on anything from Cedric or myself for this series. If
not, can we please get them queued for 4.20?
Cheers,
Joel
^ permalink raw reply
* [PATCH] i2c: aspeed: fixed invalid clock parameters for very large divisors
From: Brendan Higgins @ 2018-09-20 23:28 UTC (permalink / raw)
To: linux-aspeed
The function that computes clock parameters from divisors did not
respect the maximum size of the bitfields that the parameters were
written to. This fixes the bug.
This bug can be reproduced with (and this fix verified with) the test
at: https://kunit-review.googlesource.com/c/linux/+/1035/
Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
---
drivers/i2c/busses/i2c-aspeed.c | 38 +++++++++++++++++++++++----------
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index c258c4d9a4c0..c1c3f0a4d805 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -705,9 +705,18 @@ static const struct i2c_algorithm aspeed_i2c_algo = {
#endif /* CONFIG_I2C_SLAVE */
};
-static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
+static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_mask, u32 divisor)
{
- u32 base_clk, clk_high, clk_low, tmp;
+ u32 base_clk, clk_high_low_max, clk_high, clk_low, tmp;
+
+ /*
+ * SCL_high and SCL_low represent a value 1 greater than what is stored
+ * since a zero divider is meaningless. Thus, the max value each can
+ * store is every bit set + 1. Since SCL_high and SCL_low are added
+ * together (see below), the max value of both is the max value of one
+ * them times two.
+ */
+ clk_high_low_max = (clk_high_low_mask + 1) * 2;
/*
* The actual clock frequency of SCL is:
@@ -731,15 +740,22 @@ static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
*/
base_clk = divisor > clk_high_low_max ?
ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
- tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
- clk_low = tmp / 2;
- clk_high = tmp - clk_low;
- if (clk_high)
- clk_high--;
+ if (base_clk > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
+ base_clk = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
+ clk_low = clk_high_low_mask;
+ clk_high = clk_high_low_mask;
+ } else {
+ tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
+ clk_low = tmp / 2;
+ clk_high = tmp - clk_low;
+
+ if (clk_high)
+ clk_high--;
- if (clk_low)
- clk_low--;
+ if (clk_low)
+ clk_low--;
+ }
return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
@@ -755,7 +771,7 @@ static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)
* clk_high and clk_low are each 3 bits wide, so each can hold a max
* value of 8 giving a clk_high_low_max of 16.
*/
- return aspeed_i2c_get_clk_reg_val(16, divisor);
+ return aspeed_i2c_get_clk_reg_val(GENMASK(2, 0), divisor);
}
static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
@@ -764,7 +780,7 @@ static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
* clk_high and clk_low are each 4 bits wide, so each can hold a max
* value of 16 giving a clk_high_low_max of 32.
*/
- return aspeed_i2c_get_clk_reg_val(32, divisor);
+ return aspeed_i2c_get_clk_reg_val(GENMASK(3, 0), divisor);
}
/* precondition: bus.lock has been acquired. */
--
2.19.0.444.g18242da7ef-goog
^ permalink raw reply related
* [GIT PULL] ARM: aspeed: dts changes for 4.20
From: Joel Stanley @ 2018-09-20 8:48 UTC (permalink / raw)
To: linux-aspeed
Hello ARM Maintainers,
Here's the ASPEED device tree changes for 4.20. Please pull if they
look good. Thanks!
The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:
Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git \
tags/aspeed-4.20-devicetree
for you to fetch changes up to 3368e06e2a91a65cff59e520acc51b9adf4900bf:
ARM: dts: aspeed: Adding Facebook TiogaPass BMC (2018-09-20 17:25:48 +0930)
----------------------------------------------------------------
ASPEED device tree updates for 4.20
- Two new ast2500-based machines:
* Facebook TiogaPass (x86 server)
* HXT StarDragon 4800 Reference Evaluation Platform 2 (arm64 server)
- Updates for the Quanta q71l system
- i2c device tree cleanups
----------------------------------------------------------------
Patrick Venture (3):
ARM: dts: aspeed: quanta-q71l: add aliases for i2c
ARM: dts: aspeed: quanta-q71l: Add four PSUs
ARM: dts: aspeed: quanta-q71l: Enable adc & ibt nodes
Rob Herring (1):
ARM: dts: aspeed: Fix I2C bus warnings
Vijay Khemka (1):
ARM: dts: aspeed: Adding Facebook TiogaPass BMC
Yuan Yao (1):
ARM: dts: aspeed: Add HXT StarDragon 4800 REP2 BMC
arch/arm/boot/dts/Makefile | 2 +
.../dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 207 +++++++++++++++++++++
.../arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 146 +++++++++++++++
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 47 +++++
arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
6 files changed, 404 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
^ permalink raw reply
* [PATCH] ARM: dts: aspeed: Add HXT StarDragon 4800 REP2 BMC
From: Joel Stanley @ 2018-09-20 7:31 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CA+eB3AxTuxNFvQFk+bLrcXAfUx2O0U3Qmga+u2UsfKpfNmHfcw@mail.gmail.com>
On Thu, 13 Sep 2018 at 15:32, Yao Yuan <yao.yuan@linaro.org> wrote:
>
> On 13 September 2018 at 11:01, Joel Stanley <joel@jms.id.au> wrote:
>>
>> > The HXT StarDragon 4800 REP2 (Reference Evaluation Platform) is
>> > an aarch64 ARMv8 server platform with an ast2520 BMC.
>> >
>> Looks good. I will apply it to the Aspeed tree in a few days, after
>> giving others a chance to review.
>>
>> Out of interest, are you planning on running OpenBMC on this platform?
>
>
> Yes, I will running OpenBMC on this platform.
> And In fact, the OpenBMC basic startup is already running on REP2.
> I'm also trying to push the OpenBMC patch for this platform.
Great!
>> > .../devicetree/bindings/vendor-prefixes.txt | 1 +
>> > arch/arm/boot/dts/Makefile | 1 +
>> > .../dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 207 +++++++++++++++++++++
>> > 3 files changed, 209 insertions(+)
>> > create mode 100644 arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
>> >
>> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> > index 2c3fc51..c65c0c1 100644
>> > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
>> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> > @@ -165,6 +165,7 @@ honeywell Honeywell
>> > hp Hewlett Packard
>> > holtek Holtek Semiconductor, Inc.
>> > hwacom HwaCom Systems Inc.
>> > +hxt Huaxintong Semiconductor Technology Co., Ltd.
>> > i2se I2SE GmbH
>> > ibm International Business Machines (IBM)
>> > idt Integrated Device Technologies, Inc.
This part of the patch should go to the device tree mailing list in
it's own patch. That saves maintainers having to deal with conflicting
additions.
>> > diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
>> > new file mode 100644
>> > index 0000000..83335c0
>> > --- /dev/null
>> > +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
>> > @@ -0,0 +1,207 @@
>> > +// SPDX-License-Identifier: GPL-2.0+
>> > +/dts-v1/;
>> > +
>> > +#include "aspeed-g5.dtsi"
>> > +#include <dt-bindings/gpio/aspeed-gpio.h>
>> > +
>> > +/ {
>> > + model = "HXT StarDragon 4800 REP2 AST2520";
>> > + compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500";
>> > +
>> > + chosen {
>> > + stdout-path = &uart5;
>> > + bootargs = "console=ttyS4,115200 earlyprintk";
>> > + };
>> > +
>> > + memory {
When building with W=1:
Warning (unit_address_vs_reg): /memory: node has a reg or ranges
property, but no unit name
It should instead look like this:
memory at 80000000 {
The rest looks good to me. I made the fix for you and applied this to
the aspeed v4.20 device tree branch.
I added the device tree maintainers to cc so they could take a look.
If any comments come up please address them in follow up patches.
Cheers,
Joel
>> > + reg = <0x80000000 0x40000000>;
>> > + };
>> > +
>> > + iio-hwmon {
>> > + compatible = "iio-hwmon";
>> > + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
>> > + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>;
>> > + };
>> > +
>> > + iio-hwmon-battery {
>> > + compatible = "iio-hwmon";
>> > + io-channels = <&adc 7>;
>> > + };
>> > +
>> > + leds {
>> > + compatible = "gpio-leds";
>> > +
>> > + system_fault1 {
>> > + label = "System_fault1";
>> > + gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>;
>> > + };
>> > +
>> > + system_fault2 {
>> > + label = "System_fault2";
>> > + gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>;
>> > + };
>> > + };
>> > +};
>> > +
>> > +&fmc {
>> > + status = "okay";
>> > + flash at 0 {
>> > + status = "okay";
>> > + m25p,fast-read;
>> > + label = "bmc";
>> > +#include "openbmc-flash-layout.dtsi"
>> > + };
>> > +};
>> > +
>> > +&spi1 {
>> > + status = "okay";
>> > + pinctrl-names = "default";
>> > + pinctrl-0 = <&pinctrl_spi1_default>;
>> > + flash at 0 {
>> > + status = "okay";
>> > + };
>> > +};
>> > +
>> > +&spi2 {
>> > + pinctrl-names = "default";
>> > + pinctrl-0 = <&pinctrl_spi2ck_default
>> > + &pinctrl_spi2miso_default
>> > + &pinctrl_spi2mosi_default
>> > + &pinctrl_spi2cs0_default>;
>> > +};
>> > +
>> > +&uart3 {
>> > + status = "okay";
>> > +
>> > + pinctrl-names = "default";
>> > + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
>> > + current-speed = <115200>;
>> > +};
>> > +
>> > +&uart5 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&mac0 {
>> > + status = "okay";
>> > + pinctrl-names = "default";
>> > + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
>> > +};
>> > +
>> > +&mac1 {
>> > + status = "okay";
>> > + pinctrl-names = "default";
>> > + pinctrl-0 = <&pinctrl_rmii2_default>;
>> > + use-ncsi;
>> > +};
>> > +
>> > +&i2c0 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&i2c1 {
>> > + status = "okay";
>> > +
>> > + tmp421 at 1e {
>> > + compatible = "ti,tmp421";
>> > + reg = <0x1e>;
>> > + };
>> > + tmp421 at 2a {
>> > + compatible = "ti,tmp421";
>> > + reg = <0x2a>;
>> > + };
>> > + tmp421 at 1c {
>> > + compatible = "ti,tmp421";
>> > + reg = <0x1c>;
>> > + };
>> > +};
>> > +
>> > +&i2c2 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&i2c3 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&i2c4 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&i2c5 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&i2c6 {
>> > + status = "okay";
>> > +
>> > + tmp421 at 1f {
>> > + compatible = "ti,tmp421";
>> > + reg = <0x1f>;
>> > + };
>> > + nvt210 at 4c {
>> > + compatible = "nvt210";
>> > + reg = <0x4c>;
>> > + };
>> > + eeprom at 50 {
>> > + compatible = "atmel,24c128";
>> > + reg = <0x50>;
>> > + pagesize = <128>;
>> > + };
>> > +};
>> > +
>> > +&i2c7 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&i2c8 {
>> > + status = "okay";
>> > +
>> > + pca9641 at 70 {
>> > + compatible = "nxp,pca9641";
>> > + reg = <0x70>;
>> > + i2c-arb {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > + eeprom at 50 {
>> > + compatible = "atmel,24c02";
>> > + reg = <0x50>;
>> > + };
>> > + dps650ab at 58 {
>> > + compatible = "dps650ab";
>> > + reg = <0x58>;
>> > + };
>> > + };
>> > + };
>> > +};
>> > +
>> > +&i2c9 {
>> > + status = "okay";
>> > +};
>> > +
>> > +&vuart {
>> > + status = "okay";
>> > +};
>> > +
>> > +&gfx {
>> > + status = "okay";
>> > +};
>> > +
>> > +&pinctrl {
>> > + aspeed,external-nodes = <&gfx &lhc>;
>> > +};
>> > +
>> > +&gpio {
>> > + pin_gpio_c7 {
>> > + gpio-hog;
>> > + gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
>> > + output-low;
>> > + line-name = "BIOS_SPI_MUX_S";
>> > + };
>> > + pin_gpio_d1 {
>> > + gpio-hog;
>> > + gpios = <ASPEED_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
>> > + output-high;
>> > + line-name = "PHY2_RESET_N";
>> > + };
>> > +};
>> > --
>> > 1.8.3.1
>> >
>
>
^ permalink raw reply
* [PATCH v3] ARM: dts: aspeed: Adding Facebook TiogaPass BMC
From: Joel Stanley @ 2018-09-20 7:22 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20180918234110.1908926-1-vijaykhemka@fb.com>
Hello Vijay,
On Wed, 19 Sep 2018 at 09:11, Vijay Khemka <vijaykhemka@fb.com> wrote:
> Initial introduction of Facebook TiogaPass family equipped with
> Aspeed 2500 BMC SoC. TiogaPass is a x86 server development kit
> with a ASPEED ast2500 BMC manufactured by Facebook.
> Specifically, This adds the tiogapass platform device tree file
> including the flash layout used by the tiogapass BMC machines.
>
> This also adds an entry of tiogapass device tree file in Makefile
>
> Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
It looks like you've addressed the concerns from previous reviews. If
any comments come up please address them in follow up patches.
I made some minor whitespace fixes and applied this to the aspeed
v4.20 device tree branch.
Cheers,
Joel
^ permalink raw reply
* [PATCH v3] ARM: dts: aspeed: Adding Facebook TiogaPass BMC
From: Vijay Khemka @ 2018-09-18 23:41 UTC (permalink / raw)
To: linux-aspeed
Initial introduction of Facebook TiogaPass family equipped with
Aspeed 2500 BMC SoC. TiogaPass is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Facebook.
Specifically, This adds the tiogapass platform device tree file
including the flash layout used by the tiogapass BMC machines.
This also adds an entry of tiogapass device tree file in Makefile
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
---
arch/arm/boot/dts/Makefile | 1 +
.../dts/aspeed-bmc-facebook-tiogapass.dts | 146 ++++++++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b5bd3de87c33..1a2db605185a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1199,6 +1199,7 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
+ aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-opp-lanyang.dtb \
aspeed-bmc-opp-palmetto.dtb \
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
new file mode 100644
index 000000000000..050e72df8683
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2018 Facebook Inc.
+// Author: Vijay Khemka <vijaykhemka@fb.com>
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Facebook TiogaPass BMC";
+ compatible = "facebook,tiogapass-bmc", "aspeed,ast2500";
+ aliases {
+ serial0 = &uart1;
+ serial4 = &uart5;
+ };
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory at 80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ };
+};
+
+&uart1 {
+ // Host Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart5 {
+ // BMC Console
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&i2c0 {
+ status = "okay";
+ //Airmax Conn B, CPU0 PIROM, CPU1 PIROM
+};
+
+&i2c1 {
+ status = "okay";
+ //X24 Riser
+};
+
+&i2c2 {
+ status = "okay";
+ // Mezz Management SMBus
+};
+
+&i2c3 {
+ status = "okay";
+ // SMBus to Board ID EEPROM
+};
+
+&i2c4 {
+ status = "okay";
+ // BMC Debug Header
+};
+
+&i2c5 {
+ status = "okay";
+ //CPU Voltage regulators
+};
+
+&i2c6 {
+ status = "okay";
+ tpm at 20 {
+ compatible = "infineon,slb9645tt";
+ reg = <0x20>;
+ };
+ tmp421 at 4e {
+ compatible = "ti,tmp421";
+ reg = <0x4e>;
+ };
+ tmp421 at 4f {
+ compatible = "ti,tmp421";
+ reg = <0x4f>;
+ };
+ eeprom at 54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ pagesize = <32>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ //HSC, AirMax Conn A
+};
+
+&i2c8 {
+ status = "okay";
+ //Mezz Sensor SMBus
+};
+
+&i2c9 {
+ status = "okay";
+ //USB Debug Connector
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+ fan at 0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan at 1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+};
--
2.17.1
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