* [PATCH v2 3/4] media: dt-bindings: aspeed-video: Add missing memory-region property
From: Eddie James @ 2019-04-24 15:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556119020-7609-1-git-send-email-eajames@linux.ibm.com>
Missed documenting this property in the initial commit.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
Changes since v1:
- Add missing semi-colon
Documentation/devicetree/bindings/media/aspeed-video.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/aspeed-video.txt b/Documentation/devicetree/bindings/media/aspeed-video.txt
index 78b464a..ce28945 100644
--- a/Documentation/devicetree/bindings/media/aspeed-video.txt
+++ b/Documentation/devicetree/bindings/media/aspeed-video.txt
@@ -14,6 +14,11 @@ Required properties:
the VE
- interrupts: the interrupt associated with the VE on this platform
+Optional properties:
+ - memory-region:
+ phandle to a memory region to allocate from, as defined in
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
Example:
video-engine at 1e700000 {
@@ -23,4 +28,5 @@ video-engine at 1e700000 {
clock-names = "vclk", "eclk";
resets = <&syscon ASPEED_RESET_VIDEO>;
interrupts = <7>;
+ memory-region = <&video_engine_memory>;
};
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 2/4] media: platform: Aspeed: Make reserved memory optional
From: Eddie James @ 2019-04-24 15:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556119020-7609-1-git-send-email-eajames@linux.ibm.com>
Reserved memory doesn't need to be required; system memory would work
fine.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
drivers/media/platform/aspeed-video.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c
index 55c55a6..8144fe3 100644
--- a/drivers/media/platform/aspeed-video.c
+++ b/drivers/media/platform/aspeed-video.c
@@ -1608,11 +1608,7 @@ static int aspeed_video_init(struct aspeed_video *video)
return PTR_ERR(video->vclk);
}
- rc = of_reserved_mem_device_init(dev);
- if (rc) {
- dev_err(dev, "Unable to reserve memory\n");
- return rc;
- }
+ of_reserved_mem_device_init(dev);
rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (rc) {
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 1/4] media: platform: Aspeed: Remove use of reset line
From: Eddie James @ 2019-04-24 15:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556119020-7609-1-git-send-email-eajames@linux.ibm.com>
The reset line is toggled by enabling the clocks, so it's not necessary
to manually toggle the reset as well.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---
drivers/media/platform/aspeed-video.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c
index 692e08e..55c55a6 100644
--- a/drivers/media/platform/aspeed-video.c
+++ b/drivers/media/platform/aspeed-video.c
@@ -14,7 +14,6 @@
#include <linux/of_irq.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
-#include <linux/reset.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/string.h>
@@ -208,7 +207,6 @@ struct aspeed_video {
void __iomem *base;
struct clk *eclk;
struct clk *vclk;
- struct reset_control *rst;
struct device *dev;
struct v4l2_ctrl_handler ctrl_handler;
@@ -483,19 +481,10 @@ static void aspeed_video_enable_mode_detect(struct aspeed_video *video)
aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_TRIG_MODE_DET);
}
-static void aspeed_video_reset(struct aspeed_video *video)
-{
- /* Reset the engine */
- reset_control_assert(video->rst);
-
- /* Don't usleep here; function may be called in interrupt context */
- udelay(100);
- reset_control_deassert(video->rst);
-}
-
static void aspeed_video_off(struct aspeed_video *video)
{
- aspeed_video_reset(video);
+ /* Disable interrupts */
+ aspeed_video_write(video, VE_INTERRUPT_CTRL, 0);
/* Turn off the relevant clocks */
clk_disable_unprepare(video->vclk);
@@ -507,8 +496,6 @@ static void aspeed_video_on(struct aspeed_video *video)
/* Turn on the relevant clocks */
clk_prepare_enable(video->eclk);
clk_prepare_enable(video->vclk);
-
- aspeed_video_reset(video);
}
static void aspeed_video_bufs_done(struct aspeed_video *video,
@@ -1464,7 +1451,9 @@ static void aspeed_video_stop_streaming(struct vb2_queue *q)
* Need to force stop any DMA and try and get HW into a good
* state for future calls to start streaming again.
*/
- aspeed_video_reset(video);
+ aspeed_video_off(video);
+ aspeed_video_on(video);
+
aspeed_video_init_regs(video);
aspeed_video_get_resolution(video);
@@ -1619,12 +1608,6 @@ static int aspeed_video_init(struct aspeed_video *video)
return PTR_ERR(video->vclk);
}
- video->rst = devm_reset_control_get_exclusive(dev, NULL);
- if (IS_ERR(video->rst)) {
- dev_err(dev, "Unable to get VE reset\n");
- return PTR_ERR(video->rst);
- }
-
rc = of_reserved_mem_device_init(dev);
if (rc) {
dev_err(dev, "Unable to reserve memory\n");
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 0/4] Aspeed: Enable video engine
From: Eddie James @ 2019-04-24 15:16 UTC (permalink / raw)
To: linux-aspeed
This series enables the video engine on Aspeed BMC platforms. The use of the
video engine reset line, originally planned to be made externally available in
the clock driver, is removed from the video engine driver. A node for the video
engine is added to the AST2500 devicetree.
The series also includes a missing property for reserved memory in the
devicetree documentation, and a small change to make the video engine driver
start without reserved memory.
Changes since v1:
- Drop clock patch since it's been applied
- Add a missing semi-colon in the devicetree doc
Eddie James (4):
media: platform: Aspeed: Remove use of reset line
media: platform: Aspeed: Make reserved memory optional
media: dt-bindings: aspeed-video: Add missing memory-region property
ARM: dts: aspeed-g5: Add video engine
.../devicetree/bindings/media/aspeed-video.txt | 6 ++++
arch/arm/boot/dts/aspeed-g5.dtsi | 10 +++++++
drivers/media/platform/aspeed-video.c | 33 ++++------------------
3 files changed, 22 insertions(+), 27 deletions(-)
--
1.8.3.1
^ permalink raw reply
* [PATCH 0/5] Aspeed: Enable video engine
From: Eddie James @ 2019-04-24 15:00 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <b524e352-2e9d-6360-5517-18eee2e02c2c@xs4all.nl>
On 4/24/19 5:50 AM, Hans Verkuil wrote:
> Hi Eddie,
>
> On 4/2/19 8:24 PM, Eddie James wrote:
>> This series enables the video engine on Aspeed BMC platforms. The video engine
>> clocking is added to the Aspeed clock driver. The use of the video engine reset
>> line, originally planned to be made externally available in the clock driver,
>> is removed from the video engine driver. Finally a node for the video engine is
>> added to the AST2500 devicetree.
>> The series also includes a missing property for reserved memory in the
>> devicetree documentation, and a small change to make the video engine driver
>> start without reserved memory.
> I assume you'll post a v3 since there were some comments?
Sure... The only change would be a missing semi-colon in the devicetree
doc. And we're only on v2 :)
>
> If you want to get it in for 5.2, then be aware that you should post it tomorrow
> at the latest.
>
> Regards,
>
> Hans
>
>> Eddie James (5):
>> media: platform: Aspeed: Remove use of reset line
>> media: platform: Aspeed: Make reserved memory optional
>> media: dt-bindings: aspeed-video: Add missing memory-region property
>> clk: Aspeed: Setup video engine clocking
>> ARM: dts: aspeed-g5: Add video engine
>>
>> .../devicetree/bindings/media/aspeed-video.txt | 6 ++++
>> arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++
>> drivers/clk/clk-aspeed.c | 42 ++++++++++++++++++++--
>> drivers/media/platform/aspeed-video.c | 33 ++++-------------
>> 4 files changed, 61 insertions(+), 30 deletions(-)
>>
^ permalink raw reply
* [PATCH v3] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Patrick Venture @ 2019-04-24 14:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556108926-233682-1-git-send-email-pengms1@lenovo.com>
On Wed, Apr 24, 2019 at 5:29 AM Andrew Peng <pengms1@lenovo.com> wrote:
>
> Initial introduction of Lenovo Hr630 family equipped with
> Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
> with a ASPEED ast2500 BMC manufactured by Lenovo.
> Specifically, This adds the Hr630 platform device tree file
> used by the Hr630 BMC machines.
>
> This also adds an entry of Hr630 device tree file in Makefile
>
> Signed-off-by: Andrew Peng <pengms1@lenovo.com>
> Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
> Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
> ---
> Changes in v3:
> - revise i2c switch aliases name.
> Changes in v2:
> - add i2c switch aliases name.
> - remove the unused eeprom device from DT file.
> - remove "Licensed under..." sentence.
>
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 886 ++++++++++++++++++++++++++
> 2 files changed, 888 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f4f5aea..375e53b 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> aspeed-bmc-opp-witherspoon.dtb \
> aspeed-bmc-opp-zaius.dtb \
> aspeed-bmc-portwell-neptune.dtb \
> - aspeed-bmc-quanta-q71l.dtb
> + aspeed-bmc-quanta-q71l.dtb \
> + aspeed-bmc-lenovo-hr630.dtb
> diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
> new file mode 100644
> index 0000000..5c45523
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
> @@ -0,0 +1,886 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Device Tree file for Lenovo Hr630 platform
> + *
> + * Copyright (C) 2019-present Lenovo
> + */
> +
> +/dts-v1/;
> +
> +#include "aspeed-g5.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +
> +/ {
> + model = "HR630 BMC";
> + compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
> +
> + aliases {
> + pca9545_i2c0 = &i2c_rbp;
> + pca9545_i2c1 = &i2c_fbp1;
> + pca9545_i2c2 = &i2c_fbp2;
> + pca9545_i2c3 = &i2c_fbp3;
> + };
> +
> + chosen {
> + stdout-path = &uart5;
> + bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flash_memory: region at 98000000 {
> + no-map;
> + reg = <0x98000000 0x00100000>; /* 1M */
> + };
> +
> + gfx_memory: framebuffer {
> + size = <0x01000000>;
> + alignment = <0x01000000>;
> + compatible = "shared-dma-pool";
> + reusable;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + heartbeat {
> + gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
> + };
> +
> + fault {
> + gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + iio-hwmon {
> + compatible = "iio-hwmon";
> + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
> + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
> + <&adc 8>, <&adc 9>, <&adc 10>,
> + <&adc 12>, <&adc 13>, <&adc 14>;
> + };
> +
> +};
> +
> +&fmc {
> + status = "okay";
> + flash at 0 {
> + status = "okay";
> + m25p,fast-read;
> + label = "bmc";
> + spi-max-frequency = <50000000>;
> +#include "openbmc-flash-layout.dtsi"
> + };
> +};
> +
> +&lpc_ctrl {
> + status = "okay";
> + memory-region = <&flash_memory>;
> + flash = <&spi1>;
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&vuart {
> + status = "okay";
> +};
> +
> +&ibt {
> + status = "okay";
> +};
> +
> +&mac0 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rmii1_default>;
> + use-ncsi;
> +};
> +
> +&mac1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
> +};
> +
> +&adc {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + /* temp1 inlet */
> + tmp75 at 4e {
> + compatible = "national,lm75";
> + reg = <0x4e>;
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> + /* temp2 outlet */
> + tmp75 at 4d {
> + compatible = "national,lm75";
> + reg = <0x4d>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +};
> +
> +&i2c3 {
> + status = "okay";
> +};
> +
> +&i2c4 {
> + status = "okay";
> +};
> +
> +&i2c5 {
> + status = "okay";
> +};
> +
> +&i2c6 {
> + status = "okay";
> + /* Slot 0,
> + * Slot 1,
> + * Slot 2,
> + * Slot 3
> + */
> +
> + i2c-switch at 70 {
> + compatible = "nxp,pca9545";
> + reg = <0x70>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect; /* may use mux at 70 next. */
It's fine to leave mux-idle-disconnect, however the two muxes you're
worried about aren't competing under the same bus. This one lives
under i2c6 and the other i2c7, so they shouldn't interfere with each
other. Does that make sense? I missed this before because the window
only let me see part of a thing so I didn't see both in the same view
until I opened the patch in patchworks.
> +
> + i2c_rbp: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_fbp1: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_fbp2: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_fbp3: i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c7 {
> + status = "okay";
> +
> + /* Slot 0,
> + * Slot 1,
> + * Slot 2,
> + * Slot 3
> + */
> + i2c-switch at 76 {
> + compatible = "nxp,pca9546";
> + reg = <0x76>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect; /* may use mux at 76 next. */
> +
> + i2c_riser2: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_pcie4: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_riser1: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_ocp: i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c8 {
> + status = "okay";
> +
> + eeprom at 57 {
> + compatible = "atmel,24c256";
> + reg = <0x57>;
> + pagesize = <16>;
> + };
> +};
> +
> +&i2c9 {
> + status = "okay";
> +};
> +
> +&i2c10 {
> + status = "okay";
> +};
> +
> +&i2c11 {
> + status = "okay";
> +};
> +
> +&i2c12 {
> + status = "okay";
> +};
> +
> +/*
> + * Enable port A as device (via the virtual hub) and port B as
> + * host by default on the eval board. This can be easily changed
> + * by replacing the override below with &ehci0 { ... } to enable
> + * host on both ports.
> + */
> +&vhub {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&uhci {
> + status = "okay";
> +};
> +
> +&gfx {
> + status = "okay";
> + memory-region = <&gfx_memory>;
> +};
> +
> +&pwm_tacho {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm0_default
> + &pinctrl_pwm1_default
> + &pinctrl_pwm2_default
> + &pinctrl_pwm3_default
> + &pinctrl_pwm4_default
> + &pinctrl_pwm5_default
> + &pinctrl_pwm6_default>;
> +
> + fan at 0 {
> + reg = <0x00>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x00>;
> + };
> +
> + fan at 1 {
> + reg = <0x00>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x01>;
> + };
> +
> + fan at 2 {
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x02>;
> + };
> +
> + fan at 3 {
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x03>;
> + };
> +
> + fan at 4 {
> + reg = <0x02>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x04>;
> + };
> +
> + fan at 5 {
> + reg = <0x02>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x05>;
> + };
> +
> + fan at 6 {
> + reg = <0x03>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x06>;
> + };
> +
> + fan at 7 {
> + reg = <0x03>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x07>;
> + };
> +
> + fan at 8 {
> + reg = <0x04>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x08>;
> + };
> +
> + fan at 9 {
> + reg = <0x04>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x09>;
> + };
> +
> + fan at 10 {
> + reg = <0x05>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
> + };
> +
> + fan at 11 {
> + reg = <0x05>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
> + };
> +
> + fan at 12 {
> + reg = <0x06>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
> + };
> +
> + fan at 13 {
> + reg = <0x06>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
> + };
> +};
> +
> +&gpio {
> +
> + pin_gpio_a0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MAC1_INT_N";
> + };
> +
> + pin_gpio_a1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MEZZ_C_PRESENT_N";
> + };
> +
> + pin_gpio_a2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_PRST";
> + };
> +
> + pin_gpio_a3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_PRST";
> + };
> +
> + pin_gpio_b5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "IRQ_BMC_PCH_SMI_LPC_N";
> + };
> +
> + pin_gpio_f0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "IRQ_BMC_PCH_NMI_R";
> + };
> +
> + pin_gpio_f1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU1_DISABLE_COD_N";
> + };
> +
> + pin_gpio_f2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "SMB_LAN_ALERT_N_MEZZ";
> + };
> +
> + pin_gpio_f3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_BUS0_RST_OUT_N";
> + };
> +
> + pin_gpio_f4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "FM_SKT0_FAULT_LED";
> + };
> +
> + pin_gpio_f5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "FM_SKT1_FAULT_LED";
> + };
> +
> + pin_gpio_f6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_BMC_CPLD_NMI";
> + };
> +
> + pin_gpio_f7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_ALERT_N";
> + };
> +
> + pin_gpio_g0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU_ERR2_LVT3_N";
> + };
> +
> + pin_gpio_g1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
> + };
> +
> + pin_gpio_g2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PCH_BMC_THERMTRIP_N";
> + };
> +
> + pin_gpio_g3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_I2C_BUS7_INT_N";
> + };
> +
> + pin_gpio_g4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "FAN_PWR_CTL_N";
> + };
> +
> + pin_gpio_g5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "NFC_FD_N";
> + };
> +
> + pin_gpio_g6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_NMI_EVENT_N";
> + };
> +
> + pin_gpio_g7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "RST_BMC_PCIE_I2CMUX_N";
> + };
> +
> + pin_gpio_h0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_EPOW_N_R";
> + };
> +
> + pin_gpio_h1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_EPOW_N_R";
> + };
> +
> + pin_gpio_h2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PSU1_FFS_N_R";
> + };
> +
> + pin_gpio_h3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PSU2_FFS_N_R";
> + };
> +
> + pin_gpio_h4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_THROTTLE_N_R";
> + };
> +
> + pin_gpio_h5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_THROTTLE_N_R";
> + };
> +
> + pin_gpio_h6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_SMB_RESET_N";
> + };
> +
> + pin_gpio_h7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_SMB_RESET_N";
> + };
> +
> + pin_gpio_i1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FP_PWR_BTN_N";
> + };
> +
> + pin_gpio_i2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BIOS_RCVR_N";
> + };
> +
> + pin_gpio_i3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_INTRUDED_COVER";
> + };
> +
> + pin_gpio_j2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_BIOS_UPDATE_N";
> + };
> +
> + pin_gpio_j3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "RST_BMC_HDD_I2CMUX_N";
> + };
> +
> + pin_gpio_q4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MEZZ_A_PRESENT_N";
> + };
> +
> + pin_gpio_q5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "VGA_FRONT_PRES_N";
> + };
> +
> + pin_gpio_q6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "I2C_RISER1_INT_N";
> + };
> +
> + pin_gpio_q7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "NCSI_CABLE_DET_N";
> + };
> +
> + pin_gpio_r0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FP_RST_BTN_N";
> + };
> +
> + pin_gpio_r2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG1_DETECT_N";
> + };
> +
> + pin_gpio_r3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG2_DETECT_N";
> + };
> +
> + pin_gpio_r4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG3_DETECT_N";
> + };
> +
> + pin_gpio_r5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "VIDEO_CABLE_DETECT_N";
> + };
> +
> + pin_gpio_s0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_PS_RAPIDON_WAKE_R_N";
> + };
> +
> + pin_gpio_s1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HOST_TPM_PP_BUF";
> + };
> +
> + pin_gpio_s2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_VGA_SW";
> + };
> +
> + pin_gpio_s3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_SML0_ALERT_MUX_N";
> + };
> +
> + pin_gpio_s4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
> + output;
> + line-name = "VBAT_EN_N";
> + };
> +
> + pin_gpio_s5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_4";
> + };
> +
> + pin_gpio_s6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PU_BMC_GPIOS6";
> + };
> +
> + pin_gpio_s7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "I2C_BUS7_RESET_N";
> + };
> +
> + pin_gpio_y0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_NCSI_MUX_CTL_S0";
> + };
> +
> + pin_gpio_y1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_NCSI_MUX_CTL_S1";
> + };
> +
> + pin_gpio_y2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "UID_ALERT_N";
> + };
> +
> + pin_gpio_z0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_RISER2_INT_N";
> + };
> +
> + pin_gpio_z2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_RISER2_RESET_N";
> + };
> +
> + pin_gpio_z3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "FM_BMC_PCH_SCI_LPC_N";
> + };
> +
> + pin_gpio_z4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_17";
> + };
> +
> + pin_gpio_z6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_20";
> + };
> +
> + pin_gpio_z7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_POST_CMPLT_N";
> + };
> +
> + pin_gpio_aa0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "HOST_BMC_USB_SEL";
> + };
> +
> + pin_gpio_aa1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_ALERT_N";
> + };
> +
> + pin_gpio_aa2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
> + };
> +
> + pin_gpio_aa3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
> + };
> +
> + pin_gpio_aa4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "USB_CABLE_DETECT_N";
> + };
> +
> + pin_gpio_aa5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_BUS1_RST_OUT_N";
> + };
> +
> + pin_gpio_aa6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_SMI_ACTIVE_N";
> + };
> +
> + pin_gpio_aa7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_BIOS_POST_CMPLT_N";
> + };
> +
> + pin_gpio_ab0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_TPM_MOD_PRES_N";
> + };
> +
> + pin_gpio_ab1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FORCE_NMI_SW_FPGA_N";
> + };
> +
> + pin_gpio_ab2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "1U_2U_PCBA_SEL_R";
> + };
> +
> + pin_gpio_ab3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "INTRUDED_PRES_N";
> + };
> +};
This is my last comment.
Thanks,
Patrick
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Andrew Peng @ 2019-04-24 12:29 UTC (permalink / raw)
To: linux-aspeed
Initial introduction of Lenovo Hr630 family equipped with
Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Lenovo.
Specifically, This adds the Hr630 platform device tree file
used by the Hr630 BMC machines.
This also adds an entry of Hr630 device tree file in Makefile
Signed-off-by: Andrew Peng <pengms1@lenovo.com>
Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
---
Changes in v3:
- revise i2c switch aliases name.
Changes in v2:
- add i2c switch aliases name.
- remove the unused eeprom device from DT file.
- remove "Licensed under..." sentence.
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 886 ++++++++++++++++++++++++++
2 files changed, 888 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aea..375e53b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
- aspeed-bmc-quanta-q71l.dtb
+ aspeed-bmc-quanta-q71l.dtb \
+ aspeed-bmc-lenovo-hr630.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
new file mode 100644
index 0000000..5c45523
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -0,0 +1,886 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Lenovo Hr630 platform
+ *
+ * Copyright (C) 2019-present Lenovo
+ */
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "HR630 BMC";
+ compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
+
+ aliases {
+ pca9545_i2c0 = &i2c_rbp;
+ pca9545_i2c1 = &i2c_fbp1;
+ pca9545_i2c2 = &i2c_fbp2;
+ pca9545_i2c3 = &i2c_fbp3;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region at 98000000 {
+ no-map;
+ reg = <0x98000000 0x00100000>; /* 1M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ /* temp1 inlet */
+ tmp75 at 4e {
+ compatible = "national,lm75";
+ reg = <0x4e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ /* temp2 outlet */
+ tmp75 at 4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 70 next. */
+
+ i2c_rbp: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_fbp1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_fbp2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_fbp3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+ i2c-switch at 76 {
+ compatible = "nxp,pca9546";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 76 next. */
+
+ i2c_riser2: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_riser1: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_ocp: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom at 57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+/*
+ * Enable port A as device (via the virtual hub) and port B as
+ * host by default on the eval board. This can be easily changed
+ * by replacing the override below with &ehci0 { ... } to enable
+ * host on both ports.
+ */
+&vhub {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan at 0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan at 1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan at 2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan at 3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan at 4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan at 5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan at 6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan at 7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan at 8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan at 9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan at 10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan at 11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan at 12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan at 13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+};
+
+&gpio {
+
+ pin_gpio_a0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MAC1_INT_N";
+ };
+
+ pin_gpio_a1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_C_PRESENT_N";
+ };
+
+ pin_gpio_a2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_PRST";
+ };
+
+ pin_gpio_a3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_PRST";
+ };
+
+ pin_gpio_b5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "IRQ_BMC_PCH_SMI_LPC_N";
+ };
+
+ pin_gpio_f0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "IRQ_BMC_PCH_NMI_R";
+ };
+
+ pin_gpio_f1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU1_DISABLE_COD_N";
+ };
+
+ pin_gpio_f2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "SMB_LAN_ALERT_N_MEZZ";
+ };
+
+ pin_gpio_f3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS0_RST_OUT_N";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT0_FAULT_LED";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT1_FAULT_LED";
+ };
+
+ pin_gpio_f6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_BMC_CPLD_NMI";
+ };
+
+ pin_gpio_f7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_ALERT_N";
+ };
+
+ pin_gpio_g0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_ERR2_LVT3_N";
+ };
+
+ pin_gpio_g1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
+ };
+
+ pin_gpio_g2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PCH_BMC_THERMTRIP_N";
+ };
+
+ pin_gpio_g3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_I2C_BUS7_INT_N";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_PWR_CTL_N";
+ };
+
+ pin_gpio_g5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NFC_FD_N";
+ };
+
+ pin_gpio_g6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_NMI_EVENT_N";
+ };
+
+ pin_gpio_g7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_PCIE_I2CMUX_N";
+ };
+
+ pin_gpio_h0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_EPOW_N_R";
+ };
+
+ pin_gpio_h1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_EPOW_N_R";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU1_FFS_N_R";
+ };
+
+ pin_gpio_h3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU2_FFS_N_R";
+ };
+
+ pin_gpio_h4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_THROTTLE_N_R";
+ };
+
+ pin_gpio_h5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_THROTTLE_N_R";
+ };
+
+ pin_gpio_h6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_SMB_RESET_N";
+ };
+
+ pin_gpio_h7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_SMB_RESET_N";
+ };
+
+ pin_gpio_i1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_PWR_BTN_N";
+ };
+
+ pin_gpio_i2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BIOS_RCVR_N";
+ };
+
+ pin_gpio_i3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_INTRUDED_COVER";
+ };
+
+ pin_gpio_j2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_BIOS_UPDATE_N";
+ };
+
+ pin_gpio_j3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_HDD_I2CMUX_N";
+ };
+
+ pin_gpio_q4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_A_PRESENT_N";
+ };
+
+ pin_gpio_q5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VGA_FRONT_PRES_N";
+ };
+
+ pin_gpio_q6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_RISER1_INT_N";
+ };
+
+ pin_gpio_q7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NCSI_CABLE_DET_N";
+ };
+
+ pin_gpio_r0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_RST_BTN_N";
+ };
+
+ pin_gpio_r2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG1_DETECT_N";
+ };
+
+ pin_gpio_r3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG2_DETECT_N";
+ };
+
+ pin_gpio_r4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG3_DETECT_N";
+ };
+
+ pin_gpio_r5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VIDEO_CABLE_DETECT_N";
+ };
+
+ pin_gpio_s0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_PS_RAPIDON_WAKE_R_N";
+ };
+
+ pin_gpio_s1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HOST_TPM_PP_BUF";
+ };
+
+ pin_gpio_s2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_VGA_SW";
+ };
+
+ pin_gpio_s3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SML0_ALERT_MUX_N";
+ };
+
+ pin_gpio_s4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "VBAT_EN_N";
+ };
+
+ pin_gpio_s5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_4";
+ };
+
+ pin_gpio_s6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PU_BMC_GPIOS6";
+ };
+
+ pin_gpio_s7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_BUS7_RESET_N";
+ };
+
+ pin_gpio_y0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S0";
+ };
+
+ pin_gpio_y1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S1";
+ };
+
+ pin_gpio_y2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "UID_ALERT_N";
+ };
+
+ pin_gpio_z0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_INT_N";
+ };
+
+ pin_gpio_z2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_RESET_N";
+ };
+
+ pin_gpio_z3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FM_BMC_PCH_SCI_LPC_N";
+ };
+
+ pin_gpio_z4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_17";
+ };
+
+ pin_gpio_z6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_20";
+ };
+
+ pin_gpio_z7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_POST_CMPLT_N";
+ };
+
+ pin_gpio_aa0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "HOST_BMC_USB_SEL";
+ };
+
+ pin_gpio_aa1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_ALERT_N";
+ };
+
+ pin_gpio_aa2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "USB_CABLE_DETECT_N";
+ };
+
+ pin_gpio_aa5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS1_RST_OUT_N";
+ };
+
+ pin_gpio_aa6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SMI_ACTIVE_N";
+ };
+
+ pin_gpio_aa7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_BIOS_POST_CMPLT_N";
+ };
+
+ pin_gpio_ab0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_TPM_MOD_PRES_N";
+ };
+
+ pin_gpio_ab1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FORCE_NMI_SW_FPGA_N";
+ };
+
+ pin_gpio_ab2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "1U_2U_PCBA_SEL_R";
+ };
+
+ pin_gpio_ab3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "INTRUDED_PRES_N";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 0/5] Aspeed: Enable video engine
From: Hans Verkuil @ 2019-04-24 10:50 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1554229504-5661-1-git-send-email-eajames@linux.ibm.com>
Hi Eddie,
On 4/2/19 8:24 PM, Eddie James wrote:
> This series enables the video engine on Aspeed BMC platforms. The video engine
> clocking is added to the Aspeed clock driver. The use of the video engine reset
> line, originally planned to be made externally available in the clock driver,
> is removed from the video engine driver. Finally a node for the video engine is
> added to the AST2500 devicetree.
> The series also includes a missing property for reserved memory in the
> devicetree documentation, and a small change to make the video engine driver
> start without reserved memory.
I assume you'll post a v3 since there were some comments?
If you want to get it in for 5.2, then be aware that you should post it tomorrow
at the latest.
Regards,
Hans
>
> Eddie James (5):
> media: platform: Aspeed: Remove use of reset line
> media: platform: Aspeed: Make reserved memory optional
> media: dt-bindings: aspeed-video: Add missing memory-region property
> clk: Aspeed: Setup video engine clocking
> ARM: dts: aspeed-g5: Add video engine
>
> .../devicetree/bindings/media/aspeed-video.txt | 6 ++++
> arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++
> drivers/clk/clk-aspeed.c | 42 ++++++++++++++++++++--
> drivers/media/platform/aspeed-video.c | 33 ++++-------------
> 4 files changed, 61 insertions(+), 30 deletions(-)
>
^ permalink raw reply
* [PATCH] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-23 15:40 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAK8P3a24h=0JLZnZWOmzRqM70uhw3QZ_HcYDXST7F6TgSuW6YA@mail.gmail.com>
On Tue, Apr 23, 2019 at 8:33 AM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Tue, Apr 23, 2019 at 4:24 PM Patrick Venture <venture@google.com> wrote:
> >
> > On Tue, Apr 23, 2019 at 1:08 AM Arnd Bergmann <arnd@arndb.de> wrote:
> > >
> > > On Mon, Apr 22, 2019 at 7:38 PM Patrick Venture <venture@google.com> wrote:
> > > >
> > > > Create a SoC folder for the ASPEED parts and place the misc drivers
> > > > currently present into this folder. These drivers are not generic part
> > > > drivers, but rather only apply to the ASPEED SoCs.
> > > >
> > > > Signed-off-by: Patrick Venture <venture@google.com>
> > >
> > > Looks ok, but please resend to arm at kernel.org or soc at kernel.org
> > > so we can track the submission and make sure it gets applied if
> > > you want this to go through the arm-soc tree.
> >
> > Thanks, I didn't see those come up in the get_maintainers output.
> >
> > I had a longer question related to this patch progression -- if I am
> > moving the aspeed gpio driver to the soc folder, the soc tree may have
> > the soc/aspeed folder in their next, but the gpio tree wouldn't
> > necessarily. I know the branches sync up when things are merged at
> > the top, but I wasn't sure if there was another mechanism for this?
>
> We can generally deal with merge conflicts like this, or you can ask
> the respective maintainers about it and let us figure something out.
Thanks for explaining that.
>
> In this particular case, why would you move the gpio driver into
> the soc folder? If there is a proper subsystem for a driver, it should
> not be in drivers/misc or drivers/soc.
Ok, that makes sense. I was trying to get a sense of what belonged in
soc versus the subsystem folders. My thinking from the limited
reading was the purpose of a SoC folder was to contain the drivers
that were only associated with a system-on-a-chip and not a part you
could buy and place on any board. A tmp421 sensor is just a generic
part, versus the pwm controller, which is only for the specific SoCs.
That said, there are quite a few misc drivers associated with the
Aspeed parts -- and there are two under review now, so there's a
strong motivation to move those at least into the soc/aspeed folder.
Thanks for these clarifying remarks.
>
> Arnd
^ permalink raw reply
* [PATCH] soc: add aspeed folder and misc drivers
From: Arnd Bergmann @ 2019-04-23 15:33 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAO=notxuYsBzWBnNran5jH0RujSBeti6-HsjasCRP6Sq0MwGNA@mail.gmail.com>
On Tue, Apr 23, 2019 at 4:24 PM Patrick Venture <venture@google.com> wrote:
>
> On Tue, Apr 23, 2019 at 1:08 AM Arnd Bergmann <arnd@arndb.de> wrote:
> >
> > On Mon, Apr 22, 2019 at 7:38 PM Patrick Venture <venture@google.com> wrote:
> > >
> > > Create a SoC folder for the ASPEED parts and place the misc drivers
> > > currently present into this folder. These drivers are not generic part
> > > drivers, but rather only apply to the ASPEED SoCs.
> > >
> > > Signed-off-by: Patrick Venture <venture@google.com>
> >
> > Looks ok, but please resend to arm at kernel.org or soc at kernel.org
> > so we can track the submission and make sure it gets applied if
> > you want this to go through the arm-soc tree.
>
> Thanks, I didn't see those come up in the get_maintainers output.
>
> I had a longer question related to this patch progression -- if I am
> moving the aspeed gpio driver to the soc folder, the soc tree may have
> the soc/aspeed folder in their next, but the gpio tree wouldn't
> necessarily. I know the branches sync up when things are merged at
> the top, but I wasn't sure if there was another mechanism for this?
We can generally deal with merge conflicts like this, or you can ask
the respective maintainers about it and let us figure something out.
In this particular case, why would you move the gpio driver into
the soc folder? If there is a proper subsystem for a driver, it should
not be in drivers/misc or drivers/soc.
Arnd
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-23 15:28 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAO=notzjzpt0WHfJEWXMGgkoJU8UiLnqZnrGrPs-dRH5GNdJyQ@mail.gmail.com>
On Tue, Apr 23, 2019 at 8:22 AM Patrick Venture <venture@google.com> wrote:
>
> On Tue, Apr 23, 2019 at 7:26 AM Patrick Venture <venture@google.com> wrote:
> >
> > Create a SoC folder for the ASPEED parts and place the misc drivers
> > currently present into this folder. These drivers are not generic part
> > drivers, but rather only apply to the ASPEED SoCs.
> >
> > Signed-off-by: Patrick Venture <venture@google.com>
>
> Accidentally lost the Acked-by when re-sending this patchset as I
> didn't see it on v1 before re-sending v2 to the larger audience.
Since there was a change between v1 and v2, Arnd, I'd appreciate you
Ack this version of the patchset since it changes when the soc/aspeed
Makefile is followed.
>
> > ---
> > v2:
> > Added configuration option for ASPEED to soc/Makefile
> > ---
> > drivers/misc/Kconfig | 16 ----------------
> > drivers/misc/Makefile | 2 --
> > drivers/soc/Kconfig | 1 +
> > drivers/soc/Makefile | 1 +
> > drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
> > drivers/soc/aspeed/Makefile | 2 ++
> > .../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
> > .../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
> > 8 files changed, 23 insertions(+), 18 deletions(-)
> > create mode 100644 drivers/soc/aspeed/Kconfig
> > create mode 100644 drivers/soc/aspeed/Makefile
> > rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
> > rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> > index 42ab8ec92a04..b80cb6af0cb4 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
> > bus. System Configuration interface is one of the possible means
> > of generating transactions on this bus.
> >
> > -config ASPEED_LPC_CTRL
> > - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > - tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> > - ---help---
> > - Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> > - ioctl()s, the driver also provides a read/write interface to a BMC ram
> > - region where the host LPC read/write region can be buffered.
> > -
> > -config ASPEED_LPC_SNOOP
> > - tristate "Aspeed ast2500 HOST LPC snoop support"
> > - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > - help
> > - Provides a driver to control the LPC snoop interface which
> > - allows the BMC to listen on and save the data written by
> > - the host to an arbitrary LPC I/O port.
> > -
> > config PCI_ENDPOINT_TEST
> > depends on PCI
> > select CRC32
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> > index d5b7d3404dc7..b9affcdaa3d6 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
> > obj-$(CONFIG_ECHO) += echo/
> > obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
> > obj-$(CONFIG_CXL_BASE) += cxl/
> > -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> > -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> > obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
> > obj-$(CONFIG_OCXL) += ocxl/
> > obj-y += cardreader/
> > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> > index c07b4a85253f..b750a88547c7 100644
> > --- a/drivers/soc/Kconfig
> > +++ b/drivers/soc/Kconfig
> > @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
> >
> > source "drivers/soc/actions/Kconfig"
> > source "drivers/soc/amlogic/Kconfig"
> > +source "drivers/soc/aspeed/Kconfig"
> > source "drivers/soc/atmel/Kconfig"
> > source "drivers/soc/bcm/Kconfig"
> > source "drivers/soc/fsl/Kconfig"
> > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> > index 90b686e586c6..814128fe479f 100644
> > --- a/drivers/soc/Makefile
> > +++ b/drivers/soc/Makefile
> > @@ -4,6 +4,7 @@
> > #
> >
> > obj-$(CONFIG_ARCH_ACTIONS) += actions/
> > +obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> > obj-$(CONFIG_ARCH_AT91) += atmel/
> > obj-y += bcm/
> > obj-$(CONFIG_ARCH_DOVE) += dove/
> > diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
> > new file mode 100644
> > index 000000000000..457282cd1da5
> > --- /dev/null
> > +++ b/drivers/soc/aspeed/Kconfig
> > @@ -0,0 +1,19 @@
> > +menu "Aspeed SoC drivers"
> > +
> > +config ASPEED_LPC_CTRL
> > + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > + tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> > + ---help---
> > + Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> > + ioctl()s, the driver also provides a read/write interface to a BMC ram
> > + region where the host LPC read/write region can be buffered.
> > +
> > +config ASPEED_LPC_SNOOP
> > + tristate "Aspeed ast2500 HOST LPC snoop support"
> > + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > + help
> > + Provides a driver to control the LPC snoop interface which
> > + allows the BMC to listen on and save the data written by
> > + the host to an arbitrary LPC I/O port.
> > +
> > +
> > diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
> > new file mode 100644
> > index 000000000000..cfaa9adc67b5
> > --- /dev/null
> > +++ b/drivers/soc/aspeed/Makefile
> > @@ -0,0 +1,2 @@
> > +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> > +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> > diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
> > similarity index 100%
> > rename from drivers/misc/aspeed-lpc-ctrl.c
> > rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
> > diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
> > similarity index 100%
> > rename from drivers/misc/aspeed-lpc-snoop.c
> > rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
> > --
> > 2.21.0.593.g511ec345e18-goog
> >
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-23 15:22 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190423142629.120717-1-venture@google.com>
On Tue, Apr 23, 2019 at 7:26 AM Patrick Venture <venture@google.com> wrote:
>
> Create a SoC folder for the ASPEED parts and place the misc drivers
> currently present into this folder. These drivers are not generic part
> drivers, but rather only apply to the ASPEED SoCs.
>
> Signed-off-by: Patrick Venture <venture@google.com>
Accidentally lost the Acked-by when re-sending this patchset as I
didn't see it on v1 before re-sending v2 to the larger audience.
> ---
> v2:
> Added configuration option for ASPEED to soc/Makefile
> ---
> drivers/misc/Kconfig | 16 ----------------
> drivers/misc/Makefile | 2 --
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
> drivers/soc/aspeed/Makefile | 2 ++
> .../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
> .../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
> 8 files changed, 23 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/aspeed/Kconfig
> create mode 100644 drivers/soc/aspeed/Makefile
> rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
> rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 42ab8ec92a04..b80cb6af0cb4 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
> bus. System Configuration interface is one of the possible means
> of generating transactions on this bus.
>
> -config ASPEED_LPC_CTRL
> - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> - tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> - ---help---
> - Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> - ioctl()s, the driver also provides a read/write interface to a BMC ram
> - region where the host LPC read/write region can be buffered.
> -
> -config ASPEED_LPC_SNOOP
> - tristate "Aspeed ast2500 HOST LPC snoop support"
> - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> - help
> - Provides a driver to control the LPC snoop interface which
> - allows the BMC to listen on and save the data written by
> - the host to an arbitrary LPC I/O port.
> -
> config PCI_ENDPOINT_TEST
> depends on PCI
> select CRC32
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index d5b7d3404dc7..b9affcdaa3d6 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
> obj-$(CONFIG_ECHO) += echo/
> obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
> obj-$(CONFIG_CXL_BASE) += cxl/
> -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
> obj-$(CONFIG_OCXL) += ocxl/
> obj-y += cardreader/
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index c07b4a85253f..b750a88547c7 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
>
> source "drivers/soc/actions/Kconfig"
> source "drivers/soc/amlogic/Kconfig"
> +source "drivers/soc/aspeed/Kconfig"
> source "drivers/soc/atmel/Kconfig"
> source "drivers/soc/bcm/Kconfig"
> source "drivers/soc/fsl/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 90b686e586c6..814128fe479f 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -4,6 +4,7 @@
> #
>
> obj-$(CONFIG_ARCH_ACTIONS) += actions/
> +obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> obj-$(CONFIG_ARCH_AT91) += atmel/
> obj-y += bcm/
> obj-$(CONFIG_ARCH_DOVE) += dove/
> diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
> new file mode 100644
> index 000000000000..457282cd1da5
> --- /dev/null
> +++ b/drivers/soc/aspeed/Kconfig
> @@ -0,0 +1,19 @@
> +menu "Aspeed SoC drivers"
> +
> +config ASPEED_LPC_CTRL
> + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> + tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> + ---help---
> + Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> + ioctl()s, the driver also provides a read/write interface to a BMC ram
> + region where the host LPC read/write region can be buffered.
> +
> +config ASPEED_LPC_SNOOP
> + tristate "Aspeed ast2500 HOST LPC snoop support"
> + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> + help
> + Provides a driver to control the LPC snoop interface which
> + allows the BMC to listen on and save the data written by
> + the host to an arbitrary LPC I/O port.
> +
> +
> diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
> new file mode 100644
> index 000000000000..cfaa9adc67b5
> --- /dev/null
> +++ b/drivers/soc/aspeed/Makefile
> @@ -0,0 +1,2 @@
> +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
> similarity index 100%
> rename from drivers/misc/aspeed-lpc-ctrl.c
> rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
> diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
> similarity index 100%
> rename from drivers/misc/aspeed-lpc-snoop.c
> rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
> --
> 2.21.0.593.g511ec345e18-goog
>
^ permalink raw reply
* [PATCH v2] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Patrick Venture @ 2019-04-23 14:31 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556020484-440225-1-git-send-email-pengms1@lenovo.com>
On Tue, Apr 23, 2019 at 4:55 AM Andrew Peng <pengms1@lenovo.com> wrote:
>
> Initial introduction of Lenovo Hr630 family equipped with
> Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
> with a ASPEED ast2500 BMC manufactured by Lenovo.
> Specifically, This adds the Hr630 platform device tree file
> used by the Hr630 BMC machines.
>
> This also adds an entry of Hr630 device tree file in Makefile
>
> Signed-off-by: Andrew Peng <pengms1@lenovo.com>
> Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
> Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
In the future, or in the next version, please add a section here
explaining what changed. You can look at other v2 or v3, etc, to see
how it should appear.
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 886 ++++++++++++++++++++++++++
> 2 files changed, 888 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f4f5aea..375e53b 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> aspeed-bmc-opp-witherspoon.dtb \
> aspeed-bmc-opp-zaius.dtb \
> aspeed-bmc-portwell-neptune.dtb \
> - aspeed-bmc-quanta-q71l.dtb
> + aspeed-bmc-quanta-q71l.dtb \
> + aspeed-bmc-lenovo-hr630.dtb
> diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
> new file mode 100644
> index 0000000..3322f83
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
> @@ -0,0 +1,886 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Device Tree file for Lenovo Hr630 platform
> + *
> + * Copyright (C) 2019-present Lenovo
> + */
> +
> +/dts-v1/;
> +
> +#include "aspeed-g5.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +
> +/ {
> + model = "HR630 BMC";
> + compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
> +
> + aliases {
> + i2c_rbp = &i2c_rbp;
> + i2c_fbp1 = &i2c_fbp1;
> + i2c_fbp2 = &i2c_fbp2;
> + i2c_fbp3 = &i2c_fbp3;
> + };
These aliases don't do anything that I can see - they are assigning
themselves to themselves. I was referring to the i2c bus numbers.
For instance:
i2c14 = &ic2_rbp;
That will insure that i2c_rbp will be slotted as i2c14.
> +
> + chosen {
> + stdout-path = &uart5;
> + bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flash_memory: region at 98000000 {
> + no-map;
> + reg = <0x98000000 0x00100000>; /* 1M */
> + };
> +
> + gfx_memory: framebuffer {
> + size = <0x01000000>;
> + alignment = <0x01000000>;
> + compatible = "shared-dma-pool";
> + reusable;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + heartbeat {
> + gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
> + };
> +
> + fault {
> + gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + iio-hwmon {
> + compatible = "iio-hwmon";
> + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
> + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
> + <&adc 8>, <&adc 9>, <&adc 10>,
> + <&adc 12>, <&adc 13>, <&adc 14>;
> + };
> +
> +};
> +
> +&fmc {
> + status = "okay";
> + flash at 0 {
> + status = "okay";
> + m25p,fast-read;
> + label = "bmc";
> + spi-max-frequency = <50000000>;
> +#include "openbmc-flash-layout.dtsi"
> + };
> +};
> +
> +&lpc_ctrl {
> + status = "okay";
> + memory-region = <&flash_memory>;
> + flash = <&spi1>;
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&vuart {
> + status = "okay";
> +};
> +
> +&ibt {
> + status = "okay";
> +};
> +
> +&mac0 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rmii1_default>;
> + use-ncsi;
> +};
> +
> +&mac1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
> +};
> +
> +&adc {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + /* temp1 inlet */
> + tmp75 at 4e {
> + compatible = "national,lm75";
> + reg = <0x4e>;
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> + /* temp2 outlet */
> + tmp75 at 4d {
> + compatible = "national,lm75";
> + reg = <0x4d>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +};
> +
> +&i2c3 {
> + status = "okay";
> +};
> +
> +&i2c4 {
> + status = "okay";
> +};
> +
> +&i2c5 {
> + status = "okay";
> +};
> +
> +&i2c6 {
> + status = "okay";
> + /* Slot 0,
> + * Slot 1,
> + * Slot 2,
> + * Slot 3
> + */
> +
> + i2c-switch at 70 {
> + compatible = "nxp,pca9545";
> + reg = <0x70>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect; /* may use mux at 70 next. */
> +
> + i2c_rbp: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_fbp1: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_fbp2: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_fbp3: i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c7 {
> + status = "okay";
> +
> + /* Slot 0,
> + * Slot 1,
> + * Slot 2,
> + * Slot 3
> + */
> + i2c-switch at 76 {
> + compatible = "nxp,pca9546";
> + reg = <0x76>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect; /* may use mux at 76 next. */
> +
> + i2c_riser2: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_pcie4: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_riser1: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_ocp: i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c8 {
> + status = "okay";
> +
> + eeprom at 57 {
> + compatible = "atmel,24c256";
> + reg = <0x57>;
> + pagesize = <16>;
> + };
> +};
> +
> +&i2c9 {
> + status = "okay";
> +};
> +
> +&i2c10 {
> + status = "okay";
> +};
> +
> +&i2c11 {
> + status = "okay";
> +};
> +
> +&i2c12 {
> + status = "okay";
> +};
> +
> +/*
> + * Enable port A as device (via the virtual hub) and port B as
> + * host by default on the eval board. This can be easily changed
> + * by replacing the override below with &ehci0 { ... } to enable
> + * host on both ports.
> + */
> +&vhub {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&uhci {
> + status = "okay";
> +};
> +
> +&gfx {
> + status = "okay";
> + memory-region = <&gfx_memory>;
> +};
> +
> +&pwm_tacho {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm0_default
> + &pinctrl_pwm1_default
> + &pinctrl_pwm2_default
> + &pinctrl_pwm3_default
> + &pinctrl_pwm4_default
> + &pinctrl_pwm5_default
> + &pinctrl_pwm6_default>;
> +
> + fan at 0 {
> + reg = <0x00>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x00>;
> + };
> +
> + fan at 1 {
> + reg = <0x00>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x01>;
> + };
> +
> + fan at 2 {
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x02>;
> + };
> +
> + fan at 3 {
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x03>;
> + };
> +
> + fan at 4 {
> + reg = <0x02>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x04>;
> + };
> +
> + fan at 5 {
> + reg = <0x02>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x05>;
> + };
> +
> + fan at 6 {
> + reg = <0x03>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x06>;
> + };
> +
> + fan at 7 {
> + reg = <0x03>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x07>;
> + };
> +
> + fan at 8 {
> + reg = <0x04>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x08>;
> + };
> +
> + fan at 9 {
> + reg = <0x04>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x09>;
> + };
> +
> + fan at 10 {
> + reg = <0x05>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
> + };
> +
> + fan at 11 {
> + reg = <0x05>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
> + };
> +
> + fan at 12 {
> + reg = <0x06>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
> + };
> +
> + fan at 13 {
> + reg = <0x06>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
> + };
> +};
> +
> +&gpio {
> +
> + pin_gpio_a0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MAC1_INT_N";
> + };
> +
> + pin_gpio_a1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MEZZ_C_PRESENT_N";
> + };
> +
> + pin_gpio_a2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_PRST";
> + };
> +
> + pin_gpio_a3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_PRST";
> + };
> +
> + pin_gpio_b5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "IRQ_BMC_PCH_SMI_LPC_N";
> + };
> +
> + pin_gpio_f0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "IRQ_BMC_PCH_NMI_R";
> + };
> +
> + pin_gpio_f1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU1_DISABLE_COD_N";
> + };
> +
> + pin_gpio_f2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "SMB_LAN_ALERT_N_MEZZ";
> + };
> +
> + pin_gpio_f3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_BUS0_RST_OUT_N";
> + };
> +
> + pin_gpio_f4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "FM_SKT0_FAULT_LED";
> + };
> +
> + pin_gpio_f5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "FM_SKT1_FAULT_LED";
> + };
> +
> + pin_gpio_f6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_BMC_CPLD_NMI";
> + };
> +
> + pin_gpio_f7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_ALERT_N";
> + };
> +
> + pin_gpio_g0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU_ERR2_LVT3_N";
> + };
> +
> + pin_gpio_g1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
> + };
> +
> + pin_gpio_g2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PCH_BMC_THERMTRIP_N";
> + };
> +
> + pin_gpio_g3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_I2C_BUS7_INT_N";
> + };
> +
> + pin_gpio_g4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "FAN_PWR_CTL_N";
> + };
> +
> + pin_gpio_g5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "NFC_FD_N";
> + };
> +
> + pin_gpio_g6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_NMI_EVENT_N";
> + };
> +
> + pin_gpio_g7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "RST_BMC_PCIE_I2CMUX_N";
> + };
> +
> + pin_gpio_h0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_EPOW_N_R";
> + };
> +
> + pin_gpio_h1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_EPOW_N_R";
> + };
> +
> + pin_gpio_h2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PSU1_FFS_N_R";
> + };
> +
> + pin_gpio_h3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PSU2_FFS_N_R";
> + };
> +
> + pin_gpio_h4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_THROTTLE_N_R";
> + };
> +
> + pin_gpio_h5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_THROTTLE_N_R";
> + };
> +
> + pin_gpio_h6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_SMB_RESET_N";
> + };
> +
> + pin_gpio_h7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_SMB_RESET_N";
> + };
> +
> + pin_gpio_i1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FP_PWR_BTN_N";
> + };
> +
> + pin_gpio_i2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BIOS_RCVR_N";
> + };
> +
> + pin_gpio_i3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_INTRUDED_COVER";
> + };
> +
> + pin_gpio_j2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_BIOS_UPDATE_N";
> + };
> +
> + pin_gpio_j3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "RST_BMC_HDD_I2CMUX_N";
> + };
> +
> + pin_gpio_q4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MEZZ_A_PRESENT_N";
> + };
> +
> + pin_gpio_q5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "VGA_FRONT_PRES_N";
> + };
> +
> + pin_gpio_q6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "I2C_RISER1_INT_N";
> + };
> +
> + pin_gpio_q7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "NCSI_CABLE_DET_N";
> + };
> +
> + pin_gpio_r0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FP_RST_BTN_N";
> + };
> +
> + pin_gpio_r2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG1_DETECT_N";
> + };
> +
> + pin_gpio_r3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG2_DETECT_N";
> + };
> +
> + pin_gpio_r4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG3_DETECT_N";
> + };
> +
> + pin_gpio_r5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "VIDEO_CABLE_DETECT_N";
> + };
> +
> + pin_gpio_s0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_PS_RAPIDON_WAKE_R_N";
> + };
> +
> + pin_gpio_s1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HOST_TPM_PP_BUF";
> + };
> +
> + pin_gpio_s2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_VGA_SW";
> + };
> +
> + pin_gpio_s3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_SML0_ALERT_MUX_N";
> + };
> +
> + pin_gpio_s4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
> + output;
> + line-name = "VBAT_EN_N";
> + };
> +
> + pin_gpio_s5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_4";
> + };
> +
> + pin_gpio_s6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PU_BMC_GPIOS6";
> + };
> +
> + pin_gpio_s7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "I2C_BUS7_RESET_N";
> + };
> +
> + pin_gpio_y0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_NCSI_MUX_CTL_S0";
> + };
> +
> + pin_gpio_y1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_NCSI_MUX_CTL_S1";
> + };
> +
> + pin_gpio_y2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "UID_ALERT_N";
> + };
> +
> + pin_gpio_z0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_RISER2_INT_N";
> + };
> +
> + pin_gpio_z2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_RISER2_RESET_N";
> + };
> +
> + pin_gpio_z3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "FM_BMC_PCH_SCI_LPC_N";
> + };
> +
> + pin_gpio_z4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_17";
> + };
> +
> + pin_gpio_z6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_20";
> + };
> +
> + pin_gpio_z7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_POST_CMPLT_N";
> + };
> +
> + pin_gpio_aa0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "HOST_BMC_USB_SEL";
> + };
> +
> + pin_gpio_aa1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_ALERT_N";
> + };
> +
> + pin_gpio_aa2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
> + };
> +
> + pin_gpio_aa3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
> + };
> +
> + pin_gpio_aa4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "USB_CABLE_DETECT_N";
> + };
> +
> + pin_gpio_aa5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_BUS1_RST_OUT_N";
> + };
> +
> + pin_gpio_aa6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_SMI_ACTIVE_N";
> + };
> +
> + pin_gpio_aa7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_BIOS_POST_CMPLT_N";
> + };
> +
> + pin_gpio_ab0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_TPM_MOD_PRES_N";
> + };
> +
> + pin_gpio_ab1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FORCE_NMI_SW_FPGA_N";
> + };
> +
> + pin_gpio_ab2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "1U_2U_PCBA_SEL_R";
> + };
> +
> + pin_gpio_ab3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "INTRUDED_PRES_N";
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-23 14:26 UTC (permalink / raw)
To: linux-aspeed
Create a SoC folder for the ASPEED parts and place the misc drivers
currently present into this folder. These drivers are not generic part
drivers, but rather only apply to the ASPEED SoCs.
Signed-off-by: Patrick Venture <venture@google.com>
---
v2:
Added configuration option for ASPEED to soc/Makefile
---
drivers/misc/Kconfig | 16 ----------------
drivers/misc/Makefile | 2 --
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
drivers/soc/aspeed/Makefile | 2 ++
.../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
.../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
8 files changed, 23 insertions(+), 18 deletions(-)
create mode 100644 drivers/soc/aspeed/Kconfig
create mode 100644 drivers/soc/aspeed/Makefile
rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 42ab8ec92a04..b80cb6af0cb4 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
bus. System Configuration interface is one of the possible means
of generating transactions on this bus.
-config ASPEED_LPC_CTRL
- depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
- tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
- ---help---
- Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
- ioctl()s, the driver also provides a read/write interface to a BMC ram
- region where the host LPC read/write region can be buffered.
-
-config ASPEED_LPC_SNOOP
- tristate "Aspeed ast2500 HOST LPC snoop support"
- depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
- help
- Provides a driver to control the LPC snoop interface which
- allows the BMC to listen on and save the data written by
- the host to an arbitrary LPC I/O port.
-
config PCI_ENDPOINT_TEST
depends on PCI
select CRC32
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d5b7d3404dc7..b9affcdaa3d6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
-obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
-obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
obj-$(CONFIG_OCXL) += ocxl/
obj-y += cardreader/
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index c07b4a85253f..b750a88547c7 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
source "drivers/soc/amlogic/Kconfig"
+source "drivers/soc/aspeed/Kconfig"
source "drivers/soc/atmel/Kconfig"
source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 90b686e586c6..814128fe479f 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
obj-y += bcm/
obj-$(CONFIG_ARCH_DOVE) += dove/
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
new file mode 100644
index 000000000000..457282cd1da5
--- /dev/null
+++ b/drivers/soc/aspeed/Kconfig
@@ -0,0 +1,19 @@
+menu "Aspeed SoC drivers"
+
+config ASPEED_LPC_CTRL
+ depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
+ tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
+ ---help---
+ Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
+ ioctl()s, the driver also provides a read/write interface to a BMC ram
+ region where the host LPC read/write region can be buffered.
+
+config ASPEED_LPC_SNOOP
+ tristate "Aspeed ast2500 HOST LPC snoop support"
+ depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
+ help
+ Provides a driver to control the LPC snoop interface which
+ allows the BMC to listen on and save the data written by
+ the host to an arbitrary LPC I/O port.
+
+
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
new file mode 100644
index 000000000000..cfaa9adc67b5
--- /dev/null
+++ b/drivers/soc/aspeed/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
similarity index 100%
rename from drivers/misc/aspeed-lpc-ctrl.c
rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
similarity index 100%
rename from drivers/misc/aspeed-lpc-snoop.c
rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [PATCH] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-23 14:24 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAK8P3a0k_8+R9FeyZsL6Egvi1Z-G0VrvR0TWXzGHryqxTr6thg@mail.gmail.com>
On Tue, Apr 23, 2019 at 1:08 AM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Mon, Apr 22, 2019 at 7:38 PM Patrick Venture <venture@google.com> wrote:
> >
> > Create a SoC folder for the ASPEED parts and place the misc drivers
> > currently present into this folder. These drivers are not generic part
> > drivers, but rather only apply to the ASPEED SoCs.
> >
> > Signed-off-by: Patrick Venture <venture@google.com>
>
> Looks ok, but please resend to arm at kernel.org or soc at kernel.org
> so we can track the submission and make sure it gets applied if
> you want this to go through the arm-soc tree.
Thanks, I didn't see those come up in the get_maintainers output.
I had a longer question related to this patch progression -- if I am
moving the aspeed gpio driver to the soc folder, the soc tree may have
the soc/aspeed folder in their next, but the gpio tree wouldn't
necessarily. I know the branches sync up when things are merged at
the top, but I wasn't sure if there was another mechanism for this?
>
> If Greg wants to pick it up, that's fine too.
>
> Either way,
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> > ---
> > drivers/misc/Kconfig | 16 ----------------
> > drivers/misc/Makefile | 2 --
> > drivers/soc/Kconfig | 1 +
> > drivers/soc/Makefile | 1 +
> > drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
> > drivers/soc/aspeed/Makefile | 2 ++
> > .../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
> > .../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
> > 8 files changed, 23 insertions(+), 18 deletions(-)
> > create mode 100644 drivers/soc/aspeed/Kconfig
> > create mode 100644 drivers/soc/aspeed/Makefile
> > rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
> > rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> > index 42ab8ec92a04..b80cb6af0cb4 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
> > bus. System Configuration interface is one of the possible means
> > of generating transactions on this bus.
> >
> > -config ASPEED_LPC_CTRL
> > - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > - tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> > - ---help---
> > - Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> > - ioctl()s, the driver also provides a read/write interface to a BMC ram
> > - region where the host LPC read/write region can be buffered.
> > -
> > -config ASPEED_LPC_SNOOP
> > - tristate "Aspeed ast2500 HOST LPC snoop support"
> > - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > - help
> > - Provides a driver to control the LPC snoop interface which
> > - allows the BMC to listen on and save the data written by
> > - the host to an arbitrary LPC I/O port.
> > -
> > config PCI_ENDPOINT_TEST
> > depends on PCI
> > select CRC32
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> > index d5b7d3404dc7..b9affcdaa3d6 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
> > obj-$(CONFIG_ECHO) += echo/
> > obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
> > obj-$(CONFIG_CXL_BASE) += cxl/
> > -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> > -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> > obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
> > obj-$(CONFIG_OCXL) += ocxl/
> > obj-y += cardreader/
> > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> > index c07b4a85253f..b750a88547c7 100644
> > --- a/drivers/soc/Kconfig
> > +++ b/drivers/soc/Kconfig
> > @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
> >
> > source "drivers/soc/actions/Kconfig"
> > source "drivers/soc/amlogic/Kconfig"
> > +source "drivers/soc/aspeed/Kconfig"
> > source "drivers/soc/atmel/Kconfig"
> > source "drivers/soc/bcm/Kconfig"
> > source "drivers/soc/fsl/Kconfig"
> > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> > index 90b686e586c6..83a032db3e44 100644
> > --- a/drivers/soc/Makefile
> > +++ b/drivers/soc/Makefile
> > @@ -4,6 +4,7 @@
> > #
> >
> > obj-$(CONFIG_ARCH_ACTIONS) += actions/
> > +obj-y += aspeed/
> > obj-$(CONFIG_ARCH_AT91) += atmel/
> > obj-y += bcm/
> > obj-$(CONFIG_ARCH_DOVE) += dove/
> > diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
> > new file mode 100644
> > index 000000000000..457282cd1da5
> > --- /dev/null
> > +++ b/drivers/soc/aspeed/Kconfig
> > @@ -0,0 +1,19 @@
> > +menu "Aspeed SoC drivers"
> > +
> > +config ASPEED_LPC_CTRL
> > + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > + tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> > + ---help---
> > + Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> > + ioctl()s, the driver also provides a read/write interface to a BMC ram
> > + region where the host LPC read/write region can be buffered.
> > +
> > +config ASPEED_LPC_SNOOP
> > + tristate "Aspeed ast2500 HOST LPC snoop support"
> > + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> > + help
> > + Provides a driver to control the LPC snoop interface which
> > + allows the BMC to listen on and save the data written by
> > + the host to an arbitrary LPC I/O port.
> > +
> > +
> > diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
> > new file mode 100644
> > index 000000000000..cfaa9adc67b5
> > --- /dev/null
> > +++ b/drivers/soc/aspeed/Makefile
> > @@ -0,0 +1,2 @@
> > +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> > +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> > diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
> > similarity index 100%
> > rename from drivers/misc/aspeed-lpc-ctrl.c
> > rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
> > diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
> > similarity index 100%
> > rename from drivers/misc/aspeed-lpc-snoop.c
> > rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
> > --
> > 2.21.0.593.g511ec345e18-goog
> >
^ permalink raw reply
* [PATCH v2] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Andrew Peng @ 2019-04-23 11:55 UTC (permalink / raw)
To: linux-aspeed
Initial introduction of Lenovo Hr630 family equipped with
Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Lenovo.
Specifically, This adds the Hr630 platform device tree file
used by the Hr630 BMC machines.
This also adds an entry of Hr630 device tree file in Makefile
Signed-off-by: Andrew Peng <pengms1@lenovo.com>
Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 886 ++++++++++++++++++++++++++
2 files changed, 888 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aea..375e53b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
- aspeed-bmc-quanta-q71l.dtb
+ aspeed-bmc-quanta-q71l.dtb \
+ aspeed-bmc-lenovo-hr630.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
new file mode 100644
index 0000000..3322f83
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -0,0 +1,886 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Lenovo Hr630 platform
+ *
+ * Copyright (C) 2019-present Lenovo
+ */
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "HR630 BMC";
+ compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
+
+ aliases {
+ i2c_rbp = &i2c_rbp;
+ i2c_fbp1 = &i2c_fbp1;
+ i2c_fbp2 = &i2c_fbp2;
+ i2c_fbp3 = &i2c_fbp3;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region at 98000000 {
+ no-map;
+ reg = <0x98000000 0x00100000>; /* 1M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ /* temp1 inlet */
+ tmp75 at 4e {
+ compatible = "national,lm75";
+ reg = <0x4e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ /* temp2 outlet */
+ tmp75 at 4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 70 next. */
+
+ i2c_rbp: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_fbp1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_fbp2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_fbp3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+ i2c-switch at 76 {
+ compatible = "nxp,pca9546";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 76 next. */
+
+ i2c_riser2: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_riser1: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_ocp: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom at 57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+/*
+ * Enable port A as device (via the virtual hub) and port B as
+ * host by default on the eval board. This can be easily changed
+ * by replacing the override below with &ehci0 { ... } to enable
+ * host on both ports.
+ */
+&vhub {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan at 0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan at 1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan at 2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan at 3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan at 4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan at 5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan at 6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan at 7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan at 8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan at 9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan at 10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan at 11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan at 12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan at 13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+};
+
+&gpio {
+
+ pin_gpio_a0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MAC1_INT_N";
+ };
+
+ pin_gpio_a1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_C_PRESENT_N";
+ };
+
+ pin_gpio_a2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_PRST";
+ };
+
+ pin_gpio_a3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_PRST";
+ };
+
+ pin_gpio_b5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "IRQ_BMC_PCH_SMI_LPC_N";
+ };
+
+ pin_gpio_f0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "IRQ_BMC_PCH_NMI_R";
+ };
+
+ pin_gpio_f1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU1_DISABLE_COD_N";
+ };
+
+ pin_gpio_f2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "SMB_LAN_ALERT_N_MEZZ";
+ };
+
+ pin_gpio_f3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS0_RST_OUT_N";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT0_FAULT_LED";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT1_FAULT_LED";
+ };
+
+ pin_gpio_f6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_BMC_CPLD_NMI";
+ };
+
+ pin_gpio_f7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_ALERT_N";
+ };
+
+ pin_gpio_g0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_ERR2_LVT3_N";
+ };
+
+ pin_gpio_g1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
+ };
+
+ pin_gpio_g2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PCH_BMC_THERMTRIP_N";
+ };
+
+ pin_gpio_g3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_I2C_BUS7_INT_N";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_PWR_CTL_N";
+ };
+
+ pin_gpio_g5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NFC_FD_N";
+ };
+
+ pin_gpio_g6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_NMI_EVENT_N";
+ };
+
+ pin_gpio_g7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_PCIE_I2CMUX_N";
+ };
+
+ pin_gpio_h0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_EPOW_N_R";
+ };
+
+ pin_gpio_h1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_EPOW_N_R";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU1_FFS_N_R";
+ };
+
+ pin_gpio_h3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU2_FFS_N_R";
+ };
+
+ pin_gpio_h4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_THROTTLE_N_R";
+ };
+
+ pin_gpio_h5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_THROTTLE_N_R";
+ };
+
+ pin_gpio_h6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_SMB_RESET_N";
+ };
+
+ pin_gpio_h7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_SMB_RESET_N";
+ };
+
+ pin_gpio_i1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_PWR_BTN_N";
+ };
+
+ pin_gpio_i2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BIOS_RCVR_N";
+ };
+
+ pin_gpio_i3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_INTRUDED_COVER";
+ };
+
+ pin_gpio_j2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_BIOS_UPDATE_N";
+ };
+
+ pin_gpio_j3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_HDD_I2CMUX_N";
+ };
+
+ pin_gpio_q4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_A_PRESENT_N";
+ };
+
+ pin_gpio_q5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VGA_FRONT_PRES_N";
+ };
+
+ pin_gpio_q6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_RISER1_INT_N";
+ };
+
+ pin_gpio_q7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NCSI_CABLE_DET_N";
+ };
+
+ pin_gpio_r0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_RST_BTN_N";
+ };
+
+ pin_gpio_r2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG1_DETECT_N";
+ };
+
+ pin_gpio_r3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG2_DETECT_N";
+ };
+
+ pin_gpio_r4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG3_DETECT_N";
+ };
+
+ pin_gpio_r5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VIDEO_CABLE_DETECT_N";
+ };
+
+ pin_gpio_s0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_PS_RAPIDON_WAKE_R_N";
+ };
+
+ pin_gpio_s1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HOST_TPM_PP_BUF";
+ };
+
+ pin_gpio_s2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_VGA_SW";
+ };
+
+ pin_gpio_s3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SML0_ALERT_MUX_N";
+ };
+
+ pin_gpio_s4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "VBAT_EN_N";
+ };
+
+ pin_gpio_s5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_4";
+ };
+
+ pin_gpio_s6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PU_BMC_GPIOS6";
+ };
+
+ pin_gpio_s7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_BUS7_RESET_N";
+ };
+
+ pin_gpio_y0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S0";
+ };
+
+ pin_gpio_y1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S1";
+ };
+
+ pin_gpio_y2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "UID_ALERT_N";
+ };
+
+ pin_gpio_z0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_INT_N";
+ };
+
+ pin_gpio_z2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_RESET_N";
+ };
+
+ pin_gpio_z3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FM_BMC_PCH_SCI_LPC_N";
+ };
+
+ pin_gpio_z4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_17";
+ };
+
+ pin_gpio_z6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_20";
+ };
+
+ pin_gpio_z7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_POST_CMPLT_N";
+ };
+
+ pin_gpio_aa0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "HOST_BMC_USB_SEL";
+ };
+
+ pin_gpio_aa1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_ALERT_N";
+ };
+
+ pin_gpio_aa2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "USB_CABLE_DETECT_N";
+ };
+
+ pin_gpio_aa5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS1_RST_OUT_N";
+ };
+
+ pin_gpio_aa6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SMI_ACTIVE_N";
+ };
+
+ pin_gpio_aa7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_BIOS_POST_CMPLT_N";
+ };
+
+ pin_gpio_ab0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_TPM_MOD_PRES_N";
+ };
+
+ pin_gpio_ab1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FORCE_NMI_SW_FPGA_N";
+ };
+
+ pin_gpio_ab2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "1U_2U_PCBA_SEL_R";
+ };
+
+ pin_gpio_ab3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "INTRUDED_PRES_N";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH] soc: add aspeed folder and misc drivers
From: Arnd Bergmann @ 2019-04-23 8:08 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190422173838.182736-1-venture@google.com>
On Mon, Apr 22, 2019 at 7:38 PM Patrick Venture <venture@google.com> wrote:
>
> Create a SoC folder for the ASPEED parts and place the misc drivers
> currently present into this folder. These drivers are not generic part
> drivers, but rather only apply to the ASPEED SoCs.
>
> Signed-off-by: Patrick Venture <venture@google.com>
Looks ok, but please resend to arm at kernel.org or soc at kernel.org
so we can track the submission and make sure it gets applied if
you want this to go through the arm-soc tree.
If Greg wants to pick it up, that's fine too.
Either way,
Acked-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/misc/Kconfig | 16 ----------------
> drivers/misc/Makefile | 2 --
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
> drivers/soc/aspeed/Makefile | 2 ++
> .../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
> .../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
> 8 files changed, 23 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/aspeed/Kconfig
> create mode 100644 drivers/soc/aspeed/Makefile
> rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
> rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 42ab8ec92a04..b80cb6af0cb4 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
> bus. System Configuration interface is one of the possible means
> of generating transactions on this bus.
>
> -config ASPEED_LPC_CTRL
> - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> - tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> - ---help---
> - Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> - ioctl()s, the driver also provides a read/write interface to a BMC ram
> - region where the host LPC read/write region can be buffered.
> -
> -config ASPEED_LPC_SNOOP
> - tristate "Aspeed ast2500 HOST LPC snoop support"
> - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> - help
> - Provides a driver to control the LPC snoop interface which
> - allows the BMC to listen on and save the data written by
> - the host to an arbitrary LPC I/O port.
> -
> config PCI_ENDPOINT_TEST
> depends on PCI
> select CRC32
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index d5b7d3404dc7..b9affcdaa3d6 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
> obj-$(CONFIG_ECHO) += echo/
> obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
> obj-$(CONFIG_CXL_BASE) += cxl/
> -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
> obj-$(CONFIG_OCXL) += ocxl/
> obj-y += cardreader/
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index c07b4a85253f..b750a88547c7 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
>
> source "drivers/soc/actions/Kconfig"
> source "drivers/soc/amlogic/Kconfig"
> +source "drivers/soc/aspeed/Kconfig"
> source "drivers/soc/atmel/Kconfig"
> source "drivers/soc/bcm/Kconfig"
> source "drivers/soc/fsl/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 90b686e586c6..83a032db3e44 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -4,6 +4,7 @@
> #
>
> obj-$(CONFIG_ARCH_ACTIONS) += actions/
> +obj-y += aspeed/
> obj-$(CONFIG_ARCH_AT91) += atmel/
> obj-y += bcm/
> obj-$(CONFIG_ARCH_DOVE) += dove/
> diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
> new file mode 100644
> index 000000000000..457282cd1da5
> --- /dev/null
> +++ b/drivers/soc/aspeed/Kconfig
> @@ -0,0 +1,19 @@
> +menu "Aspeed SoC drivers"
> +
> +config ASPEED_LPC_CTRL
> + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> + tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> + ---help---
> + Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> + ioctl()s, the driver also provides a read/write interface to a BMC ram
> + region where the host LPC read/write region can be buffered.
> +
> +config ASPEED_LPC_SNOOP
> + tristate "Aspeed ast2500 HOST LPC snoop support"
> + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> + help
> + Provides a driver to control the LPC snoop interface which
> + allows the BMC to listen on and save the data written by
> + the host to an arbitrary LPC I/O port.
> +
> +
> diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
> new file mode 100644
> index 000000000000..cfaa9adc67b5
> --- /dev/null
> +++ b/drivers/soc/aspeed/Makefile
> @@ -0,0 +1,2 @@
> +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
> similarity index 100%
> rename from drivers/misc/aspeed-lpc-ctrl.c
> rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
> diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
> similarity index 100%
> rename from drivers/misc/aspeed-lpc-snoop.c
> rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
> --
> 2.21.0.593.g511ec345e18-goog
>
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-22 19:24 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190422175419.189895-1-venture@google.com>
On Mon, Apr 22, 2019 at 10:54 AM Patrick Venture <venture@google.com> wrote:
>
> Create a SoC folder for the ASPEED parts and place the misc drivers
> currently present into this folder. These drivers are not generic part
> drivers, but rather only apply to the ASPEED SoCs.
>
> Signed-off-by: Patrick Venture <venture@google.com>
> ---
> v2:
> Added configuration option for ASPEED to soc/Makefile
> ---
> drivers/misc/Kconfig | 16 ----------------
> drivers/misc/Makefile | 2 --
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
> drivers/soc/aspeed/Makefile | 2 ++
> .../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
> .../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
> 8 files changed, 23 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/aspeed/Kconfig
> create mode 100644 drivers/soc/aspeed/Makefile
> rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
> rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 42ab8ec92a04..b80cb6af0cb4 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
> bus. System Configuration interface is one of the possible means
> of generating transactions on this bus.
>
> -config ASPEED_LPC_CTRL
> - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> - tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> - ---help---
> - Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> - ioctl()s, the driver also provides a read/write interface to a BMC ram
> - region where the host LPC read/write region can be buffered.
> -
> -config ASPEED_LPC_SNOOP
> - tristate "Aspeed ast2500 HOST LPC snoop support"
> - depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> - help
> - Provides a driver to control the LPC snoop interface which
> - allows the BMC to listen on and save the data written by
> - the host to an arbitrary LPC I/O port.
> -
> config PCI_ENDPOINT_TEST
> depends on PCI
> select CRC32
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index d5b7d3404dc7..b9affcdaa3d6 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
> obj-$(CONFIG_ECHO) += echo/
> obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
> obj-$(CONFIG_CXL_BASE) += cxl/
> -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
> obj-$(CONFIG_OCXL) += ocxl/
> obj-y += cardreader/
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index c07b4a85253f..b750a88547c7 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
>
> source "drivers/soc/actions/Kconfig"
> source "drivers/soc/amlogic/Kconfig"
> +source "drivers/soc/aspeed/Kconfig"
> source "drivers/soc/atmel/Kconfig"
> source "drivers/soc/bcm/Kconfig"
> source "drivers/soc/fsl/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 90b686e586c6..814128fe479f 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -4,6 +4,7 @@
> #
>
> obj-$(CONFIG_ARCH_ACTIONS) += actions/
> +obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> obj-$(CONFIG_ARCH_AT91) += atmel/
> obj-y += bcm/
> obj-$(CONFIG_ARCH_DOVE) += dove/
> diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
> new file mode 100644
> index 000000000000..457282cd1da5
> --- /dev/null
> +++ b/drivers/soc/aspeed/Kconfig
> @@ -0,0 +1,19 @@
> +menu "Aspeed SoC drivers"
> +
> +config ASPEED_LPC_CTRL
> + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> + tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
> + ---help---
> + Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
> + ioctl()s, the driver also provides a read/write interface to a BMC ram
> + region where the host LPC read/write region can be buffered.
> +
> +config ASPEED_LPC_SNOOP
> + tristate "Aspeed ast2500 HOST LPC snoop support"
> + depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
> + help
> + Provides a driver to control the LPC snoop interface which
> + allows the BMC to listen on and save the data written by
> + the host to an arbitrary LPC I/O port.
> +
> +
> diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
> new file mode 100644
> index 000000000000..cfaa9adc67b5
> --- /dev/null
> +++ b/drivers/soc/aspeed/Makefile
> @@ -0,0 +1,2 @@
> +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
> similarity index 100%
> rename from drivers/misc/aspeed-lpc-ctrl.c
> rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
> diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
> similarity index 100%
> rename from drivers/misc/aspeed-lpc-snoop.c
> rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
> --
> 2.21.0.593.g511ec345e18-goog
>
Fixed CC on this reply (Gmail button didn't behave as expected) and
replied to the v2 patchset instead of accidentally the first.
Given this patchset, I have several patches that move the drivers into
the folder, and thought about writing it up as a series. I wanted to
see how this patchset would do before I staged the rest -- my question
is, should this patchset create the folder with the empty Kconfig and
Makefile, and then have follow-on patches that provide content to
split out the process into multiple logical steps?
^ permalink raw reply
* [PATCH dev-5.0 v2] ARM: dts: aspeed: Add Swift BMC machine
From: Matt Spinler @ 2019-04-22 18:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1555605815-31386-1-git-send-email-anoo@linux.ibm.com>
On 4/18/2019 11:43 AM, Adriana Kobylak wrote:
> From: Adriana Kobylak <anoo@us.ibm.com>
>
> The Swift BMC is an ASPEED ast2500 based BMC that is part of
> a Power9 server. This adds the device tree description for
> most upstream components.
>
> Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 782 +++++++++++++++++++++++++++++
> 2 files changed, 783 insertions(+)
> create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index bd40148..b82a24d 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1244,6 +1244,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> aspeed-bmc-opp-lanyang.dtb \
> aspeed-bmc-opp-palmetto.dtb \
> aspeed-bmc-opp-romulus.dtb \
> + aspeed-bmc-opp-swift.dtb \
> aspeed-bmc-opp-witherspoon.dtb \
> aspeed-bmc-opp-zaius.dtb \
> aspeed-bmc-portwell-neptune.dtb \
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
> new file mode 100644
> index 0000000..1921a50
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
> @@ -0,0 +1,782 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/dts-v1/;
> +#include "aspeed-g5.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +#include <dt-bindings/leds/leds-pca955x.h>
> +
> +/ {
> + model = "Swift BMC";
> + compatible = "ibm,swift-bmc", "aspeed,ast2500";
> +
> + chosen {
> + stdout-path = &uart5;
> + bootargs = "console=ttyS4,115200 earlyprintk";
> + };
> +
> + memory at 80000000 {
> + reg = <0x80000000 0x20000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flash_memory: region at 98000000 {
> + no-map;
> + reg = <0x98000000 0x04000000>; /* 64M */
> + };
> +
> + gfx_memory: framebuffer {
> + size = <0x01000000>;
> + alignment = <0x01000000>;
> + compatible = "shared-dma-pool";
> + reusable;
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + air-water {
> + label = "air-water";
> + gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
> + linux,code = <ASPEED_GPIO(B, 5)>;
> + };
> +
> + checkstop {
> + label = "checkstop";
> + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
> + linux,code = <ASPEED_GPIO(J, 2)>;
> + };
> +
> + ps0-presence {
> + label = "ps0-presence";
> + gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>;
> + linux,code = <ASPEED_GPIO(R, 7)>;
> + };
> +
> + ps1-presence {
> + label = "ps1-presence";
> + gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;
> + linux,code = <ASPEED_GPIO(N, 0)>;
> + };
Can you also add the entries for the op-panel and CAPI riser presence
detects?
> + };
> +
> + iio-hwmon-battery {
> + compatible = "iio-hwmon";
> + io-channels = <&adc 12>;
> + };
> +
> + gpio-keys-polled {
> + compatible = "gpio-keys-polled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + poll-interval = <1000>;
> +
The SCM and VRM presence detects from the pca9552 on bus 8 below
I think we also want listed here?
> + fan0-presence {
> + label = "fan0-presence";
> + gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
> + linux,code = <5>;
> + };
> +
> + fan1-presence {
> + label = "fan1-presence";
> + gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
> + linux,code = <6>;
> + };
> +
> + fan2-presence {
> + label = "fan2-presence";
> + gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
> + linux,code = <7>;
> + };
> +
> + fan3-presence {
> + label = "fan3-presence";
> + gpios = <&pca0 8 GPIO_ACTIVE_LOW>;
> + linux,code = <8>;
> + };
> +
> + fanboost-presence {
> + label = "fanboost-presence";
> + gpios = <&pca0 9 GPIO_ACTIVE_LOW>;
> + linux,code = <9>;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + fan0 {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
> + };
> +
> + fan1 {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
> + };
> +
> + fan2 {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
> + };
> +
> + fan3 {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
> + };
> +
> + fanboost {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
> + };
> +
> + front-fault {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca1 2 GPIO_ACTIVE_LOW>;
> + };
> +
> + front-power {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca1 3 GPIO_ACTIVE_LOW>;
> + };
> +
> + front-id {
> + retain-state-shutdown;
> + default-state = "keep";
> + gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
> + };
> +
> + rear-fault {
> + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
> + };
> +
> + rear-id {
> + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
> + };
> +
> + rear-power {
> + gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + fsi: gpio-fsi {
> + compatible = "fsi-master-gpio", "fsi-master";
> + #address-cells = <2>;
> + #size-cells = <0>;
> + no-gpio-delays;
> +
> + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
> + data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
> + mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
> + enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
> + trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
> + };
> +
> + iio-hwmon-dps310 {
> + compatible = "iio-hwmon";
> + io-channels = <&dps 0>;
> + };
> +
> +};
> +
> +&fmc {
> + status = "okay";
> +
> + flash at 0 {
> + status = "okay";
> + label = "bmc";
> + m25p,fast-read;
> + spi-max-frequency = <100000000>;
> + partitions {
> + #address-cells = < 1 >;
> + #size-cells = < 1 >;
> + compatible = "fixed-partitions";
> + u-boot at 0 {
> + reg = < 0 0x60000 >;
> + label = "u-boot";
> + };
> + u-boot-env at 60000 {
> + reg = < 0x60000 0x20000 >;
> + label = "u-boot-env";
> + };
> + obmc-ubi at 80000 {
> + reg = < 0x80000 0x7F80000>;
> + label = "obmc-ubi";
> + };
> + };
> + };
> +
> + flash at 1 {
> + status = "okay";
> + label = "alt-bmc";
> + m25p,fast-read;
> + spi-max-frequency = <100000000>;
> + partitions {
> + #address-cells = < 1 >;
> + #size-cells = < 1 >;
> + compatible = "fixed-partitions";
> + u-boot at 0 {
> + reg = < 0 0x60000 >;
> + label = "alt-u-boot";
> + };
> + u-boot-env at 60000 {
> + reg = < 0x60000 0x20000 >;
> + label = "alt-u-boot-env";
> + };
> + obmc-ubi at 80000 {
> + reg = < 0x80000 0x7F80000>;
> + label = "alt-obmc-ubi";
> + };
> + };
> + };
> +};
> +
> +&spi1 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi1_default>;
> +
> + flash at 0 {
> + status = "okay";
> + label = "pnor";
> + m25p,fast-read;
> + spi-max-frequency = <100000000>;
> + };
> +};
> +
> +&uart1 {
> + /* Rear RS-232 connector */
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_txd1_default
> + &pinctrl_rxd1_default
> + &pinctrl_nrts1_default
> + &pinctrl_ndtr1_default
> + &pinctrl_ndsr1_default
> + &pinctrl_ncts1_default
> + &pinctrl_ndcd1_default
> + &pinctrl_nri1_default>;
> +};
> +
> +&uart2 {
> + /* APSS */
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&lpc_ctrl {
> + status = "okay";
> + memory-region = <&flash_memory>;
> + flash = <&spi1>;
> +};
> +
> +&mbox {
> + status = "okay";
> +};
> +
> +&mac0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rmii1_default>;
> + use-ncsi;
> +};
> +
> +&i2c2 {
> + status = "okay";
> +
> + /* MUX ->
> + * Samtec 1
> + * Samtec 2
> + */
> +};
> +
> +&i2c3 {
> + status = "okay";
> +
> + max31785 at 52 {
> + compatible = "maxim,max31785a";
> + reg = <0x52>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + fan at 0 {
> + compatible = "pmbus-fan";
> + reg = <0>;
> + tach-pulses = <2>;
> + maxim,fan-rotor-input = "tach";
> + maxim,fan-pwm-freq = <25000>;
> + maxim,fan-no-watchdog;
> + maxim,fan-no-fault-ramp;
> + maxim,fan-ramp = <2>;
> + maxim,fan-fault-pin-mon;
> + };
> +
> + fan at 1 {
> + compatible = "pmbus-fan";
> + reg = <1>;
> + tach-pulses = <2>;
> + maxim,fan-rotor-input = "tach";
> + maxim,fan-pwm-freq = <25000>;
> + maxim,fan-no-watchdog;
> + maxim,fan-no-fault-ramp;
> + maxim,fan-ramp = <2>;
> + maxim,fan-fault-pin-mon;
> + };
> +
> + fan at 2 {
> + compatible = "pmbus-fan";
> + reg = <2>;
> + tach-pulses = <2>;
> + maxim,fan-rotor-input = "tach";
> + maxim,fan-pwm-freq = <25000>;
> + maxim,fan-no-watchdog;
> + maxim,fan-no-fault-ramp;
> + maxim,fan-ramp = <2>;
> + maxim,fan-fault-pin-mon;
> + };
> +
> + fan at 3 {
> + compatible = "pmbus-fan";
> + reg = <3>;
> + tach-pulses = <2>;
> + maxim,fan-rotor-input = "tach";
> + maxim,fan-pwm-freq = <25000>;
> + maxim,fan-no-watchdog;
> + maxim,fan-no-fault-ramp;
> + maxim,fan-ramp = <2>;
> + maxim,fan-fault-pin-mon;
> + };
> +
> + fan at 4 {
> + compatible = "pmbus-fan";
> + reg = <4>;
> + tach-pulses = <2>;
> + maxim,fan-rotor-input = "tach";
> + maxim,fan-pwm-freq = <25000>;
> + maxim,fan-no-watchdog;
> + maxim,fan-no-fault-ramp;
> + maxim,fan-ramp = <2>;
> + maxim,fan-fault-pin-mon;
> + };
> + };
> +
> + pca0: pca9552 at 60 {
> + compatible = "nxp,pca9552";
> + reg = <0x60>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + gpio at 0 {
> + reg = <0>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 1 {
> + reg = <1>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 2 {
> + reg = <2>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 3 {
> + reg = <3>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 4 {
> + reg = <4>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 5 {
> + reg = <5>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 6 {
> + reg = <6>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 7 {
> + reg = <7>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 8 {
> + reg = <8>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 9 {
> + reg = <9>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 10 {
> + reg = <10>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 11 {
> + reg = <11>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 12 {
> + reg = <12>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 13 {
> + reg = <13>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 14 {
> + reg = <14>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 15 {
> + reg = <15>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> + };
> +
> + power-supply at 68 {
> + compatible = "ibm,cffps1";
> + reg = <0x68>;
> + };
> +
> + eeprom at 50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + };
> +
> + power-supply at 69 {
> + compatible = "ibm,cffps1";
> + reg = <0x69>;
> + };
> +
> + eeprom at 51 {
> + compatible = "atmel,24c64";
> + reg = <0x51>;
> + };
> +};
> +
> +&i2c7 {
> + status = "okay";
> +
> + dps: dps310 at 76 {
> + compatible = "infineon,dps310";
> + reg = <0x76>;
> + #io-channel-cells = <0>;
> + };
> +
> + tmp275 at 48 {
> + compatible = "ti,tmp275";
> + reg = <0x48>;
> + };
> +
> + si7021a20 at 20 {
> + compatible = "si,si7021a20";
> + reg = <0x20>;
> + };
> +
> + eeprom at 50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + };
> +
> + pca1: pca9551 at 60 {
> + compatible = "nxp,pca9551";
> + reg = <0x60>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + gpio at 0 {
> + reg = <0>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 1 {
> + reg = <1>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 2 {
> + reg = <2>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 3 {
> + reg = <3>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 4 {
> + reg = <4>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 5 {
> + reg = <5>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 6 {
> + reg = <6>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 7 {
> + reg = <7>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> + };
> +};
> +
> +&i2c8 {
> + status = "okay";
> +
> + pca9552: pca9552 at 60 {
> + compatible = "nxp,pca9552";
> + reg = <0x60>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
> + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
> + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
> + "P9_SCM0_PRES", "P9_SCM1_PRES",
> + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
> + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
> + "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N",
> + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
> +
> + gpio at 0 {
> + reg = <0>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 1 {
> + reg = <1>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 2 {
> + reg = <2>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 3 {
> + reg = <3>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 4 {
> + reg = <4>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 5 {
> + reg = <5>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 6 {
> + reg = <6>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 7 {
> + reg = <7>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 8 {
> + reg = <8>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 9 {
> + reg = <9>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 10 {
> + reg = <10>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 11 {
> + reg = <11>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 12 {
> + reg = <12>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 13 {
> + reg = <13>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 14 {
> + reg = <14>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> +
> + gpio at 15 {
> + reg = <15>;
> + type = <PCA955X_TYPE_GPIO>;
> + };
> + };
> +
> + rtc at 32 {
> + compatible = "epson,rx8900";
> + reg = <0x32>;
> + };
> +
> + eeprom at 51 {
> + compatible = "atmel,24c64";
> + reg = <0x51>;
> + };
> +
> + ucd90160 at 64 {
> + compatible = "ti,ucd90160";
> + reg = <0x64>;
> + };
> +};
> +
> +&i2c9 {
> + status = "okay";
> +
> + tmp423a at 4c {
> + compatible = "ti,tmp423";
> + reg = <0x4c>;
> + };
> +
> + ir35221 at 71 {
> + compatible = "infineon,ir35221";
> + reg = <0x71>;
> + };
> +
> + ir35221 at 72 {
> + compatible = "infineon,ir35221";
> + reg = <0x72>;
> + };
Can you add the EEPROM for this CPU0 VRM here?
> +};
> +
> +&i2c10 {
> + status = "okay";
> +
> + tmp423a at 4c {
> + compatible = "ti,tmp423";
> + reg = <0x4c>;
> + };
> +
> + ir35221 at 71 {
> + compatible = "infineon,ir35221";
> + reg = <0x71>;
> + };
> +
> + ir35221 at 72 {
> + compatible = "infineon,ir35221";
> + reg = <0x72>;
> + };
Can you add the EEPROM for this CPU1 VRM here?
> +};
> +
> +&i2c11 {
> + /* MUX
> + * -> PCIe Slot 0
> + * -> PCIe Slot 1
> + * -> PCIe Slot 2
> + * -> PCIe Slot 3
> + */
> + status = "okay";
> +};
> +
> +&i2c12 {
> + status = "okay";
> +
> + tmp275 at 48 {
> + compatible = "ti,tmp275";
> + reg = <0x48>;
> + };
> +
> + tmp275 at 4a {
> + compatible = "ti,tmp275";
> + reg = <0x4a>;
> + };
> +};
> +
> +&i2c13 {
> + status = "okay";
> +};
> +
> +&vuart {
> + status = "okay";
> +};
> +
> +&gfx {
> + status = "okay";
> + memory-region = <&gfx_memory>;
> +};
> +
> +&pinctrl {
> + aspeed,external-nodes = <&gfx &lhc>;
> +};
> +
> +&wdt1 {
> + aspeed,reset-type = "none";
> + aspeed,external-signal;
> + aspeed,ext-push-pull;
> + aspeed,ext-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdtrst1_default>;
> +};
> +
> +&wdt2 {
> + aspeed,alt-boot;
> +};
> +
> +&ibt {
> + status = "okay";
> +};
> +
> +&adc {
> + status = "okay";
> +};
> +
> +#include "ibm-power9-dual.dtsi"
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-22 17:54 UTC (permalink / raw)
To: linux-aspeed
Create a SoC folder for the ASPEED parts and place the misc drivers
currently present into this folder. These drivers are not generic part
drivers, but rather only apply to the ASPEED SoCs.
Signed-off-by: Patrick Venture <venture@google.com>
---
v2:
Added configuration option for ASPEED to soc/Makefile
---
drivers/misc/Kconfig | 16 ----------------
drivers/misc/Makefile | 2 --
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
drivers/soc/aspeed/Makefile | 2 ++
.../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
.../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
8 files changed, 23 insertions(+), 18 deletions(-)
create mode 100644 drivers/soc/aspeed/Kconfig
create mode 100644 drivers/soc/aspeed/Makefile
rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 42ab8ec92a04..b80cb6af0cb4 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
bus. System Configuration interface is one of the possible means
of generating transactions on this bus.
-config ASPEED_LPC_CTRL
- depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
- tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
- ---help---
- Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
- ioctl()s, the driver also provides a read/write interface to a BMC ram
- region where the host LPC read/write region can be buffered.
-
-config ASPEED_LPC_SNOOP
- tristate "Aspeed ast2500 HOST LPC snoop support"
- depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
- help
- Provides a driver to control the LPC snoop interface which
- allows the BMC to listen on and save the data written by
- the host to an arbitrary LPC I/O port.
-
config PCI_ENDPOINT_TEST
depends on PCI
select CRC32
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d5b7d3404dc7..b9affcdaa3d6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
-obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
-obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
obj-$(CONFIG_OCXL) += ocxl/
obj-y += cardreader/
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index c07b4a85253f..b750a88547c7 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
source "drivers/soc/amlogic/Kconfig"
+source "drivers/soc/aspeed/Kconfig"
source "drivers/soc/atmel/Kconfig"
source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 90b686e586c6..814128fe479f 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
obj-y += bcm/
obj-$(CONFIG_ARCH_DOVE) += dove/
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
new file mode 100644
index 000000000000..457282cd1da5
--- /dev/null
+++ b/drivers/soc/aspeed/Kconfig
@@ -0,0 +1,19 @@
+menu "Aspeed SoC drivers"
+
+config ASPEED_LPC_CTRL
+ depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
+ tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
+ ---help---
+ Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
+ ioctl()s, the driver also provides a read/write interface to a BMC ram
+ region where the host LPC read/write region can be buffered.
+
+config ASPEED_LPC_SNOOP
+ tristate "Aspeed ast2500 HOST LPC snoop support"
+ depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
+ help
+ Provides a driver to control the LPC snoop interface which
+ allows the BMC to listen on and save the data written by
+ the host to an arbitrary LPC I/O port.
+
+
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
new file mode 100644
index 000000000000..cfaa9adc67b5
--- /dev/null
+++ b/drivers/soc/aspeed/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
similarity index 100%
rename from drivers/misc/aspeed-lpc-ctrl.c
rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
similarity index 100%
rename from drivers/misc/aspeed-lpc-snoop.c
rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [PATCH] soc: add aspeed folder and misc drivers
From: Patrick Venture @ 2019-04-22 17:38 UTC (permalink / raw)
To: linux-aspeed
Create a SoC folder for the ASPEED parts and place the misc drivers
currently present into this folder. These drivers are not generic part
drivers, but rather only apply to the ASPEED SoCs.
Signed-off-by: Patrick Venture <venture@google.com>
---
drivers/misc/Kconfig | 16 ----------------
drivers/misc/Makefile | 2 --
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/aspeed/Kconfig | 19 +++++++++++++++++++
drivers/soc/aspeed/Makefile | 2 ++
.../{misc => soc/aspeed}/aspeed-lpc-ctrl.c | 0
.../{misc => soc/aspeed}/aspeed-lpc-snoop.c | 0
8 files changed, 23 insertions(+), 18 deletions(-)
create mode 100644 drivers/soc/aspeed/Kconfig
create mode 100644 drivers/soc/aspeed/Makefile
rename drivers/{misc => soc/aspeed}/aspeed-lpc-ctrl.c (100%)
rename drivers/{misc => soc/aspeed}/aspeed-lpc-snoop.c (100%)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 42ab8ec92a04..b80cb6af0cb4 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -496,22 +496,6 @@ config VEXPRESS_SYSCFG
bus. System Configuration interface is one of the possible means
of generating transactions on this bus.
-config ASPEED_LPC_CTRL
- depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
- tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
- ---help---
- Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
- ioctl()s, the driver also provides a read/write interface to a BMC ram
- region where the host LPC read/write region can be buffered.
-
-config ASPEED_LPC_SNOOP
- tristate "Aspeed ast2500 HOST LPC snoop support"
- depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
- help
- Provides a driver to control the LPC snoop interface which
- allows the BMC to listen on and save the data written by
- the host to an arbitrary LPC I/O port.
-
config PCI_ENDPOINT_TEST
depends on PCI
select CRC32
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d5b7d3404dc7..b9affcdaa3d6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -54,8 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
-obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
-obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
obj-$(CONFIG_OCXL) += ocxl/
obj-y += cardreader/
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index c07b4a85253f..b750a88547c7 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
source "drivers/soc/amlogic/Kconfig"
+source "drivers/soc/aspeed/Kconfig"
source "drivers/soc/atmel/Kconfig"
source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 90b686e586c6..83a032db3e44 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
obj-y += bcm/
obj-$(CONFIG_ARCH_DOVE) += dove/
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
new file mode 100644
index 000000000000..457282cd1da5
--- /dev/null
+++ b/drivers/soc/aspeed/Kconfig
@@ -0,0 +1,19 @@
+menu "Aspeed SoC drivers"
+
+config ASPEED_LPC_CTRL
+ depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
+ tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
+ ---help---
+ Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
+ ioctl()s, the driver also provides a read/write interface to a BMC ram
+ region where the host LPC read/write region can be buffered.
+
+config ASPEED_LPC_SNOOP
+ tristate "Aspeed ast2500 HOST LPC snoop support"
+ depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
+ help
+ Provides a driver to control the LPC snoop interface which
+ allows the BMC to listen on and save the data written by
+ the host to an arbitrary LPC I/O port.
+
+
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
new file mode 100644
index 000000000000..cfaa9adc67b5
--- /dev/null
+++ b/drivers/soc/aspeed/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
similarity index 100%
rename from drivers/misc/aspeed-lpc-ctrl.c
rename to drivers/soc/aspeed/aspeed-lpc-ctrl.c
diff --git a/drivers/misc/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
similarity index 100%
rename from drivers/misc/aspeed-lpc-snoop.c
rename to drivers/soc/aspeed/aspeed-lpc-snoop.c
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [PATCH] [PATCH v1] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Andrew Peng @ 2019-04-19 11:32 UTC (permalink / raw)
To: linux-aspeed
Initial introduction of Lenovo Hr630 family equipped with
Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Lenovo.
Specifically, This adds the Hr630 platform device tree file
used by the Hr630 BMC machines.
This also adds an entry of Hr630 device tree file in Makefile
Signed-off-by: Andrew Peng <pengms1@lenovo.com>
Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 884 ++++++++++++++++++++++++++
2 files changed, 886 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aea..375e53b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
- aspeed-bmc-quanta-q71l.dtb
+ aspeed-bmc-quanta-q71l.dtb \
+ aspeed-bmc-lenovo-hr630.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
new file mode 100644
index 0000000..ca80509
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -0,0 +1,884 @@
+// SPDX-License-Identifier: GPL-2.0+
+//"Copyright ? 2019-present Lenovo
+//Licensed under GPL v2, see COPYING file for details."
+
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "HR630 BMC";
+ compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region at 98000000 {
+ no-map;
+ reg = <0x98000000 0x00100000>; /* 1M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ /* temp1 inlet */
+ tmp75 at 4e {
+ compatible = "national,lm75";
+ reg = <0x4e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ /* temp2 outlet */
+ tmp75 at 4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+ /*
+ *eeprom at 50 {
+ * compatible = "atmel,24c08";
+ * reg = <0x50>;
+ * pagesize = <16>;
+ *};
+ */
+};
+
+&i2c6 {
+ status = "okay";
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 70 next. */
+
+ i2c_rbp: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_fbp1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_fbp2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_fbp3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+ i2c-switch at 76 {
+ compatible = "nxp,pca9546";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 76 next. */
+
+ i2c_riser2: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_riser1: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_ocp: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom at 57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+/*
+ * Enable port A as device (via the virtual hub) and port B as
+ * host by default on the eval board. This can be easily changed
+ * by replacing the override below with &ehci0 { ... } to enable
+ * host on both ports.
+ */
+&vhub {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan at 0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan at 1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan at 2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan at 3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan at 4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan at 5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan at 6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan at 7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan at 8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan at 9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan at 10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan at 11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan at 12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan at 13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+};
+
+&gpio {
+
+ pin_gpio_a0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MAC1_INT_N";
+ };
+
+ pin_gpio_a1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_C_PRESENT_N";
+ };
+
+ pin_gpio_a2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_PRST";
+ };
+
+ pin_gpio_a3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_PRST";
+ };
+
+ pin_gpio_b5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "IRQ_BMC_PCH_SMI_LPC_N";
+ };
+
+ pin_gpio_f0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "IRQ_BMC_PCH_NMI_R";
+ };
+
+ pin_gpio_f1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU1_DISABLE_COD_N";
+ };
+
+ pin_gpio_f2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "SMB_LAN_ALERT_N_MEZZ";
+ };
+
+ pin_gpio_f3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS0_RST_OUT_N";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT0_FAULT_LED";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT1_FAULT_LED";
+ };
+
+ pin_gpio_f6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_BMC_CPLD_NMI";
+ };
+
+ pin_gpio_f7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_ALERT_N";
+ };
+
+ pin_gpio_g0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_ERR2_LVT3_N";
+ };
+
+ pin_gpio_g1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
+ };
+
+ pin_gpio_g2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PCH_BMC_THERMTRIP_N";
+ };
+
+ pin_gpio_g3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_I2C_BUS7_INT_N";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_PWR_CTL_N";
+ };
+
+ pin_gpio_g5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NFC_FD_N";
+ };
+
+ pin_gpio_g6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_NMI_EVENT_N";
+ };
+
+ pin_gpio_g7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_PCIE_I2CMUX_N";
+ };
+
+ pin_gpio_h0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_EPOW_N_R";
+ };
+
+ pin_gpio_h1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_EPOW_N_R";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU1_FFS_N_R";
+ };
+
+ pin_gpio_h3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU2_FFS_N_R";
+ };
+
+ pin_gpio_h4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_THROTTLE_N_R";
+ };
+
+ pin_gpio_h5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_THROTTLE_N_R";
+ };
+
+ pin_gpio_h6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_SMB_RESET_N";
+ };
+
+ pin_gpio_h7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_SMB_RESET_N";
+ };
+
+ pin_gpio_i1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_PWR_BTN_N";
+ };
+
+ pin_gpio_i2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BIOS_RCVR_N";
+ };
+
+ pin_gpio_i3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_INTRUDED_COVER";
+ };
+
+ pin_gpio_j2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_BIOS_UPDATE_N";
+ };
+
+ pin_gpio_j3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_HDD_I2CMUX_N";
+ };
+
+ pin_gpio_q4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_A_PRESENT_N";
+ };
+
+ pin_gpio_q5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VGA_FRONT_PRES_N";
+ };
+
+ pin_gpio_q6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_RISER1_INT_N";
+ };
+
+ pin_gpio_q7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NCSI_CABLE_DET_N";
+ };
+
+ pin_gpio_r0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_RST_BTN_N";
+ };
+
+ pin_gpio_r2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG1_DETECT_N";
+ };
+
+ pin_gpio_r3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG2_DETECT_N";
+ };
+
+ pin_gpio_r4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG3_DETECT_N";
+ };
+
+ pin_gpio_r5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VIDEO_CABLE_DETECT_N";
+ };
+
+ pin_gpio_s0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_PS_RAPIDON_WAKE_R_N";
+ };
+
+ pin_gpio_s1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HOST_TPM_PP_BUF";
+ };
+
+ pin_gpio_s2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_VGA_SW";
+ };
+
+ pin_gpio_s3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SML0_ALERT_MUX_N";
+ };
+
+ pin_gpio_s4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "VBAT_EN_N";
+ };
+
+ pin_gpio_s5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_4";
+ };
+
+ pin_gpio_s6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PU_BMC_GPIOS6";
+ };
+
+ pin_gpio_s7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_BUS7_RESET_N";
+ };
+
+ pin_gpio_y0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S0";
+ };
+
+ pin_gpio_y1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S1";
+ };
+
+ pin_gpio_y2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "UID_ALERT_N";
+ };
+
+ pin_gpio_z0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_INT_N";
+ };
+
+ pin_gpio_z2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_RESET_N";
+ };
+
+ pin_gpio_z3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FM_BMC_PCH_SCI_LPC_N";
+ };
+
+ pin_gpio_z4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_17";
+ };
+
+ pin_gpio_z6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_20";
+ };
+
+ pin_gpio_z7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_POST_CMPLT_N";
+ };
+
+ pin_gpio_aa0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "HOST_BMC_USB_SEL";
+ };
+
+ pin_gpio_aa1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_ALERT_N";
+ };
+
+ pin_gpio_aa2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "USB_CABLE_DETECT_N";
+ };
+
+ pin_gpio_aa5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS1_RST_OUT_N";
+ };
+
+ pin_gpio_aa6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SMI_ACTIVE_N";
+ };
+
+ pin_gpio_aa7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_BIOS_POST_CMPLT_N";
+ };
+
+ pin_gpio_ab0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_TPM_MOD_PRES_N";
+ };
+
+ pin_gpio_ab1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FORCE_NMI_SW_FPGA_N";
+ };
+
+ pin_gpio_ab2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "1U_2U_PCBA_SEL_R";
+ };
+
+ pin_gpio_ab3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "INTRUDED_PRES_N";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 4/5] clk: Aspeed: Setup video engine clocking
From: Stephen Boyd @ 2019-04-18 21:56 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8Xc5vA6M06QgXMAm9angZMdobxNOqFMNwzq30_GQNaBT9A@mail.gmail.com>
Quoting Joel Stanley (2019-04-10 19:50:16)
> On Tue, 2 Apr 2019 at 18:25, Eddie James <eajames@linux.ibm.com> wrote:
> >
> > Add eclk mux and clock divider table. Also change the video engine reset
> > to the correct clock; it was previously on the video capture but needs
> > to be on the video engine clock.
> >
> > Signed-off-by: Eddie James <eajames@linux.ibm.com>
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> Stephen, Eddie and I have worked together on this change and I am
> happy with it now.
>
Thanks! Applied to clk-next.
^ permalink raw reply
* [PATCH 2/6] hwmon: (aspeed-pwm-tacho) Use devm_thermal_of_cooling_device_register
From: Patrick Venture @ 2019-04-18 20:35 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1555617500-10862-3-git-send-email-linux@roeck-us.net>
On Thu, Apr 18, 2019 at 12:58 PM Guenter Roeck <linux@roeck-us.net> wrote:
>
> Use devm_thermal_of_cooling_device_register() to register the cooling
> device. As a side effect, this fixes a driver bug:
> thermal_cooling_device_unregister() was not called on removal.
>
> Fixes: f198907d2ff6d ("hwmon: (aspeed-pwm-tacho) cooling device support.")
> Cc: Mykola Kostenok <c_mykolak@mellanox.com>
> Cc: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Patrick Venture <venture@google.com>
> ---
> drivers/hwmon/aspeed-pwm-tacho.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/hwmon/aspeed-pwm-tacho.c b/drivers/hwmon/aspeed-pwm-tacho.c
> index c4dd6301e7c8..0daf0b32aa4a 100644
> --- a/drivers/hwmon/aspeed-pwm-tacho.c
> +++ b/drivers/hwmon/aspeed-pwm-tacho.c
> @@ -830,10 +830,8 @@ static int aspeed_create_pwm_cooling(struct device *dev,
> }
> snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
>
> - cdev->tcdev = thermal_of_cooling_device_register(child,
> - cdev->name,
> - cdev,
> - &aspeed_pwm_cool_ops);
> + cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
> + cdev->name, cdev, &aspeed_pwm_cool_ops);
> if (IS_ERR(cdev->tcdev))
> return PTR_ERR(cdev->tcdev);
>
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 6/6] hwmon: (pwm-fan) Use devm_thermal_of_cooling_device_register
From: Guenter Roeck @ 2019-04-18 19:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1555617500-10862-1-git-send-email-linux@roeck-us.net>
Use devm_thermal_of_cooling_device_register() to register the cooling
device. Also use devm_add_action_or_reset() to stop the fan on device
removal, and to disable the pwm. Introduce a local 'dev' variable in
the probe function to make the code easier to read.
As a side effect, this fixes a bug seen if pwm_fan_of_get_cooling_data()
returned an error. In that situation, the pwm was not disabled, and
the fan was not stopped. Using devm functions also ensures that the
pwm is disabled and that the fan is stopped only after the hwmon device
has been unregistered.
Cc: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/pwm-fan.c | 73 ++++++++++++++++++++-----------------------------
1 file changed, 29 insertions(+), 44 deletions(-)
diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c
index 167221c7628a..0243ba70107e 100644
--- a/drivers/hwmon/pwm-fan.c
+++ b/drivers/hwmon/pwm-fan.c
@@ -207,33 +207,44 @@ static int pwm_fan_of_get_cooling_data(struct device *dev,
return 0;
}
+static void pwm_fan_regulator_disable(void *data)
+{
+ regulator_disable(data);
+}
+
+static void pwm_fan_pwm_disable(void *data)
+{
+ pwm_disable(data);
+}
+
static int pwm_fan_probe(struct platform_device *pdev)
{
struct thermal_cooling_device *cdev;
+ struct device *dev = &pdev->dev;
struct pwm_fan_ctx *ctx;
struct device *hwmon;
int ret;
struct pwm_state state = { };
- ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
mutex_init(&ctx->lock);
- ctx->pwm = devm_of_pwm_get(&pdev->dev, pdev->dev.of_node, NULL);
+ ctx->pwm = devm_of_pwm_get(dev, dev->of_node, NULL);
if (IS_ERR(ctx->pwm)) {
ret = PTR_ERR(ctx->pwm);
if (ret != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Could not get PWM: %d\n", ret);
+ dev_err(dev, "Could not get PWM: %d\n", ret);
return ret;
}
platform_set_drvdata(pdev, ctx);
- ctx->reg_en = devm_regulator_get_optional(&pdev->dev, "fan");
+ ctx->reg_en = devm_regulator_get_optional(dev, "fan");
if (IS_ERR(ctx->reg_en)) {
if (PTR_ERR(ctx->reg_en) != -ENODEV)
return PTR_ERR(ctx->reg_en);
@@ -242,10 +253,11 @@ static int pwm_fan_probe(struct platform_device *pdev)
} else {
ret = regulator_enable(ctx->reg_en);
if (ret) {
- dev_err(&pdev->dev,
- "Failed to enable fan supply: %d\n", ret);
+ dev_err(dev, "Failed to enable fan supply: %d\n", ret);
return ret;
}
+ devm_add_action_or_reset(dev, pwm_fan_regulator_disable,
+ ctx->reg_en);
}
ctx->pwm_value = MAX_PWM;
@@ -257,62 +269,36 @@ static int pwm_fan_probe(struct platform_device *pdev)
ret = pwm_apply_state(ctx->pwm, &state);
if (ret) {
- dev_err(&pdev->dev, "Failed to configure PWM\n");
- goto err_reg_disable;
+ dev_err(dev, "Failed to configure PWM\n");
+ return ret;
}
+ devm_add_action_or_reset(dev, pwm_fan_pwm_disable, ctx->pwm);
- hwmon = devm_hwmon_device_register_with_groups(&pdev->dev, "pwmfan",
+ hwmon = devm_hwmon_device_register_with_groups(dev, "pwmfan",
ctx, pwm_fan_groups);
if (IS_ERR(hwmon)) {
- dev_err(&pdev->dev, "Failed to register hwmon device\n");
- ret = PTR_ERR(hwmon);
- goto err_pwm_disable;
+ dev_err(dev, "Failed to register hwmon device\n");
+ return PTR_ERR(hwmon);
}
- ret = pwm_fan_of_get_cooling_data(&pdev->dev, ctx);
+ ret = pwm_fan_of_get_cooling_data(dev, ctx);
if (ret)
return ret;
ctx->pwm_fan_state = ctx->pwm_fan_max_state;
if (IS_ENABLED(CONFIG_THERMAL)) {
- cdev = thermal_of_cooling_device_register(pdev->dev.of_node,
- "pwm-fan", ctx,
- &pwm_fan_cooling_ops);
+ cdev = devm_thermal_of_cooling_device_register(dev,
+ dev->of_node, "pwm-fan", ctx, &pwm_fan_cooling_ops);
if (IS_ERR(cdev)) {
- dev_err(&pdev->dev,
+ dev_err(dev,
"Failed to register pwm-fan as cooling device");
- ret = PTR_ERR(cdev);
- goto err_pwm_disable;
+ return PTR_ERR(cdev);
}
ctx->cdev = cdev;
thermal_cdev_update(cdev);
}
return 0;
-
-err_pwm_disable:
- state.enabled = false;
- pwm_apply_state(ctx->pwm, &state);
-
-err_reg_disable:
- if (ctx->reg_en)
- regulator_disable(ctx->reg_en);
-
- return ret;
-}
-
-static int pwm_fan_remove(struct platform_device *pdev)
-{
- struct pwm_fan_ctx *ctx = platform_get_drvdata(pdev);
-
- thermal_cooling_device_unregister(ctx->cdev);
- if (ctx->pwm_value)
- pwm_disable(ctx->pwm);
-
- if (ctx->reg_en)
- regulator_disable(ctx->reg_en);
-
- return 0;
}
#ifdef CONFIG_PM_SLEEP
@@ -380,7 +366,6 @@ MODULE_DEVICE_TABLE(of, of_pwm_fan_match);
static struct platform_driver pwm_fan_driver = {
.probe = pwm_fan_probe,
- .remove = pwm_fan_remove,
.driver = {
.name = "pwm-fan",
.pm = &pwm_fan_pm,
--
2.7.4
^ permalink raw reply related
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