* [PATCH v2 3/4] media: dt-bindings: aspeed-video: Add missing memory-region property
From: Eddie James @ 2019-04-24 15:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556119020-7609-1-git-send-email-eajames@linux.ibm.com>
Missed documenting this property in the initial commit.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
Changes since v1:
- Add missing semi-colon
Documentation/devicetree/bindings/media/aspeed-video.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/aspeed-video.txt b/Documentation/devicetree/bindings/media/aspeed-video.txt
index 78b464a..ce28945 100644
--- a/Documentation/devicetree/bindings/media/aspeed-video.txt
+++ b/Documentation/devicetree/bindings/media/aspeed-video.txt
@@ -14,6 +14,11 @@ Required properties:
the VE
- interrupts: the interrupt associated with the VE on this platform
+Optional properties:
+ - memory-region:
+ phandle to a memory region to allocate from, as defined in
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
Example:
video-engine at 1e700000 {
@@ -23,4 +28,5 @@ video-engine at 1e700000 {
clock-names = "vclk", "eclk";
resets = <&syscon ASPEED_RESET_VIDEO>;
interrupts = <7>;
+ memory-region = <&video_engine_memory>;
};
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 4/4] ARM: dts: aspeed-g5: Add video engine
From: Eddie James @ 2019-04-24 15:19 UTC (permalink / raw)
To: linux-aspeed
Add a node to describe the video engine on the AST2500.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 85ed9db..c6d5edc 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -243,6 +243,16 @@
status = "disabled";
};
+ video: video at 1e700000 {
+ compatible = "aspeed,ast2500-video-engine";
+ reg = <0x1e700000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
+ <&syscon ASPEED_CLK_GATE_ECLK>;
+ clock-names = "vclk", "eclk";
+ interrupts = <7>;
+ status = "disabled";
+ };
+
sram: sram at 1e720000 {
compatible = "mmio-sram";
reg = <0x1e720000 0x9000>; // 36K
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Andrew Peng @ 2019-04-24 17:39 UTC (permalink / raw)
To: linux-aspeed
Initial introduction of Lenovo Hr630 family equipped with
Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Lenovo.
Specifically, This adds the Hr630 platform device tree file
used by the Hr630 BMC machines.
This also adds an entry of Hr630 device tree file in Makefile
Signed-off-by: Andrew Peng <pengms1@lenovo.com>
Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
---
Changes in v4:
- add pca9546 switch aliases name.
Changes in v3:
- revise i2c switch aliases name.
Changes in v2:
- add i2c switch aliases name.
- remove the unused eeprom device from DT file.
- remove "Licensed under..." sentence.
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 890 ++++++++++++++++++++++++++
2 files changed, 892 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aea..375e53b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
- aspeed-bmc-quanta-q71l.dtb
+ aspeed-bmc-quanta-q71l.dtb \
+ aspeed-bmc-lenovo-hr630.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
new file mode 100644
index 0000000..41d5689
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -0,0 +1,890 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Lenovo Hr630 platform
+ *
+ * Copyright (C) 2019-present Lenovo
+ */
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "HR630 BMC";
+ compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
+
+ aliases {
+ pca9545_i2c0 = &i2c_rbp;
+ pca9545_i2c1 = &i2c_fbp1;
+ pca9545_i2c2 = &i2c_fbp2;
+ pca9545_i2c3 = &i2c_fbp3;
+ pca9546_i2c0 = &i2c_riser2;
+ pca9546_i2c1 = &i2c_pcie4;
+ pca9546_i2c2 = &i2c_riser1;
+ pca9546_i2c3 = &i2c_ocp;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region at 98000000 {
+ no-map;
+ reg = <0x98000000 0x00100000>; /* 1M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ /* temp1 inlet */
+ tmp75 at 4e {
+ compatible = "national,lm75";
+ reg = <0x4e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ /* temp2 outlet */
+ tmp75 at 4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 70 next. */
+
+ i2c_rbp: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_fbp1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_fbp2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_fbp3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+ i2c-switch at 76 {
+ compatible = "nxp,pca9546";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 76 next. */
+
+ i2c_riser2: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_riser1: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_ocp: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom at 57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+/*
+ * Enable port A as device (via the virtual hub) and port B as
+ * host by default on the eval board. This can be easily changed
+ * by replacing the override below with &ehci0 { ... } to enable
+ * host on both ports.
+ */
+&vhub {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan at 0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan at 1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan at 2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan at 3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan at 4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan at 5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan at 6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan at 7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan at 8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan at 9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan at 10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan at 11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan at 12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan at 13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+};
+
+&gpio {
+
+ pin_gpio_a0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MAC1_INT_N";
+ };
+
+ pin_gpio_a1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_C_PRESENT_N";
+ };
+
+ pin_gpio_a2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_PRST";
+ };
+
+ pin_gpio_a3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_PRST";
+ };
+
+ pin_gpio_b5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "IRQ_BMC_PCH_SMI_LPC_N";
+ };
+
+ pin_gpio_f0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "IRQ_BMC_PCH_NMI_R";
+ };
+
+ pin_gpio_f1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU1_DISABLE_COD_N";
+ };
+
+ pin_gpio_f2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "SMB_LAN_ALERT_N_MEZZ";
+ };
+
+ pin_gpio_f3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS0_RST_OUT_N";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT0_FAULT_LED";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT1_FAULT_LED";
+ };
+
+ pin_gpio_f6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_BMC_CPLD_NMI";
+ };
+
+ pin_gpio_f7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_ALERT_N";
+ };
+
+ pin_gpio_g0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_ERR2_LVT3_N";
+ };
+
+ pin_gpio_g1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
+ };
+
+ pin_gpio_g2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PCH_BMC_THERMTRIP_N";
+ };
+
+ pin_gpio_g3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_I2C_BUS7_INT_N";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_PWR_CTL_N";
+ };
+
+ pin_gpio_g5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NFC_FD_N";
+ };
+
+ pin_gpio_g6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_NMI_EVENT_N";
+ };
+
+ pin_gpio_g7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_PCIE_I2CMUX_N";
+ };
+
+ pin_gpio_h0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_EPOW_N_R";
+ };
+
+ pin_gpio_h1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_EPOW_N_R";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU1_FFS_N_R";
+ };
+
+ pin_gpio_h3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU2_FFS_N_R";
+ };
+
+ pin_gpio_h4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_THROTTLE_N_R";
+ };
+
+ pin_gpio_h5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_THROTTLE_N_R";
+ };
+
+ pin_gpio_h6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_SMB_RESET_N";
+ };
+
+ pin_gpio_h7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_SMB_RESET_N";
+ };
+
+ pin_gpio_i1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_PWR_BTN_N";
+ };
+
+ pin_gpio_i2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BIOS_RCVR_N";
+ };
+
+ pin_gpio_i3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_INTRUDED_COVER";
+ };
+
+ pin_gpio_j2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_BIOS_UPDATE_N";
+ };
+
+ pin_gpio_j3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_HDD_I2CMUX_N";
+ };
+
+ pin_gpio_q4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_A_PRESENT_N";
+ };
+
+ pin_gpio_q5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VGA_FRONT_PRES_N";
+ };
+
+ pin_gpio_q6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_RISER1_INT_N";
+ };
+
+ pin_gpio_q7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NCSI_CABLE_DET_N";
+ };
+
+ pin_gpio_r0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_RST_BTN_N";
+ };
+
+ pin_gpio_r2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG1_DETECT_N";
+ };
+
+ pin_gpio_r3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG2_DETECT_N";
+ };
+
+ pin_gpio_r4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG3_DETECT_N";
+ };
+
+ pin_gpio_r5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VIDEO_CABLE_DETECT_N";
+ };
+
+ pin_gpio_s0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_PS_RAPIDON_WAKE_R_N";
+ };
+
+ pin_gpio_s1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HOST_TPM_PP_BUF";
+ };
+
+ pin_gpio_s2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_VGA_SW";
+ };
+
+ pin_gpio_s3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SML0_ALERT_MUX_N";
+ };
+
+ pin_gpio_s4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "VBAT_EN_N";
+ };
+
+ pin_gpio_s5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_4";
+ };
+
+ pin_gpio_s6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PU_BMC_GPIOS6";
+ };
+
+ pin_gpio_s7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_BUS7_RESET_N";
+ };
+
+ pin_gpio_y0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S0";
+ };
+
+ pin_gpio_y1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S1";
+ };
+
+ pin_gpio_y2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "UID_ALERT_N";
+ };
+
+ pin_gpio_z0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_INT_N";
+ };
+
+ pin_gpio_z2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_RESET_N";
+ };
+
+ pin_gpio_z3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FM_BMC_PCH_SCI_LPC_N";
+ };
+
+ pin_gpio_z4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_17";
+ };
+
+ pin_gpio_z6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_20";
+ };
+
+ pin_gpio_z7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_POST_CMPLT_N";
+ };
+
+ pin_gpio_aa0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "HOST_BMC_USB_SEL";
+ };
+
+ pin_gpio_aa1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_ALERT_N";
+ };
+
+ pin_gpio_aa2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "USB_CABLE_DETECT_N";
+ };
+
+ pin_gpio_aa5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS1_RST_OUT_N";
+ };
+
+ pin_gpio_aa6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SMI_ACTIVE_N";
+ };
+
+ pin_gpio_aa7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_BIOS_POST_CMPLT_N";
+ };
+
+ pin_gpio_ab0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_TPM_MOD_PRES_N";
+ };
+
+ pin_gpio_ab1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FORCE_NMI_SW_FPGA_N";
+ };
+
+ pin_gpio_ab2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "1U_2U_PCBA_SEL_R";
+ };
+
+ pin_gpio_ab3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "INTRUDED_PRES_N";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 3/4] media: dt-bindings: aspeed-video: Add missing memory-region property
From: Rob Herring @ 2019-04-24 21:17 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556119020-7609-4-git-send-email-eajames@linux.ibm.com>
On Wed, 24 Apr 2019 10:16:59 -0500, Eddie James wrote:
> Missed documenting this property in the initial commit.
>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
> ---
> Changes since v1:
> - Add missing semi-colon
>
> Documentation/devicetree/bindings/media/aspeed-video.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
^ permalink raw reply
* [PATCH v4] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Benjamin Fair @ 2019-04-25 3:51 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556127550-234791-1-git-send-email-pengms1@lenovo.com>
On Wed, Apr 24, 2019 at 10:39 AM Andrew Peng <pengms1@lenovo.com> wrote:
>
> Initial introduction of Lenovo Hr630 family equipped with
> Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
> with a ASPEED ast2500 BMC manufactured by Lenovo.
> Specifically, This adds the Hr630 platform device tree file
> used by the Hr630 BMC machines.
>
> This also adds an entry of Hr630 device tree file in Makefile
>
> Signed-off-by: Andrew Peng <pengms1@lenovo.com>
> Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
> Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
> ---
> Changes in v4:
> - add pca9546 switch aliases name.
> Changes in v3:
> - revise i2c switch aliases name.
> Changes in v2:
> - add i2c switch aliases name.
> - remove the unused eeprom device from DT file.
> - remove "Licensed under..." sentence.
>
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 890 ++++++++++++++++++++++++++
> 2 files changed, 892 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f4f5aea..375e53b 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> aspeed-bmc-opp-witherspoon.dtb \
> aspeed-bmc-opp-zaius.dtb \
> aspeed-bmc-portwell-neptune.dtb \
> - aspeed-bmc-quanta-q71l.dtb
> + aspeed-bmc-quanta-q71l.dtb \
> + aspeed-bmc-lenovo-hr630.dtb
> diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
> new file mode 100644
> index 0000000..41d5689
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
> @@ -0,0 +1,890 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Device Tree file for Lenovo Hr630 platform
> + *
> + * Copyright (C) 2019-present Lenovo
> + */
> +
> +/dts-v1/;
> +
> +#include "aspeed-g5.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +
> +/ {
> + model = "HR630 BMC";
> + compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
> +
> + aliases {
> + pca9545_i2c0 = &i2c_rbp;
> + pca9545_i2c1 = &i2c_fbp1;
> + pca9545_i2c2 = &i2c_fbp2;
> + pca9545_i2c3 = &i2c_fbp3;
> + pca9546_i2c0 = &i2c_riser2;
> + pca9546_i2c1 = &i2c_pcie4;
> + pca9546_i2c2 = &i2c_riser1;
> + pca9546_i2c3 = &i2c_ocp;
I don't think these aliases do what Patrick was requesting. The i2c
driver in the kernel will assign a fixed numbering to a bus if it has
an alias of the form "i2c##". So "i2c14 = &i2c_rbp" would cause the
bus to be numbered 14 and create a device node called "/dev/i2c-14".
You can see an example of this in arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
> + };
> +
> + chosen {
> + stdout-path = &uart5;
> + bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flash_memory: region at 98000000 {
> + no-map;
> + reg = <0x98000000 0x00100000>; /* 1M */
> + };
> +
> + gfx_memory: framebuffer {
> + size = <0x01000000>;
> + alignment = <0x01000000>;
> + compatible = "shared-dma-pool";
> + reusable;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + heartbeat {
> + gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
> + };
> +
> + fault {
> + gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + iio-hwmon {
> + compatible = "iio-hwmon";
> + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
> + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
> + <&adc 8>, <&adc 9>, <&adc 10>,
> + <&adc 12>, <&adc 13>, <&adc 14>;
> + };
> +
> +};
> +
> +&fmc {
> + status = "okay";
> + flash at 0 {
> + status = "okay";
> + m25p,fast-read;
> + label = "bmc";
> + spi-max-frequency = <50000000>;
> +#include "openbmc-flash-layout.dtsi"
> + };
> +};
> +
> +&lpc_ctrl {
> + status = "okay";
> + memory-region = <&flash_memory>;
> + flash = <&spi1>;
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&vuart {
> + status = "okay";
> +};
> +
> +&ibt {
> + status = "okay";
> +};
> +
> +&mac0 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rmii1_default>;
> + use-ncsi;
> +};
> +
> +&mac1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
> +};
> +
> +&adc {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + /* temp1 inlet */
> + tmp75 at 4e {
> + compatible = "national,lm75";
> + reg = <0x4e>;
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> + /* temp2 outlet */
> + tmp75 at 4d {
> + compatible = "national,lm75";
> + reg = <0x4d>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +};
> +
> +&i2c3 {
> + status = "okay";
> +};
> +
> +&i2c4 {
> + status = "okay";
> +};
> +
> +&i2c5 {
> + status = "okay";
> +};
> +
> +&i2c6 {
> + status = "okay";
> + /* Slot 0,
> + * Slot 1,
> + * Slot 2,
> + * Slot 3
> + */
> +
> + i2c-switch at 70 {
> + compatible = "nxp,pca9545";
> + reg = <0x70>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect; /* may use mux at 70 next. */
> +
> + i2c_rbp: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_fbp1: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_fbp2: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_fbp3: i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c7 {
> + status = "okay";
> +
> + /* Slot 0,
> + * Slot 1,
> + * Slot 2,
> + * Slot 3
> + */
> + i2c-switch at 76 {
> + compatible = "nxp,pca9546";
> + reg = <0x76>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect; /* may use mux at 76 next. */
> +
> + i2c_riser2: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_pcie4: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_riser1: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_ocp: i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c8 {
> + status = "okay";
> +
> + eeprom at 57 {
> + compatible = "atmel,24c256";
> + reg = <0x57>;
> + pagesize = <16>;
> + };
> +};
> +
> +&i2c9 {
> + status = "okay";
> +};
> +
> +&i2c10 {
> + status = "okay";
> +};
> +
> +&i2c11 {
> + status = "okay";
> +};
> +
> +&i2c12 {
> + status = "okay";
> +};
> +
> +/*
> + * Enable port A as device (via the virtual hub) and port B as
> + * host by default on the eval board. This can be easily changed
> + * by replacing the override below with &ehci0 { ... } to enable
> + * host on both ports.
> + */
> +&vhub {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&uhci {
> + status = "okay";
> +};
> +
> +&gfx {
> + status = "okay";
> + memory-region = <&gfx_memory>;
> +};
> +
> +&pwm_tacho {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm0_default
> + &pinctrl_pwm1_default
> + &pinctrl_pwm2_default
> + &pinctrl_pwm3_default
> + &pinctrl_pwm4_default
> + &pinctrl_pwm5_default
> + &pinctrl_pwm6_default>;
> +
> + fan at 0 {
> + reg = <0x00>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x00>;
> + };
> +
> + fan at 1 {
> + reg = <0x00>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x01>;
> + };
> +
> + fan at 2 {
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x02>;
> + };
> +
> + fan at 3 {
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x03>;
> + };
> +
> + fan at 4 {
> + reg = <0x02>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x04>;
> + };
> +
> + fan at 5 {
> + reg = <0x02>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x05>;
> + };
> +
> + fan at 6 {
> + reg = <0x03>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x06>;
> + };
> +
> + fan at 7 {
> + reg = <0x03>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x07>;
> + };
> +
> + fan at 8 {
> + reg = <0x04>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x08>;
> + };
> +
> + fan at 9 {
> + reg = <0x04>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x09>;
> + };
> +
> + fan at 10 {
> + reg = <0x05>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
> + };
> +
> + fan at 11 {
> + reg = <0x05>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
> + };
> +
> + fan at 12 {
> + reg = <0x06>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
> + };
> +
> + fan at 13 {
> + reg = <0x06>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
> + };
> +};
> +
> +&gpio {
> +
> + pin_gpio_a0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MAC1_INT_N";
> + };
> +
> + pin_gpio_a1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MEZZ_C_PRESENT_N";
> + };
> +
> + pin_gpio_a2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_PRST";
> + };
> +
> + pin_gpio_a3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_PRST";
> + };
> +
> + pin_gpio_b5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "IRQ_BMC_PCH_SMI_LPC_N";
> + };
> +
> + pin_gpio_f0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "IRQ_BMC_PCH_NMI_R";
> + };
> +
> + pin_gpio_f1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU1_DISABLE_COD_N";
> + };
> +
> + pin_gpio_f2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "SMB_LAN_ALERT_N_MEZZ";
> + };
> +
> + pin_gpio_f3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_BUS0_RST_OUT_N";
> + };
> +
> + pin_gpio_f4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "FM_SKT0_FAULT_LED";
> + };
> +
> + pin_gpio_f5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "FM_SKT1_FAULT_LED";
> + };
> +
> + pin_gpio_f6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_BMC_CPLD_NMI";
> + };
> +
> + pin_gpio_f7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_ALERT_N";
> + };
> +
> + pin_gpio_g0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU_ERR2_LVT3_N";
> + };
> +
> + pin_gpio_g1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
> + };
> +
> + pin_gpio_g2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PCH_BMC_THERMTRIP_N";
> + };
> +
> + pin_gpio_g3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_I2C_BUS7_INT_N";
> + };
> +
> + pin_gpio_g4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "FAN_PWR_CTL_N";
> + };
> +
> + pin_gpio_g5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "NFC_FD_N";
> + };
> +
> + pin_gpio_g6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_NMI_EVENT_N";
> + };
> +
> + pin_gpio_g7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "RST_BMC_PCIE_I2CMUX_N";
> + };
> +
> + pin_gpio_h0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_EPOW_N_R";
> + };
> +
> + pin_gpio_h1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_EPOW_N_R";
> + };
> +
> + pin_gpio_h2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PSU1_FFS_N_R";
> + };
> +
> + pin_gpio_h3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PSU2_FFS_N_R";
> + };
> +
> + pin_gpio_h4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_THROTTLE_N_R";
> + };
> +
> + pin_gpio_h5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_THROTTLE_N_R";
> + };
> +
> + pin_gpio_h6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_SMB_RESET_N";
> + };
> +
> + pin_gpio_h7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU2_SMB_RESET_N";
> + };
> +
> + pin_gpio_i1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FP_PWR_BTN_N";
> + };
> +
> + pin_gpio_i2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BIOS_RCVR_N";
> + };
> +
> + pin_gpio_i3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_INTRUDED_COVER";
> + };
> +
> + pin_gpio_j2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_BIOS_UPDATE_N";
> + };
> +
> + pin_gpio_j3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "RST_BMC_HDD_I2CMUX_N";
> + };
> +
> + pin_gpio_q4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "MEZZ_A_PRESENT_N";
> + };
> +
> + pin_gpio_q5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "VGA_FRONT_PRES_N";
> + };
> +
> + pin_gpio_q6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "I2C_RISER1_INT_N";
> + };
> +
> + pin_gpio_q7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "NCSI_CABLE_DET_N";
> + };
> +
> + pin_gpio_r0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FP_RST_BTN_N";
> + };
> +
> + pin_gpio_r2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG1_DETECT_N";
> + };
> +
> + pin_gpio_r3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG2_DETECT_N";
> + };
> +
> + pin_gpio_r4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HDDSIG3_DETECT_N";
> + };
> +
> + pin_gpio_r5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "VIDEO_CABLE_DETECT_N";
> + };
> +
> + pin_gpio_s0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_PS_RAPIDON_WAKE_R_N";
> + };
> +
> + pin_gpio_s1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "HOST_TPM_PP_BUF";
> + };
> +
> + pin_gpio_s2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_VGA_SW";
> + };
> +
> + pin_gpio_s3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_SML0_ALERT_MUX_N";
> + };
> +
> + pin_gpio_s4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
> + output;
> + line-name = "VBAT_EN_N";
> + };
> +
> + pin_gpio_s5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_4";
> + };
> +
> + pin_gpio_s6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "PU_BMC_GPIOS6";
> + };
> +
> + pin_gpio_s7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "I2C_BUS7_RESET_N";
> + };
> +
> + pin_gpio_y0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_NCSI_MUX_CTL_S0";
> + };
> +
> + pin_gpio_y1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_NCSI_MUX_CTL_S1";
> + };
> +
> + pin_gpio_y2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "UID_ALERT_N";
> + };
> +
> + pin_gpio_z0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_RISER2_INT_N";
> + };
> +
> + pin_gpio_z2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_RISER2_RESET_N";
> + };
> +
> + pin_gpio_z3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "FM_BMC_PCH_SCI_LPC_N";
> + };
> +
> + pin_gpio_z4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_17";
> + };
> +
> + pin_gpio_z6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "BMC_HW_STRAP_20";
> + };
> +
> + pin_gpio_z7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "BMC_POST_CMPLT_N";
> + };
> +
> + pin_gpio_aa0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
> + output-low;
> + line-name = "HOST_BMC_USB_SEL";
> + };
> +
> + pin_gpio_aa1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "PSU1_ALERT_N";
> + };
> +
> + pin_gpio_aa2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
> + };
> +
> + pin_gpio_aa3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
> + };
> +
> + pin_gpio_aa4 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "USB_CABLE_DETECT_N";
> + };
> +
> + pin_gpio_aa5 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "I2C_BUS1_RST_OUT_N";
> + };
> +
> + pin_gpio_aa6 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "IRQ_SMI_ACTIVE_N";
> + };
> +
> + pin_gpio_aa7 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_BIOS_POST_CMPLT_N";
> + };
> +
> + pin_gpio_ab0 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FM_TPM_MOD_PRES_N";
> + };
> +
> + pin_gpio_ab1 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "FORCE_NMI_SW_FPGA_N";
> + };
> +
> + pin_gpio_ab2 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "1U_2U_PCBA_SEL_R";
> + };
> +
> + pin_gpio_ab3 {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
> + input;
> + line-name = "INTRUDED_PRES_N";
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v5] ARM: dts: aspeed: Adding Lenovo Hr630 BMC
From: Andrew Peng @ 2019-04-25 6:48 UTC (permalink / raw)
To: linux-aspeed
Initial introduction of Lenovo Hr630 family equipped with
Aspeed 2500 BMC SoC. Hr630 is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Lenovo.
Specifically, This adds the Hr630 platform device tree file
used by the Hr630 BMC machines.
This also adds an entry of Hr630 device tree file in Makefile
Signed-off-by: Andrew Peng <pengms1@lenovo.com>
Signed-off-by: Yonghui Liu <liuyh21@lenovo.com>
Signed-off-by: Lisa Liu <liuyj19@lenovo.com>
---
Changes in v5:
- revise pca9545 and pca9546 switch aliases name.
Changes in v4:
- add pca9546 switch aliases name.
Changes in v3:
- revise i2c switch aliases name.
Changes in v2:
- add i2c switch aliases name.
- remove the unused eeprom device from DT file.
- remove "Licensed under..." sentence.
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 890 ++++++++++++++++++++++++++
2 files changed, 892 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aea..375e53b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1261,4 +1261,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
- aspeed-bmc-quanta-q71l.dtb
+ aspeed-bmc-quanta-q71l.dtb \
+ aspeed-bmc-lenovo-hr630.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
new file mode 100644
index 0000000..4f18f4d
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -0,0 +1,890 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Lenovo Hr630 platform
+ *
+ * Copyright (C) 2019-present Lenovo
+ */
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "HR630 BMC";
+ compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
+
+ aliases {
+ i2c14 = &i2c_rbp;
+ i2c15 = &i2c_fbp1;
+ i2c16 = &i2c_fbp2;
+ i2c17 = &i2c_fbp3;
+ i2c18 = &i2c_riser2;
+ i2c19 = &i2c_pcie4;
+ i2c20 = &i2c_riser1;
+ i2c21 = &i2c_ocp;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region at 98000000 {
+ no-map;
+ reg = <0x98000000 0x00100000>; /* 1M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ /* temp1 inlet */
+ tmp75 at 4e {
+ compatible = "national,lm75";
+ reg = <0x4e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ /* temp2 outlet */
+ tmp75 at 4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 70 next. */
+
+ i2c_rbp: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_fbp1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_fbp2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_fbp3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+ i2c-switch at 76 {
+ compatible = "nxp,pca9546";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux at 76 next. */
+
+ i2c_riser2: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_riser1: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_ocp: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom at 57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+/*
+ * Enable port A as device (via the virtual hub) and port B as
+ * host by default on the eval board. This can be easily changed
+ * by replacing the override below with &ehci0 { ... } to enable
+ * host on both ports.
+ */
+&vhub {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan at 0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan at 1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan at 2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan at 3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan at 4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan at 5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan at 6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan at 7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan at 8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan at 9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan at 10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan at 11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan at 12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan at 13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+};
+
+&gpio {
+
+ pin_gpio_a0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MAC1_INT_N";
+ };
+
+ pin_gpio_a1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_C_PRESENT_N";
+ };
+
+ pin_gpio_a2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_PRST";
+ };
+
+ pin_gpio_a3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_PRST";
+ };
+
+ pin_gpio_b5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "IRQ_BMC_PCH_SMI_LPC_N";
+ };
+
+ pin_gpio_f0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "IRQ_BMC_PCH_NMI_R";
+ };
+
+ pin_gpio_f1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU1_DISABLE_COD_N";
+ };
+
+ pin_gpio_f2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "SMB_LAN_ALERT_N_MEZZ";
+ };
+
+ pin_gpio_f3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS0_RST_OUT_N";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT0_FAULT_LED";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT1_FAULT_LED";
+ };
+
+ pin_gpio_f6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_BMC_CPLD_NMI";
+ };
+
+ pin_gpio_f7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_ALERT_N";
+ };
+
+ pin_gpio_g0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_ERR2_LVT3_N";
+ };
+
+ pin_gpio_g1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_CPU_MSMI_CATERR_LVT3_N";
+ };
+
+ pin_gpio_g2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PCH_BMC_THERMTRIP_N";
+ };
+
+ pin_gpio_g3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_I2C_BUS7_INT_N";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_PWR_CTL_N";
+ };
+
+ pin_gpio_g5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NFC_FD_N";
+ };
+
+ pin_gpio_g6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_NMI_EVENT_N";
+ };
+
+ pin_gpio_g7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_PCIE_I2CMUX_N";
+ };
+
+ pin_gpio_h0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_EPOW_N_R";
+ };
+
+ pin_gpio_h1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_EPOW_N_R";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU1_FFS_N_R";
+ };
+
+ pin_gpio_h3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU2_FFS_N_R";
+ };
+
+ pin_gpio_h4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_THROTTLE_N_R";
+ };
+
+ pin_gpio_h5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_THROTTLE_N_R";
+ };
+
+ pin_gpio_h6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_SMB_RESET_N";
+ };
+
+ pin_gpio_h7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU2_SMB_RESET_N";
+ };
+
+ pin_gpio_i1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_PWR_BTN_N";
+ };
+
+ pin_gpio_i2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BIOS_RCVR_N";
+ };
+
+ pin_gpio_i3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_INTRUDED_COVER";
+ };
+
+ pin_gpio_j2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_BIOS_UPDATE_N";
+ };
+
+ pin_gpio_j3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_HDD_I2CMUX_N";
+ };
+
+ pin_gpio_q4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MEZZ_A_PRESENT_N";
+ };
+
+ pin_gpio_q5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VGA_FRONT_PRES_N";
+ };
+
+ pin_gpio_q6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_RISER1_INT_N";
+ };
+
+ pin_gpio_q7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "NCSI_CABLE_DET_N";
+ };
+
+ pin_gpio_r0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FP_RST_BTN_N";
+ };
+
+ pin_gpio_r2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG1_DETECT_N";
+ };
+
+ pin_gpio_r3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG2_DETECT_N";
+ };
+
+ pin_gpio_r4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HDDSIG3_DETECT_N";
+ };
+
+ pin_gpio_r5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "VIDEO_CABLE_DETECT_N";
+ };
+
+ pin_gpio_s0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_PS_RAPIDON_WAKE_R_N";
+ };
+
+ pin_gpio_s1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "HOST_TPM_PP_BUF";
+ };
+
+ pin_gpio_s2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_VGA_SW";
+ };
+
+ pin_gpio_s3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SML0_ALERT_MUX_N";
+ };
+
+ pin_gpio_s4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "VBAT_EN_N";
+ };
+
+ pin_gpio_s5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_4";
+ };
+
+ pin_gpio_s6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PU_BMC_GPIOS6";
+ };
+
+ pin_gpio_s7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "I2C_BUS7_RESET_N";
+ };
+
+ pin_gpio_y0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S0";
+ };
+
+ pin_gpio_y1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S1";
+ };
+
+ pin_gpio_y2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "UID_ALERT_N";
+ };
+
+ pin_gpio_z0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_INT_N";
+ };
+
+ pin_gpio_z2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_RESET_N";
+ };
+
+ pin_gpio_z3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FM_BMC_PCH_SCI_LPC_N";
+ };
+
+ pin_gpio_z4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_17";
+ };
+
+ pin_gpio_z6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_HW_STRAP_20";
+ };
+
+ pin_gpio_z7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_POST_CMPLT_N";
+ };
+
+ pin_gpio_aa0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "HOST_BMC_USB_SEL";
+ };
+
+ pin_gpio_aa1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PSU1_ALERT_N";
+ };
+
+ pin_gpio_aa2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU0_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_PVCCIN_CPU1_PWR_IN_ALERT_N";
+ };
+
+ pin_gpio_aa4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "USB_CABLE_DETECT_N";
+ };
+
+ pin_gpio_aa5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS1_RST_OUT_N";
+ };
+
+ pin_gpio_aa6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "IRQ_SMI_ACTIVE_N";
+ };
+
+ pin_gpio_aa7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_BIOS_POST_CMPLT_N";
+ };
+
+ pin_gpio_ab0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FM_TPM_MOD_PRES_N";
+ };
+
+ pin_gpio_ab1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "FORCE_NMI_SW_FPGA_N";
+ };
+
+ pin_gpio_ab2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 2) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "1U_2U_PCBA_SEL_R";
+ };
+
+ pin_gpio_ab3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "INTRUDED_PRES_N";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 3/4] media: dt-bindings: aspeed-video: Add missing memory-region property
From: Hans Verkuil @ 2019-04-25 7:19 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190424211732.GA18914@bogus>
On 4/24/19 11:17 PM, Rob Herring wrote:
> On Wed, 24 Apr 2019 10:16:59 -0500, Eddie James wrote:
>> Missed documenting this property in the initial commit.
>>
>> Signed-off-by: Eddie James <eajames@linux.ibm.com>
>> ---
>> Changes since v1:
>> - Add missing semi-colon
>>
>> Documentation/devicetree/bindings/media/aspeed-video.txt | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
>
I noticed the same when I was processing this patch. I've added back your
'Reviewed-by' tag.
So there is no need to repost, Eddie. Just remember this for the next
time :-)
Regards,
Hans
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Greg KH @ 2019-04-25 17:25 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAO=notz9QVoqKLrhJ3kx9FHja5+Mh68f36O36+1ewLG+SanmOA@mail.gmail.com>
On Tue, Apr 23, 2019 at 08:28:14AM -0700, Patrick Venture wrote:
> On Tue, Apr 23, 2019 at 8:22 AM Patrick Venture <venture@google.com> wrote:
> >
> > On Tue, Apr 23, 2019 at 7:26 AM Patrick Venture <venture@google.com> wrote:
> > >
> > > Create a SoC folder for the ASPEED parts and place the misc drivers
> > > currently present into this folder. These drivers are not generic part
> > > drivers, but rather only apply to the ASPEED SoCs.
> > >
> > > Signed-off-by: Patrick Venture <venture@google.com>
> >
> > Accidentally lost the Acked-by when re-sending this patchset as I
> > didn't see it on v1 before re-sending v2 to the larger audience.
>
> Since there was a change between v1 and v2, Arnd, I'd appreciate you
> Ack this version of the patchset since it changes when the soc/aspeed
> Makefile is followed.
I have no objection for moving stuff out of drivers/misc/ so the SOC
maintainers are free to take this.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* [PATCH 1/2] ARM: dts: aspeed: Add aspeed-p2a-ctrl node
From: Patrick Venture @ 2019-04-25 19:48 UTC (permalink / raw)
To: linux-aspeed
Add a node for the aspeed-p2a-ctrl module. This node, when enabled will
disable the PCI-to-AHB bridge and then allow control of this bridge via
ioctls, and access via mmap.
Signed-off-by: Patrick Venture <venture@google.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 4 ++++
arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9549f867aa1ef..0b7bc6072aed0 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -165,6 +165,10 @@
compatible = "aspeed,g4-pinctrl";
};
+ p2a: p2a-control {
+ compatible = "aspeed,ast2400-p2a-ctrl";
+ status = "disabled";
+ };
};
rng: hwrng at 1e6e2078 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 3e4ed081505cc..5f01befcca1e2 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -212,6 +212,11 @@
aspeed,external-nodes = <&gfx &lhc>;
};
+
+ p2a: p2a-control {
+ compatible = "aspeed,ast2500-p2a-ctrl";
+ status = "disabled";
+ };
};
rng: hwrng at 1e6e2078 {
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: aspeed: quanta-q71: Enable p2a node
From: Patrick Venture @ 2019-04-25 19:49 UTC (permalink / raw)
To: linux-aspeed
Enable the aspeed-p2a-ctrl node and configure with memory-region to
enable mmap access.
Signed-off-by: Patrick Venture <venture@google.com>
---
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
index 0d7c6339da465..a68ff0675c28a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -112,6 +112,11 @@
&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
};
+&p2a {
+ status = "okay";
+ memory-region = <&vga_memory>;
+};
+
&ibt {
status = "okay";
};
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [PATCH] fixup! drivers/misc: Add Aspeed P2A control driver
From: Patrick Venture @ 2019-04-25 20:23 UTC (permalink / raw)
To: linux-aspeed
Fixup compiler warnings:
- 108 warning: ISO C90 forbids mixed declarations and code
- 264 warning: unused variable 'value'
- 335 warning: unused variable 'res'
Signed-off-by: Patrick Venture <venture@google.com>
---
drivers/misc/aspeed-p2a-ctrl.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/aspeed-p2a-ctrl.c b/drivers/misc/aspeed-p2a-ctrl.c
index c0521b2ffc6a..9736821972ef 100644
--- a/drivers/misc/aspeed-p2a-ctrl.c
+++ b/drivers/misc/aspeed-p2a-ctrl.c
@@ -99,13 +99,14 @@ static void aspeed_p2a_disable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
{
+ unsigned long vsize;
struct aspeed_p2a_user *priv = file->private_data;
struct aspeed_p2a_ctrl *ctrl = priv->parent;
if (ctrl->mem_base == 0 && ctrl->mem_size == 0)
return -EINVAL;
- unsigned long vsize = vma->vm_end - vma->vm_start;
+ vsize = vma->vm_end - vma->vm_start;
pgprot_t prot = vma->vm_page_prot;
if (vma->vm_pgoff + vsize > ctrl->mem_base + ctrl->mem_size)
@@ -261,7 +262,6 @@ static int aspeed_p2a_open(struct inode *inode, struct file *file)
static int aspeed_p2a_release(struct inode *inode, struct file *file)
{
int i;
- u32 value;
u32 bits = 0;
bool open_regions = false;
struct aspeed_p2a_user *priv = file->private_data;
@@ -332,7 +332,7 @@ static int aspeed_p2a_ctrl_probe(struct platform_device *pdev)
{
struct aspeed_p2a_ctrl *misc_ctrl;
struct device *dev;
- struct resource *res, resm;
+ struct resource resm;
struct device_node *node;
int rc = 0;
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [PATCH] fixup! drivers/misc: Add Aspeed P2A control driver
From: Greg KH @ 2019-04-25 20:36 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190425202347.83880-1-venture@google.com>
On Thu, Apr 25, 2019 at 01:23:47PM -0700, Patrick Venture wrote:
> Fixup compiler warnings:
> - 108 warning: ISO C90 forbids mixed declarations and code
> - 264 warning: unused variable 'value'
> - 335 warning: unused variable 'res'
>
> Signed-off-by: Patrick Venture <venture@google.com>
Reported-by: kbuild...
I'll go add it, next time please do it yourself.
thanks,
greg k-h
^ permalink raw reply
* [PATCH] fixup! drivers/misc: Add Aspeed P2A control driver
From: Patrick Venture @ 2019-04-25 20:37 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190425203652.GA23304@kroah.com>
On Thu, Apr 25, 2019 at 1:36 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Thu, Apr 25, 2019 at 01:23:47PM -0700, Patrick Venture wrote:
> > Fixup compiler warnings:
> > - 108 warning: ISO C90 forbids mixed declarations and code
> > - 264 warning: unused variable 'value'
> > - 335 warning: unused variable 'res'
> >
> > Signed-off-by: Patrick Venture <venture@google.com>
>
> Reported-by: kbuild...
>
> I'll go add it, next time please do it yourself.
Roger that!
>
> thanks,
>
> greg k-h
^ permalink raw reply
* [PATCH v2 3/4] media: dt-bindings: aspeed-video: Add missing memory-region property
From: Eddie James @ 2019-04-26 14:11 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190424211732.GA18914@bogus>
On 4/24/19 4:17 PM, Rob Herring wrote:
> On Wed, 24 Apr 2019 10:16:59 -0500, Eddie James wrote:
>> Missed documenting this property in the initial commit.
>>
>> Signed-off-by: Eddie James <eajames@linux.ibm.com>
>> ---
>> Changes since v1:
>> - Add missing semi-colon
>>
>> Documentation/devicetree/bindings/media/aspeed-video.txt | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
Yes, I left it off because I added a semi-colon (trivial, I know, but it
did change). The change log is there below the commit message.
Thanks,
Eddie
>
^ permalink raw reply
* [PATCH] misc: aspeed-p2a-ctrl: fix mixed declarations
From: Patrick Venture @ 2019-04-26 16:56 UTC (permalink / raw)
To: linux-aspeed
Fix up mixed declarations and code in aspeed_p2a_mmap.
Tested: Verified the build had the error and that this patch resolved it
and there were no other warnings or build errors associated with
compilation of this driver.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Patrick Venture <venture@google.com>
---
drivers/misc/aspeed-p2a-ctrl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/aspeed-p2a-ctrl.c b/drivers/misc/aspeed-p2a-ctrl.c
index 9736821972ef..b60fbeaffcbd 100644
--- a/drivers/misc/aspeed-p2a-ctrl.c
+++ b/drivers/misc/aspeed-p2a-ctrl.c
@@ -100,6 +100,7 @@ static void aspeed_p2a_disable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
{
unsigned long vsize;
+ pgprot_t prot;
struct aspeed_p2a_user *priv = file->private_data;
struct aspeed_p2a_ctrl *ctrl = priv->parent;
@@ -107,7 +108,7 @@ static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
return -EINVAL;
vsize = vma->vm_end - vma->vm_start;
- pgprot_t prot = vma->vm_page_prot;
+ prot = vma->vm_page_prot;
if (vma->vm_pgoff + vsize > ctrl->mem_base + ctrl->mem_size)
return -EINVAL;
--
2.21.0.593.g511ec345e18-goog
^ permalink raw reply related
* [GIT PULL] ARM: aspeed: dts changes for 5.2
From: Olof Johansson @ 2019-04-28 19:17 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XdevZ9LHtVVu=fHbTxSKfDugym3jT0ueKEpa9qhLYbFnw@mail.gmail.com>
On Fri, Apr 05, 2019 at 03:47:38AM +0000, Joel Stanley wrote:
> Hello ARM Maintainers,
>
> Here's the first ASPEED device tree pull request for 5.2. There might be a
> second one later as I pushed out a pair of patches for review today.
>
> The following changes since commit 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b:
>
> Linux 5.1-rc1 (2019-03-17 14:22:26 -0700)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git \
> tags/aspeed-5.2-devicetree
Thanks for easing copy-paste!
>
> for you to fetch changes up to 6d00c6f8d2e781e3c821fc9c614f404cc981804d:
>
> ARM: dts: aspeed: Add RTC node (2019-04-05 14:08:20 +1030)
>
> ----------------------------------------------------------------
> ASPEED device tree updates for 5.2
>
> - RTC and GFX DRM driver went upstream this cycle
>
> - Miscellaneous board updates for Facebook and IBM BMCs
Merged, thanks!
-Olof
^ permalink raw reply
* [PATCH] misc: aspeed-p2a-ctrl: fix mixed declarations
From: Joel Stanley @ 2019-04-29 6:34 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190426165655.218228-1-venture@google.com>
On Fri, 26 Apr 2019 at 16:57, Patrick Venture <venture@google.com> wrote:
>
> Fix up mixed declarations and code in aspeed_p2a_mmap.
>
> Tested: Verified the build had the error and that this patch resolved it
> and there were no other warnings or build errors associated with
> compilation of this driver.
>
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/misc/aspeed-p2a-ctrl.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/aspeed-p2a-ctrl.c b/drivers/misc/aspeed-p2a-ctrl.c
> index 9736821972ef..b60fbeaffcbd 100644
> --- a/drivers/misc/aspeed-p2a-ctrl.c
> +++ b/drivers/misc/aspeed-p2a-ctrl.c
> @@ -100,6 +100,7 @@ static void aspeed_p2a_disable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
> static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
> {
> unsigned long vsize;
> + pgprot_t prot;
> struct aspeed_p2a_user *priv = file->private_data;
> struct aspeed_p2a_ctrl *ctrl = priv->parent;
>
> @@ -107,7 +108,7 @@ static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
> return -EINVAL;
>
> vsize = vma->vm_end - vma->vm_start;
> - pgprot_t prot = vma->vm_page_prot;
> + prot = vma->vm_page_prot;
>
> if (vma->vm_pgoff + vsize > ctrl->mem_base + ctrl->mem_size)
> return -EINVAL;
> --
> 2.21.0.593.g511ec345e18-goog
>
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Joel Stanley @ 2019-04-29 7:48 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190425172549.GA12376@kroah.com>
On Thu, 25 Apr 2019 at 17:25, Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Tue, Apr 23, 2019 at 08:28:14AM -0700, Patrick Venture wrote:
> > On Tue, Apr 23, 2019 at 8:22 AM Patrick Venture <venture@google.com> wrote:
> > >
> > > On Tue, Apr 23, 2019 at 7:26 AM Patrick Venture <venture@google.com> wrote:
> > > >
> > > > Create a SoC folder for the ASPEED parts and place the misc drivers
> > > > currently present into this folder. These drivers are not generic part
> > > > drivers, but rather only apply to the ASPEED SoCs.
> > > >
> > > > Signed-off-by: Patrick Venture <venture@google.com>
> > >
> > > Accidentally lost the Acked-by when re-sending this patchset as I
> > > didn't see it on v1 before re-sending v2 to the larger audience.
> >
> > Since there was a change between v1 and v2, Arnd, I'd appreciate you
> > Ack this version of the patchset since it changes when the soc/aspeed
> > Makefile is followed.
>
> I have no objection for moving stuff out of drivers/misc/ so the SOC
> maintainers are free to take this.
I was on the fence about this. The downside of moving drivers out of
drivers/misc is it allows SoCs to hide little drivers away from
scrutiny, when in fact they could be sharing a common userspace API
with other BMCs. (Keep an eye out for the coming Nuvoton "bios post
code" driver which is very similar to
drivers/misc/aspeed-lpc-snoop.c).
However, in the effort to move away from BMC that are full of shell
scripts that bash on /dev/mem, we are going to see a collection of
small, very SoC specific, drivers and it doesn't make sense to clutter
up drivers/misc.
Acked-by: Joel Stanley <joel@jms.id.au>
The p2a driver has been merged by Greg. We should move that one over
too. Arnd, can you advise Patrick on how to proceed? We could have him
spin a v3 that includes the p2a driver, but it would depend on Greg's
char-misc-next branch.
Cheers,
Joel
^ permalink raw reply
* [PATCH v2 4/4] ARM: dts: aspeed-g5: Add video engine
From: Joel Stanley @ 2019-04-29 7:51 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1556119194-10917-1-git-send-email-eajames@linux.ibm.com>
On Wed, 24 Apr 2019 at 15:20, Eddie James <eajames@linux.ibm.com> wrote:
>
> Add a node to describe the video engine on the AST2500.
>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
Applied to the aspeed SoC tree.
Cheers,
Joel
> ---
> arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 85ed9db..c6d5edc 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -243,6 +243,16 @@
> status = "disabled";
> };
>
> + video: video at 1e700000 {
> + compatible = "aspeed,ast2500-video-engine";
> + reg = <0x1e700000 0x1000>;
> + clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
> + <&syscon ASPEED_CLK_GATE_ECLK>;
> + clock-names = "vclk", "eclk";
> + interrupts = <7>;
> + status = "disabled";
> + };
> +
> sram: sram at 1e720000 {
> compatible = "mmio-sram";
> reg = <0x1e720000 0x9000>; // 36K
> --
> 1.8.3.1
>
^ permalink raw reply
* [PATCH 2/2] ARM: dts: aspeed: quanta-q71: Enable p2a node
From: Joel Stanley @ 2019-04-29 7:53 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190425194903.144569-1-venture@google.com>
On Thu, 25 Apr 2019 at 19:49, Patrick Venture <venture@google.com> wrote:
>
> Enable the aspeed-p2a-ctrl node and configure with memory-region to
> enable mmap access.
>
> Signed-off-by: Patrick Venture <venture@google.com>
Applied to the aspeed SoC tree.
Cheers,
Joel
^ permalink raw reply
* [PATCH 1/2] ARM: dts: aspeed: Add aspeed-p2a-ctrl node
From: Joel Stanley @ 2019-04-29 7:53 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190425194853.140617-1-venture@google.com>
On Thu, 25 Apr 2019 at 19:48, Patrick Venture <venture@google.com> wrote:
>
> Add a node for the aspeed-p2a-ctrl module. This node, when enabled will
> disable the PCI-to-AHB bridge and then allow control of this bridge via
> ioctls, and access via mmap.
>
> Signed-off-by: Patrick Venture <venture@google.com>
Applied to the aspeed SoC tree.
Cheers,
Joel
^ permalink raw reply
* [PATCH v2] soc: add aspeed folder and misc drivers
From: Arnd Bergmann @ 2019-04-29 8:07 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XemgKvM38wDSUJsXXeK51dwmeUoKWn+e3ZNHd9v5VBZHA@mail.gmail.com>
On Mon, Apr 29, 2019 at 9:49 AM Joel Stanley <joel@jms.id.au> wrote:
>
> On Thu, 25 Apr 2019 at 17:25, Greg KH <gregkh@linuxfoundation.org> wrote:
> >
> > On Tue, Apr 23, 2019 at 08:28:14AM -0700, Patrick Venture wrote:
> > > On Tue, Apr 23, 2019 at 8:22 AM Patrick Venture <venture@google.com> wrote:
> > > >
> > > > On Tue, Apr 23, 2019 at 7:26 AM Patrick Venture <venture@google.com> wrote:
> > > > >
> > > > > Create a SoC folder for the ASPEED parts and place the misc drivers
> > > > > currently present into this folder. These drivers are not generic part
> > > > > drivers, but rather only apply to the ASPEED SoCs.
> > > > >
> > > > > Signed-off-by: Patrick Venture <venture@google.com>
> > > >
> > > > Accidentally lost the Acked-by when re-sending this patchset as I
> > > > didn't see it on v1 before re-sending v2 to the larger audience.
> > >
> > > Since there was a change between v1 and v2, Arnd, I'd appreciate you
> > > Ack this version of the patchset since it changes when the soc/aspeed
> > > Makefile is followed.
> >
> > I have no objection for moving stuff out of drivers/misc/ so the SOC
> > maintainers are free to take this.
>
> I was on the fence about this. The downside of moving drivers out of
> drivers/misc is it allows SoCs to hide little drivers away from
> scrutiny, when in fact they could be sharing a common userspace API
> with other BMCs. (Keep an eye out for the coming Nuvoton "bios post
> code" driver which is very similar to
> drivers/misc/aspeed-lpc-snoop.c).
Things like this should usually find a different home: drivers/misc
tends to be for one-of-a-kind stuff with a user interface, not for things
where you have multiple chips doing the same thing.
If you think there are going to be additional cases where you have
more than one bmc in need of a user interface for the same
functionality, we could introduce a drivers/bmc/ subsystem and
have a set of user interfaces backed by a set of chip specific
drivers.
> However, in the effort to move away from BMC that are full of shell
> scripts that bash on /dev/mem, we are going to see a collection of
> small, very SoC specific, drivers and it doesn't make sense to clutter
> up drivers/misc.
>
> Acked-by: Joel Stanley <joel@jms.id.au>
>
> The p2a driver has been merged by Greg. We should move that one over
> too. Arnd, can you advise Patrick on how to proceed? We could have him
> spin a v3 that includes the p2a driver, but it would depend on Greg's
> char-misc-next branch.
I don't think there is a rush here, so let's do that for the following
merge window.
Arnd
^ permalink raw reply
* [PATCH 0/3] update aspeed-bmc-opp-zaius device-tree
From: Joel Stanley @ 2019-04-29 8:27 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190416162150.150154-1-venture@google.com>
On Tue, 16 Apr 2019 at 16:22, Patrick Venture <venture@google.com> wrote:
>
> Hi,
>
> This series contains three updates to the Zaius ASPEED device-tree to
> add voltrage regulators, and update addresses and aliases. The Infineon
> and Intersil drivers are staged on hwmon-next, and the trivial device
> dt-bindings changed are up for review.
Applied to the aspeed SoC tree, thanks Patrick.
Cheers,
Joel
>
> Maxim Sloyko (1):
> ARM: dts: aspeed: zaius: add Infineon and Intersil regulators
>
> Robert Lippert (2):
> ARM: dts: aspeed: zaius: update 12V brick I2C address
> ARM: dts: aspeed: zaius: fixed I2C bus numbers for pcie slots
>
> arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 121 +++++++++++++++++++--
> 1 file changed, 113 insertions(+), 8 deletions(-)
>
> --
> 2.21.0.392.gf8f6787159e-goog
>
^ permalink raw reply
* [PATCH] soc: add aspeed folder and misc drivers
From: Olof Johansson @ 2019-04-29 16:31 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAO=noty2QN6H_x3RMjqOrY9b0xLLz=MBk6Fb6yCdW9+J0a-bSA@mail.gmail.com>
On Tue, Apr 23, 2019 at 08:40:25AM -0700, Patrick Venture wrote:
> On Tue, Apr 23, 2019 at 8:33 AM Arnd Bergmann <arnd@arndb.de> wrote:
> >
> > On Tue, Apr 23, 2019 at 4:24 PM Patrick Venture <venture@google.com> wrote:
> > >
> > > On Tue, Apr 23, 2019 at 1:08 AM Arnd Bergmann <arnd@arndb.de> wrote:
> > > >
> > > > On Mon, Apr 22, 2019 at 7:38 PM Patrick Venture <venture@google.com> wrote:
> > > > >
> > > > > Create a SoC folder for the ASPEED parts and place the misc drivers
> > > > > currently present into this folder. These drivers are not generic part
> > > > > drivers, but rather only apply to the ASPEED SoCs.
> > > > >
> > > > > Signed-off-by: Patrick Venture <venture@google.com>
> > > >
> > > > Looks ok, but please resend to arm at kernel.org or soc at kernel.org
> > > > so we can track the submission and make sure it gets applied if
> > > > you want this to go through the arm-soc tree.
> > >
> > > Thanks, I didn't see those come up in the get_maintainers output.
> > >
> > > I had a longer question related to this patch progression -- if I am
> > > moving the aspeed gpio driver to the soc folder, the soc tree may have
> > > the soc/aspeed folder in their next, but the gpio tree wouldn't
> > > necessarily. I know the branches sync up when things are merged at
> > > the top, but I wasn't sure if there was another mechanism for this?
> >
> > We can generally deal with merge conflicts like this, or you can ask
> > the respective maintainers about it and let us figure something out.
>
> Thanks for explaining that.
>
> >
> > In this particular case, why would you move the gpio driver into
> > the soc folder? If there is a proper subsystem for a driver, it should
> > not be in drivers/misc or drivers/soc.
>
> Ok, that makes sense. I was trying to get a sense of what belonged in
> soc versus the subsystem folders. My thinking from the limited
> reading was the purpose of a SoC folder was to contain the drivers
> that were only associated with a system-on-a-chip and not a part you
> could buy and place on any board. A tmp421 sensor is just a generic
> part, versus the pwm controller, which is only for the specific SoCs.
>
> That said, there are quite a few misc drivers associated with the
> Aspeed parts -- and there are two under review now, so there's a
> strong motivation to move those at least into the soc/aspeed folder.
> Thanks for these clarifying remarks.
drivers/soc is more about platform-level glue and SoC configuration, etc.
Specific IP blocks and drivers normally don't go into there, unless it's
a shared resource that a lot of drivers need access to.
So, for most of the small drivers around the SoC, other directories than
drivers/soc are still the best answer.
-Olof
^ permalink raw reply
* [PATCH] soc: add aspeed folder and misc drivers
From: Olof Johansson @ 2019-04-29 16:32 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CAK8P3a0k_8+R9FeyZsL6Egvi1Z-G0VrvR0TWXzGHryqxTr6thg@mail.gmail.com>
On Tue, Apr 23, 2019 at 10:08:11AM +0200, Arnd Bergmann wrote:
> On Mon, Apr 22, 2019 at 7:38 PM Patrick Venture <venture@google.com> wrote:
> >
> > Create a SoC folder for the ASPEED parts and place the misc drivers
> > currently present into this folder. These drivers are not generic part
> > drivers, but rather only apply to the ASPEED SoCs.
> >
> > Signed-off-by: Patrick Venture <venture@google.com>
>
> Looks ok, but please resend to arm at kernel.org or soc at kernel.org
> so we can track the submission and make sure it gets applied if
> you want this to go through the arm-soc tree.
>
> If Greg wants to pick it up, that's fine too.
>
> Either way,
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
Applied to the SoC tree now.
-Olof
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