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From: Torin Cooper-Bennun <torin@maxiluxsystems.com>
To: linux-can@vger.kernel.org
Cc: Marc Kleine-Budde <mkl@pengutronix.de>,
	Pankaj Sharma <pankj.sharma@samsung.com>,
	Torin Cooper-Bennun <torin@maxiluxsystems.com>
Subject: [PATCH 3/4] can: m_can: make TXESC, RXESC config more explicit
Date: Tue,  4 May 2021 12:20:34 +0100	[thread overview]
Message-ID: <20210504112035.336424-4-torin@maxiluxsystems.com> (raw)
In-Reply-To: <20210504112035.336424-1-torin@maxiluxsystems.com>

Introduce masks for the three RXESC fields (RBDS, F1DS, F0DS) and the
one TXESC field (TBDS). Update m_can_chip_config() to explicitly set all
four fields to the 64-byte option (0x7) (and these defs are renamed to
be more concise).

This is an improvement in maintainability, and also makes it easier to
implement more flexible configuration of the M_CAN buffers in the
future.
---
 drivers/net/can/m_can/m_can.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index c85f064de4a0..e3b15b74fdc9 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -235,8 +235,10 @@ enum m_can_reg {
 #define RXFS_FFL_MASK	GENMASK(6, 0)
 
 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
-#define M_CAN_RXESC_8BYTES	0x0
-#define M_CAN_RXESC_64BYTES	0x777
+#define RXESC_RBDS_MASK		GENMASK(10, 8)
+#define RXESC_F1DS_MASK		GENMASK(6, 4)
+#define RXESC_F0DS_MASK		GENMASK(2, 0)
+#define RXESC_64B		0x7
 
 /* Tx Buffer Configuration (TXBC) */
 #define TXBC_TFQS_MASK		GENMASK(29, 24)
@@ -249,8 +251,8 @@ enum m_can_reg {
 #define TXFQS_TFFL_MASK		GENMASK(5, 0)
 
 /* Tx Buffer Element Size Configuration(TXESC) */
-#define TXESC_TBDS_8BYTES	0x0
-#define TXESC_TBDS_64BYTES	0x7
+#define TXESC_TBDS_MASK		GENMASK(2, 0)
+#define TXESC_TBDS_64B		0x7
 
 /* Tx Event FIFO Configuration (TXEFC) */
 #define TXEFC_EFS_MASK		GENMASK(21, 16)
@@ -1191,7 +1193,10 @@ static void m_can_chip_config(struct net_device *dev)
 	m_can_config_endisable(cdev, true);
 
 	/* RX Buffer/FIFO Element Size 64 bytes data field */
-	m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
+	m_can_write(cdev, M_CAN_RXESC,
+		    FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
+		    FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
+		    FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
 
 	/* Accept Non-matching Frames Into FIFO 0 */
 	m_can_write(cdev, M_CAN_GFC, 0x0);
@@ -1209,7 +1214,8 @@ static void m_can_chip_config(struct net_device *dev)
 	}
 
 	/* support 64 bytes payload */
-	m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES);
+	m_can_write(cdev, M_CAN_TXESC,
+		    FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
 
 	/* TX Event FIFO */
 	if (cdev->version == 30) {
-- 
2.30.2


  parent reply	other threads:[~2021-05-04 11:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04 11:20 PATCH [0/4] can: m_can: various regmask-related cleanup Torin Cooper-Bennun
2021-05-04 11:20 ` [PATCH 1/4] can: m_can: use bits.h macros for all regmasks Torin Cooper-Bennun
2021-05-04 11:20 ` [PATCH 2/4] can: m_can: clean up CCCR reg defs, order by revs Torin Cooper-Bennun
2021-05-04 11:20 ` Torin Cooper-Bennun [this message]
2021-05-04 11:20 ` [PATCH 4/4] can: m_can: fix whitespace in a few comments Torin Cooper-Bennun
2021-05-04 11:27 ` PATCH [0/4] can: m_can: various regmask-related cleanup Marc Kleine-Budde
2021-05-04 11:39   ` Torin Cooper-Bennun
  -- strict thread matches above, loose matches on Subject: below --
2021-05-04 11:48 [REPOST PATCH 0/4] " Torin Cooper-Bennun
2021-05-04 11:49 ` [PATCH 3/4] can: m_can: make TXESC, RXESC config more explicit Torin Cooper-Bennun

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