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From: Torin Cooper-Bennun <torin@maxiluxsystems.com>
To: linux-can@vger.kernel.org
Cc: Marc Kleine-Budde <mkl@pengutronix.de>,
	Pankaj Sharma <pankj.sharma@samsung.com>,
	Torin Cooper-Bennun <torin@maxiluxsystems.com>
Subject: [PATCH 4/4] can: m_can: fix whitespace in a few comments
Date: Tue,  4 May 2021 12:20:35 +0100	[thread overview]
Message-ID: <20210504112035.336424-5-torin@maxiluxsystems.com> (raw)
In-Reply-To: <20210504112035.336424-1-torin@maxiluxsystems.com>

Fixes whitespace in comments titling sections of register masks.
---
 drivers/net/can/m_can/m_can.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index e3b15b74fdc9..9d3c2116fd53 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -101,7 +101,7 @@ enum m_can_reg {
 /* Test Register (TEST) */
 #define TEST_LBCK		BIT(4)
 
-/* CC Control Register(CCCR) */
+/* CC Control Register (CCCR) */
 #define CCCR_TXP		BIT(14)
 #define CCCR_TEST		BIT(7)
 #define CCCR_DAR		BIT(6)
@@ -147,18 +147,18 @@ enum m_can_reg {
 /* Timestamp Counter Value Register (TSCV) */
 #define TSCV_TSC_MASK		GENMASK(15, 0)
 
-/* Error Counter Register(ECR) */
+/* Error Counter Register (ECR) */
 #define ECR_RP			BIT(15)
 #define ECR_REC_MASK		GENMASK(14, 8)
 #define ECR_TEC_MASK		GENMASK(7, 0)
 
-/* Protocol Status Register(PSR) */
+/* Protocol Status Register (PSR) */
 #define PSR_BO		BIT(7)
 #define PSR_EW		BIT(6)
 #define PSR_EP		BIT(5)
 #define PSR_LEC_MASK	GENMASK(2, 0)
 
-/* Interrupt Register(IR) */
+/* Interrupt Register (IR) */
 #define IR_ALL_INT	0xffffffff
 
 /* Renamed bits for versions > 3.1.x */
@@ -250,7 +250,7 @@ enum m_can_reg {
 #define TXFQS_TFGI_MASK		GENMASK(12, 8)
 #define TXFQS_TFFL_MASK		GENMASK(5, 0)
 
-/* Tx Buffer Element Size Configuration(TXESC) */
+/* Tx Buffer Element Size Configuration (TXESC) */
 #define TXESC_TBDS_MASK		GENMASK(2, 0)
 #define TXESC_TBDS_64B		0x7
 
-- 
2.30.2


  parent reply	other threads:[~2021-05-04 11:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04 11:20 PATCH [0/4] can: m_can: various regmask-related cleanup Torin Cooper-Bennun
2021-05-04 11:20 ` [PATCH 1/4] can: m_can: use bits.h macros for all regmasks Torin Cooper-Bennun
2021-05-04 11:20 ` [PATCH 2/4] can: m_can: clean up CCCR reg defs, order by revs Torin Cooper-Bennun
2021-05-04 11:20 ` [PATCH 3/4] can: m_can: make TXESC, RXESC config more explicit Torin Cooper-Bennun
2021-05-04 11:20 ` Torin Cooper-Bennun [this message]
2021-05-04 11:27 ` PATCH [0/4] can: m_can: various regmask-related cleanup Marc Kleine-Budde
2021-05-04 11:39   ` Torin Cooper-Bennun
  -- strict thread matches above, loose matches on Subject: below --
2021-05-04 11:48 [REPOST PATCH 0/4] " Torin Cooper-Bennun
2021-05-04 11:49 ` [PATCH 4/4] can: m_can: fix whitespace in a few comments Torin Cooper-Bennun

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