* RE: [PATCH] clk: samsung: correct clock summary for hsi1 block
2025-04-28 11:50 ` [PATCH] clk: samsung: correct clock summary for hsi1 block Pritam Manohar Sutar
@ 2025-04-30 8:03 ` Alim Akhtar
0 siblings, 0 replies; 2+ messages in thread
From: Alim Akhtar @ 2025-04-30 8:03 UTC (permalink / raw)
To: 'Pritam Manohar Sutar', krzk, s.nawrocki, cw00.choi,
mturquette, sboyd, sunyeal.hong
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
rosa.pila, dev.tailor, faraz.ata, 'stable'
Hi Pritam
> -----Original Message-----
> From: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> Sent: Monday, April 28, 2025 5:21 PM
> To: krzk@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com;
> alim.akhtar@samsung.com; mturquette@baylibre.com; sboyd@kernel.org;
> sunyeal.hong@samsung.com
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-
> arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; Pritam Manohar Sutar
> <pritam.sutar@samsung.com>; stable <stable@kernel.org>
> Subject: [PATCH] clk: samsung: correct clock summary for hsi1 block
>
> When debugfs is mounted to check clk_summary, 'mout_hsi1_usbdrd_user'
> shows 400Mhz instead of 40Mhz. Snippet of the clock summary is given as
> below
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
>
> Hence corrected the clk-tree for the cmu_hsi1 & the corrected clock
> summary is as mentioned below.
>
May be just " correct the clk_tree by adding correct clock patent for
mout_hsi1_usbdrd_user "
see: https://www.kernel.org/doc/html/latest/process/submitting-patches.html
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ...
>
> Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto
> v920 SoC")
> Cc: stable <stable@kernel.org>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov920.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov920.c
> b/drivers/clk/samsung/clk-exynosautov920.c
> index dc8d4240f6de..b0561faecfeb 100644
> --- a/drivers/clk/samsung/clk-exynosautov920.c
> +++ b/drivers/clk/samsung/clk-exynosautov920.c
> @@ -1393,7 +1393,7 @@ static const unsigned long hsi1_clk_regs[]
> __initconst = {
> /* List of parent clocks for Muxes in CMU_HSI1 */
> PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk",
> "dout_clkcmu_hsi1_mmc_card"};
> PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
> -PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk",
> "mout_clkcmu_hsi1_usbdrd" };
> +PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk",
> "dout_clkcmu_hsi1_usbdrd"
> +};
> PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2",
> "mout_hsi1_usbdrd_user" };
>
> static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
> --
> 2.34.1
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