* [PATCH v3 1/8] clk: qcom: rpmh: group clock definitions together
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 2/8] clk: qcom: rpmh: reuse common duplicate clocks Dmitry Baryshkov
` (8 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
In preparations to the further changes, group all RPMH clock definitions
to ease review. Group the clocks by their type to make similar/duplicate
clocks stand out.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 55 ++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 29 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 1da45a6e2f29..f13c9bd610d0 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -342,19 +342,45 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
};
/* Resource name must match resource id present in cmd-db */
+DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1);
DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
+DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
+DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
+
+DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
+DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
+
+DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
+
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4);
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
+
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
+
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1);
+DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
+DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
+
+DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
+
DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
+DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0");
+DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
+DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
+DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
@@ -398,11 +424,6 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
.num_clks = ARRAY_SIZE(sdm670_rpmh_clocks),
};
-DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
-DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
-DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
-DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0");
-
static struct clk_hw *sdx55_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
@@ -478,8 +499,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
.num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks),
};
-DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
-
static struct clk_hw *sm8250_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
@@ -500,12 +519,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
};
-DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
-DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
-DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
-
static struct clk_hw *sm8350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
@@ -533,8 +546,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
};
-DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
-
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
@@ -550,12 +561,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
.num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks),
};
-/* Resource name must match resource id present in cmd-db */
-DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
-
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
-
static struct clk_hw *sm8450_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
@@ -600,10 +605,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
.num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
};
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
-DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
-
static struct clk_hw *sm6350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
@@ -620,8 +621,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
.num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
};
-DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
-
static struct clk_hw *sdx65_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
@@ -644,8 +643,6 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
.num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
};
-DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1);
-
static struct clk_hw *qdu1000_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw,
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 2/8] clk: qcom: rpmh: reuse common duplicate clocks
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 1/8] clk: qcom: rpmh: group clock definitions together Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 3/8] clk: qcom: rpmh: drop all _ao names Dmitry Baryshkov
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
After the grouping it is obvious that some of the clock definitions are
pure duplicates. Rename them to use a single common name for the clock.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index f13c9bd610d0..c4852bbd00bf 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -350,9 +350,7 @@ DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
-DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
-DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
@@ -362,7 +360,6 @@ DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
-DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
@@ -370,14 +367,11 @@ DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1);
-DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
-DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
-DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0");
DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
@@ -427,12 +421,12 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
static struct clk_hw *sdx55_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
- [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw,
+ [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
+ [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
+ [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
+ [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
[RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
- [RPMH_IPA_CLK] = &sdx55_ipa.hw,
+ [RPMH_IPA_CLK] = &sdm845_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
@@ -549,8 +543,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
- [RPMH_LN_BB_CLK3] = &sc8280xp_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sc8280xp_ln_bb_clk3_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_PKA_CLK] = &sm8350_pka.hw,
[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
@@ -624,8 +618,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
static struct clk_hw *sdx65_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
- [RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw,
- [RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw,
+ [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
+ [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 3/8] clk: qcom: rpmh: drop all _ao names
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 1/8] clk: qcom: rpmh: group clock definitions together Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 2/8] clk: qcom: rpmh: reuse common duplicate clocks Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 4/8] clk: qcom: rpmh: remove platform names from BCM clocks Dmitry Baryshkov
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder, Abel Vesa
In preparation for the further cleanup, remove the active only names,
they can be easily generated from the standard ones.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 62 ++++++++++++++++++-------------------
1 file changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index c4852bbd00bf..00c0c8f851bd 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -70,15 +70,15 @@ struct clk_rpmh_desc {
static DEFINE_MUTEX(rpmh_clk_lock);
-#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
+#define __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
_res_en_offset, _res_on, _div) \
- static struct clk_rpmh _platform##_##_name_active; \
+ static struct clk_rpmh _platform##_##_name##_ao; \
static struct clk_rpmh _platform##_##_name = { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
- .peer = &_platform##_##_name_active, \
+ .peer = &_platform##_##_name##_ao, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE) | \
BIT(RPMH_SLEEP_STATE)), \
@@ -92,7 +92,7 @@ static DEFINE_MUTEX(rpmh_clk_lock);
.num_parents = 1, \
}, \
}; \
- static struct clk_rpmh _platform##_##_name_active = { \
+ static struct clk_rpmh _platform##_##_name##_ao= { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
@@ -102,7 +102,7 @@ static DEFINE_MUTEX(rpmh_clk_lock);
BIT(RPMH_ACTIVE_ONLY_STATE)), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_ops, \
- .name = #_name_active, \
+ .name = #_name "_ao", \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
@@ -111,14 +111,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
}, \
}
-#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
- _res_on, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
+#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
+ __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
-#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
- _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
+#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
+ __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
@@ -342,33 +340,33 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
};
/* Resource name must match resource id present in cmd-db */
-DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1);
-DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
-DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
-DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
+DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, "xo.lvl", 0x3, 1);
+DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2);
+DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4);
+DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4);
-DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
-DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
-DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
+DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2);
+DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2);
+DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, "lnbclka3", 2);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, "lnbclka1", 4);
+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, "lnbclka2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, "lnbclkg2", 4);
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, "lnbclkg3", 4);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, "rfclka1", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, "rfclka2", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, "rfclka3", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, "rfclka4", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, "rfclka5", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, "rfclkd1", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, "rfclkd2", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, "rfclkd3", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
+DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 4/8] clk: qcom: rpmh: remove platform names from BCM clocks
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (2 preceding siblings ...)
2022-12-02 18:58 ` [PATCH v3 3/8] clk: qcom: rpmh: drop all _ao names Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 18:58 ` [PATCH v3 5/8] clk: qcom: rpmh: support separate symbol name for the RPMH clocks Dmitry Baryshkov
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
There are no platform-specific parts in the BCM clocks, drop the
platform name from the clock definitions, replacing it with clk_rpmh to
have the common prefix.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 52 ++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 00c0c8f851bd..2ab406c1dab5 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -119,8 +119,8 @@ static DEFINE_MUTEX(rpmh_clk_lock);
__DEFINE_CLK_RPMH(_platform, _name, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
-#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
- static struct clk_rpmh _platform##_##_name = { \
+#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
+ static struct clk_rpmh clk_rpmh_##_name = { \
.res_name = _res_name, \
.valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
.div = 1, \
@@ -368,11 +368,11 @@ DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1);
DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2);
-DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
-DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
-DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
-DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
-DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
+DEFINE_CLK_RPMH_BCM(ce, "CE0");
+DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
+DEFINE_CLK_RPMH_BCM(ipa, "IP0");
+DEFINE_CLK_RPMH_BCM(pka, "PKA0");
+DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
@@ -387,8 +387,8 @@ static struct clk_hw *sdm845_rpmh_clocks[] = {
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
- [RPMH_CE_CLK] = &sdm845_ce.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+ [RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
@@ -407,8 +407,8 @@ static struct clk_hw *sdm670_rpmh_clocks[] = {
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
- [RPMH_CE_CLK] = &sdm845_ce.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+ [RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
@@ -423,8 +423,8 @@ static struct clk_hw *sdx55_rpmh_clocks[] = {
[RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
- [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
+ [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
@@ -463,7 +463,7 @@ static struct clk_hw *sc7180_rpmh_clocks[] = {
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
@@ -528,9 +528,9 @@ static struct clk_hw *sm8350_rpmh_clocks[] = {
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
[RPMH_RF_CLK5] = &sm8350_rf_clk5.hw,
[RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
- [RPMH_PKA_CLK] = &sm8350_pka.hw,
- [RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+ [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
+ [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
@@ -543,9 +543,9 @@ static struct clk_hw *sc8280xp_rpmh_clocks[] = {
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
- [RPMH_PKA_CLK] = &sm8350_pka.hw,
- [RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+ [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
+ [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
@@ -568,7 +568,7 @@ static struct clk_hw *sm8450_rpmh_clocks[] = {
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
@@ -587,9 +587,9 @@ static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
- [RPMH_PKA_CLK] = &sm8350_pka.hw,
- [RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+ [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
+ [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
@@ -626,8 +626,8 @@ static struct clk_hw *sdx65_rpmh_clocks[] = {
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
- [RPMH_IPA_CLK] = &sdm845_ipa.hw,
- [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+ [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 5/8] clk: qcom: rpmh: support separate symbol name for the RPMH clocks
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (3 preceding siblings ...)
2022-12-02 18:58 ` [PATCH v3 4/8] clk: qcom: rpmh: remove platform names from BCM clocks Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 19:29 ` Alex Elder
2022-12-02 18:58 ` [PATCH v3 6/8] clk: qcom: rpmh: rename ARC clock data Dmitry Baryshkov
` (4 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
Both ARC and VRM clocks have minor differences between platforms.
However using SoC names directly results in duplication, confusion and
ocassional errors. Next patches are going to drop the SoC names and
encode these differences into the clock names.
To keep the system clock names (visible to userspace) intact, add
separate symbol names that are used in the code.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 2ab406c1dab5..34099bb6b899 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -70,15 +70,15 @@ struct clk_rpmh_desc {
static DEFINE_MUTEX(rpmh_clk_lock);
-#define __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
+#define __DEFINE_CLK_RPMH(_platform, _name, _clk_name, _res_name, \
_res_en_offset, _res_on, _div) \
- static struct clk_rpmh _platform##_##_name##_ao; \
- static struct clk_rpmh _platform##_##_name = { \
+ static struct clk_rpmh _platform##_##_clk_name##_ao; \
+ static struct clk_rpmh _platform##_##_clk_name = { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
- .peer = &_platform##_##_name##_ao, \
+ .peer = &_platform##_##_clk_name##_ao, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE) | \
BIT(RPMH_SLEEP_STATE)), \
@@ -92,12 +92,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
.num_parents = 1, \
}, \
}; \
- static struct clk_rpmh _platform##_##_name##_ao= { \
+ static struct clk_rpmh _platform##_##_clk_name##_ao= { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
- .peer = &_platform##_##_name, \
+ .peer = &_platform##_##_clk_name, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE)), \
.hw.init = &(struct clk_init_data){ \
@@ -112,11 +112,11 @@ static DEFINE_MUTEX(rpmh_clk_lock);
}
#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
+ __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
+ __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 5/8] clk: qcom: rpmh: support separate symbol name for the RPMH clocks
2022-12-02 18:58 ` [PATCH v3 5/8] clk: qcom: rpmh: support separate symbol name for the RPMH clocks Dmitry Baryshkov
@ 2022-12-02 19:29 ` Alex Elder
0 siblings, 0 replies; 15+ messages in thread
From: Alex Elder @ 2022-12-02 19:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk
On 12/2/22 12:58 PM, Dmitry Baryshkov wrote:
> Both ARC and VRM clocks have minor differences between platforms.
> However using SoC names directly results in duplication, confusion and
> ocassional errors. Next patches are going to drop the SoC names and
s/ocassional/occasional/
> encode these differences into the clock names.
> To keep the system clock names (visible to userspace) intact, add
> separate symbol names that are used in the code.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Looks good. Thank you for rearranging this, it's easier to follow.
Reviewed-by: Alex Elder <elder@linaro.org>
> ---
> drivers/clk/qcom/clk-rpmh.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 2ab406c1dab5..34099bb6b899 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -70,15 +70,15 @@ struct clk_rpmh_desc {
>
> static DEFINE_MUTEX(rpmh_clk_lock);
>
> -#define __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
> +#define __DEFINE_CLK_RPMH(_platform, _name, _clk_name, _res_name, \
> _res_en_offset, _res_on, _div) \
> - static struct clk_rpmh _platform##_##_name##_ao; \
> - static struct clk_rpmh _platform##_##_name = { \
> + static struct clk_rpmh _platform##_##_clk_name##_ao; \
> + static struct clk_rpmh _platform##_##_clk_name = { \
> .res_name = _res_name, \
> .res_addr = _res_en_offset, \
> .res_on_val = _res_on, \
> .div = _div, \
> - .peer = &_platform##_##_name##_ao, \
> + .peer = &_platform##_##_clk_name##_ao, \
> .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
> BIT(RPMH_ACTIVE_ONLY_STATE) | \
> BIT(RPMH_SLEEP_STATE)), \
> @@ -92,12 +92,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> .num_parents = 1, \
> }, \
> }; \
> - static struct clk_rpmh _platform##_##_name##_ao= { \
> + static struct clk_rpmh _platform##_##_clk_name##_ao= { \
> .res_name = _res_name, \
> .res_addr = _res_en_offset, \
> .res_on_val = _res_on, \
> .div = _div, \
> - .peer = &_platform##_##_name, \
> + .peer = &_platform##_##_clk_name, \
> .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
> BIT(RPMH_ACTIVE_ONLY_STATE)), \
> .hw.init = &(struct clk_init_data){ \
> @@ -112,11 +112,11 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> }
>
> #define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
> - __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
> + __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
> CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
>
> #define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
> - __DEFINE_CLK_RPMH(_platform, _name, _res_name, \
> + __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
> CLK_RPMH_VRM_EN_OFFSET, 1, _div)
>
> #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 6/8] clk: qcom: rpmh: rename ARC clock data
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (4 preceding siblings ...)
2022-12-02 18:58 ` [PATCH v3 5/8] clk: qcom: rpmh: support separate symbol name for the RPMH clocks Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 19:29 ` Alex Elder
2022-12-02 18:58 ` [PATCH v3 7/8] clk: qcom: rpmh: rename VRM " Dmitry Baryshkov
` (3 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
RPMH ARC clocks are frequently shared between several platfoms. It makes
little sense to encode the SoC name into the clock name, if the same
clock is used for other SoCs.
Rework the ARC clock defintions to remove the SoC name. Keep the
userspace-visible clock name, but encode the divider into the variable
name. This also makes it obvious which divider is used by the platform,
making the code less error-prone.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 62 ++++++++++++++++++-------------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 34099bb6b899..439cace44bd1 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -112,7 +112,7 @@ static DEFINE_MUTEX(rpmh_clk_lock);
}
#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
+ __DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
@@ -375,8 +375,8 @@ DEFINE_CLK_RPMH_BCM(pka, "PKA0");
DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
@@ -397,8 +397,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
};
static struct clk_hw *sdm670_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
@@ -417,8 +417,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
};
static struct clk_hw *sdx55_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
@@ -433,8 +433,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
};
static struct clk_hw *sm8150_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
@@ -453,8 +453,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
};
static struct clk_hw *sc7180_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
@@ -472,8 +472,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
};
static struct clk_hw *sc8180x_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
@@ -492,8 +492,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
};
static struct clk_hw *sm8250_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
@@ -512,8 +512,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
};
static struct clk_hw *sm8350_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_DIV_CLK1] = &sm8350_div_clk1.hw,
[RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
@@ -539,8 +539,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
};
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
@@ -554,8 +554,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
};
static struct clk_hw *sm8450_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
[RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
@@ -577,8 +577,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
@@ -598,14 +598,14 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
};
static struct clk_hw *sm6350_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw,
- [RPMH_QLINK_CLK] = &sm6350_qlink.hw,
- [RPMH_QLINK_CLK_A] = &sm6350_qlink_ao.hw,
+ [RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw,
+ [RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
@@ -614,8 +614,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
};
static struct clk_hw *sdx65_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
@@ -636,8 +636,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
};
static struct clk_hw *qdu1000_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw,
- [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw,
+ [RPMH_CXO_CLK] = &qdu1000_bi_tcxo_div1.hw,
+ [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_div1_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 6/8] clk: qcom: rpmh: rename ARC clock data
2022-12-02 18:58 ` [PATCH v3 6/8] clk: qcom: rpmh: rename ARC clock data Dmitry Baryshkov
@ 2022-12-02 19:29 ` Alex Elder
0 siblings, 0 replies; 15+ messages in thread
From: Alex Elder @ 2022-12-02 19:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk
On 12/2/22 12:58 PM, Dmitry Baryshkov wrote:
> RPMH ARC clocks are frequently shared between several platfoms. It makes
s/platfoms/platforms/
> little sense to encode the SoC name into the clock name, if the same
> clock is used for other SoCs.
>
> Rework the ARC clock defintions to remove the SoC name. Keep the
s/defintions/definitions/
> userspace-visible clock name, but encode the divider into the variable
> name. This also makes it obvious which divider is used by the platform,
> making the code less error-prone.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Looks good.
Reviewed-by: Alex Elder <elder@linaro.org>
> ---
> drivers/clk/qcom/clk-rpmh.c | 62 ++++++++++++++++++-------------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 34099bb6b899..439cace44bd1 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -112,7 +112,7 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> }
>
> #define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
> - __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
> + __DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \
> CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
>
> #define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
> @@ -375,8 +375,8 @@ DEFINE_CLK_RPMH_BCM(pka, "PKA0");
> DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
>
> static struct clk_hw *sdm845_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> @@ -397,8 +397,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
> };
>
> static struct clk_hw *sdm670_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> @@ -417,8 +417,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
> };
>
> static struct clk_hw *sdx55_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
> [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
> [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
> @@ -433,8 +433,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
> };
>
> static struct clk_hw *sm8150_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> @@ -453,8 +453,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
> };
>
> static struct clk_hw *sc7180_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> @@ -472,8 +472,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
> };
>
> static struct clk_hw *sc8180x_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> @@ -492,8 +492,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
> };
>
> static struct clk_hw *sm8250_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
> [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> @@ -512,8 +512,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> };
>
> static struct clk_hw *sm8350_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw,
> [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw,
> [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
> @@ -539,8 +539,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
> };
>
> static struct clk_hw *sc8280xp_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> @@ -554,8 +554,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
> };
>
> static struct clk_hw *sm8450_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
> [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
> [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
> @@ -577,8 +577,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
> };
>
> static struct clk_hw *sc7280_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> @@ -598,14 +598,14 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
> };
>
> static struct clk_hw *sm6350_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw,
> [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw,
> [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw,
> [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw,
> - [RPMH_QLINK_CLK] = &sm6350_qlink.hw,
> - [RPMH_QLINK_CLK_A] = &sm6350_qlink_ao.hw,
> + [RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw,
> + [RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
> @@ -614,8 +614,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
> };
>
> static struct clk_hw *sdx65_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
> [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
> [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> @@ -636,8 +636,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
> };
>
> static struct clk_hw *qdu1000_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw,
> - [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw,
> + [RPMH_CXO_CLK] = &qdu1000_bi_tcxo_div1.hw,
> + [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_div1_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 7/8] clk: qcom: rpmh: rename VRM clock data
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (5 preceding siblings ...)
2022-12-02 18:58 ` [PATCH v3 6/8] clk: qcom: rpmh: rename ARC clock data Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 19:29 ` Alex Elder
2022-12-02 18:58 ` [PATCH v3 8/8] clk: qcom: rpmh: remove usage of platform name Dmitry Baryshkov
` (2 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
RPMH VRM clocks are frequently shared between several platfoms. It makes
little sense to encode the SoC name into the clock name, if the same
clock is used for other SoCs.
Rework the VRM clock defintions to add resource-specific suffix. Keep the
userspace-visible clock name, but encode the part of cmd resource and
the divider into the variable name. This also make it obvious which
variant is used, making the code less error-prone.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 258 ++++++++++++++++++------------------
1 file changed, 129 insertions(+), 129 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 439cace44bd1..b543939de1c8 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -115,8 +115,8 @@ static DEFINE_MUTEX(rpmh_clk_lock);
__DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
-#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
+#define DEFINE_CLK_RPMH_VRM(_platform, _name, _suffix, _res_name, _div) \
+ __DEFINE_CLK_RPMH(_platform, _name, _name##_suffix, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
@@ -345,28 +345,28 @@ DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4);
-DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2);
-DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2);
-DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, "lnbclka3", 2);
+DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, _a2, "lnbclka1", 2);
+DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, _a2, "lnbclka2", 2);
+DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, _a2, "lnbclka3", 2);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, "lnbclka1", 4);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, "lnbclka2", 4);
+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, _a4, "lnbclka1", 4);
+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, _a4, "lnbclka2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, "lnbclkg2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, "lnbclkg3", 4);
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, _g4, "lnbclkg2", 4);
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, _g4, "lnbclkg3", 4);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, "rfclka1", 1);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, "rfclka2", 1);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, "rfclka3", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, "rfclka4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, "rfclka5", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, _a, "rfclka1", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, _a, "rfclka2", 1);
+DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, _a, "rfclka3", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, _a, "rfclka4", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, _a, "rfclka5", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, "rfclkd1", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, "rfclkd2", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, "rfclkd3", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, _d, "rfclkd1", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, _d, "rfclkd2", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, _d, "rfclkd3", 1);
+DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, _d, "rfclkd4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2);
+DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
@@ -377,16 +377,16 @@ DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
@@ -399,14 +399,14 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
static struct clk_hw *sdm670_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
@@ -419,10 +419,10 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
static struct clk_hw *sdx55_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
+ [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
+ [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
+ [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
+ [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
@@ -435,16 +435,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
static struct clk_hw *sm8150_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
@@ -455,14 +455,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
static struct clk_hw *sc7180_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
@@ -474,16 +474,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
static struct clk_hw *sc8180x_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
- [RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
+ [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
+ [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
+ [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
+ [RPMH_RF_CLK3] = &sc8180x_rf_clk3_d.hw,
+ [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_d_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
@@ -494,16 +494,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
static struct clk_hw *sm8250_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
+ [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
+ [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
@@ -514,20 +514,20 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
static struct clk_hw *sm8350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw,
- [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
- [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw,
- [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw,
+ [RPMH_DIV_CLK1] = &sm8350_div_clk1_div2.hw,
+ [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_div2_ao.hw,
+ [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
+ [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
+ [RPMH_RF_CLK5] = &sm8350_rf_clk5_a.hw,
+ [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
@@ -541,8 +541,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
@@ -556,18 +556,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
static struct clk_hw *sm8450_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
- [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
+ [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
+ [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2_a4.hw,
+ [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_a4_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
@@ -579,14 +579,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
@@ -600,10 +600,10 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
static struct clk_hw *sm6350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw,
- [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw,
- [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2_g4.hw,
+ [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_g4_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3_g4.hw,
+ [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_g4_ao.hw,
[RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw,
[RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw,
};
@@ -616,16 +616,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
static struct clk_hw *sdx65_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
+ [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
+ [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
};
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 7/8] clk: qcom: rpmh: rename VRM clock data
2022-12-02 18:58 ` [PATCH v3 7/8] clk: qcom: rpmh: rename VRM " Dmitry Baryshkov
@ 2022-12-02 19:29 ` Alex Elder
0 siblings, 0 replies; 15+ messages in thread
From: Alex Elder @ 2022-12-02 19:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk
On 12/2/22 12:58 PM, Dmitry Baryshkov wrote:
> RPMH VRM clocks are frequently shared between several platfoms. It makes
s/platfoms/platforms/
> little sense to encode the SoC name into the clock name, if the same
> clock is used for other SoCs.
>
> Rework the VRM clock defintions to add resource-specific suffix. Keep the
s/defintions/definitions/
> userspace-visible clock name, but encode the part of cmd resource and
> the divider into the variable name. This also make it obvious which
> variant is used, making the code less error-prone.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Looks good.
Reviewed-by: Alex Elder <elder@linaro.org>
> ---
> drivers/clk/qcom/clk-rpmh.c | 258 ++++++++++++++++++------------------
> 1 file changed, 129 insertions(+), 129 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 439cace44bd1..b543939de1c8 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -115,8 +115,8 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> __DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \
> CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
>
> -#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \
> - __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \
> +#define DEFINE_CLK_RPMH_VRM(_platform, _name, _suffix, _res_name, _div) \
> + __DEFINE_CLK_RPMH(_platform, _name, _name##_suffix, _res_name, \
> CLK_RPMH_VRM_EN_OFFSET, 1, _div)
>
> #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
> @@ -345,28 +345,28 @@ DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2);
> DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4);
> DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4);
>
> -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2);
> -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2);
> -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, "lnbclka3", 2);
> +DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, _a2, "lnbclka1", 2);
> +DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, _a2, "lnbclka2", 2);
> +DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, _a2, "lnbclka3", 2);
>
> -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, "lnbclka1", 4);
> -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, "lnbclka2", 4);
> +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, _a4, "lnbclka1", 4);
> +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, _a4, "lnbclka2", 4);
>
> -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, "lnbclkg2", 4);
> -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, "lnbclkg3", 4);
> +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, _g4, "lnbclkg2", 4);
> +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, _g4, "lnbclkg3", 4);
>
> -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, "rfclka1", 1);
> -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, "rfclka2", 1);
> -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, "rfclka3", 1);
> -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, "rfclka4", 1);
> -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, "rfclka5", 1);
> +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, _a, "rfclka1", 1);
> +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, _a, "rfclka2", 1);
> +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, _a, "rfclka3", 1);
> +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, _a, "rfclka4", 1);
> +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, _a, "rfclka5", 1);
>
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, "rfclkd1", 1);
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, "rfclkd2", 1);
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, "rfclkd3", 1);
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1);
> +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, _d, "rfclkd1", 1);
> +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, _d, "rfclkd2", 1);
> +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, _d, "rfclkd3", 1);
> +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, _d, "rfclkd4", 1);
>
> -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2);
> +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, _div2, "divclka1", 2);
>
> DEFINE_CLK_RPMH_BCM(ce, "CE0");
> DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
> @@ -377,16 +377,16 @@ DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
> static struct clk_hw *sdm845_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_CE_CLK] = &clk_rpmh_ce.hw,
> };
> @@ -399,14 +399,14 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
> static struct clk_hw *sdm670_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_CE_CLK] = &clk_rpmh_ce.hw,
> };
> @@ -419,10 +419,10 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
> static struct clk_hw *sdx55_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
> + [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
> + [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
> + [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
> + [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
> [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> };
> @@ -435,16 +435,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
> static struct clk_hw *sm8150_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
> @@ -455,14 +455,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
> static struct clk_hw *sc7180_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> };
>
> @@ -474,16 +474,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
> static struct clk_hw *sc8180x_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> - [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
> - [RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
> + [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
> + [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
> + [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
> + [RPMH_RF_CLK3] = &sc8180x_rf_clk3_d.hw,
> + [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_d_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
> @@ -494,16 +494,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
> static struct clk_hw *sm8250_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> + [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
> + [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> @@ -514,20 +514,20 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> static struct clk_hw *sm8350_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw,
> - [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
> - [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw,
> - [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw,
> + [RPMH_DIV_CLK1] = &sm8350_div_clk1_div2.hw,
> + [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_div2_ao.hw,
> + [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
> + [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> + [RPMH_RF_CLK5] = &sm8350_rf_clk5_a.hw,
> + [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
> [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
> @@ -541,8 +541,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
> static struct clk_hw *sc8280xp_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
> [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
> @@ -556,18 +556,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
> static struct clk_hw *sm8450_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
> + [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
> + [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2_a4.hw,
> + [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_a4_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> };
>
> @@ -579,14 +579,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
> static struct clk_hw *sc7280_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
> [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
> @@ -600,10 +600,10 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
> static struct clk_hw *sm6350_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw,
> - [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2_g4.hw,
> + [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_g4_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3_g4.hw,
> + [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_g4_ao.hw,
> [RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw,
> [RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw,
> };
> @@ -616,16 +616,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
> static struct clk_hw *sdx65_rpmh_clocks[] = {
> [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
> + [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
> + [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
> };
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 8/8] clk: qcom: rpmh: remove usage of platform name
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (6 preceding siblings ...)
2022-12-02 18:58 ` [PATCH v3 7/8] clk: qcom: rpmh: rename VRM " Dmitry Baryshkov
@ 2022-12-02 18:58 ` Dmitry Baryshkov
2022-12-02 19:30 ` Alex Elder
2022-12-02 19:55 ` [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Bjorn Andersson
2022-12-02 20:58 ` Bjorn Andersson
9 siblings, 1 reply; 15+ messages in thread
From: Dmitry Baryshkov @ 2022-12-02 18:58 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk, Alex Elder
Now that all clocks have individual names, remove the names of SoCs from
the RPMH clock definitions. Replace it with the common clk_rpmh_ prefix.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/clk-rpmh.c | 342 ++++++++++++++++++------------------
1 file changed, 171 insertions(+), 171 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index b543939de1c8..2c2ef4b6d130 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -70,15 +70,15 @@ struct clk_rpmh_desc {
static DEFINE_MUTEX(rpmh_clk_lock);
-#define __DEFINE_CLK_RPMH(_platform, _name, _clk_name, _res_name, \
+#define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \
_res_en_offset, _res_on, _div) \
- static struct clk_rpmh _platform##_##_clk_name##_ao; \
- static struct clk_rpmh _platform##_##_clk_name = { \
+ static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \
+ static struct clk_rpmh clk_rpmh_##_clk_name = { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
- .peer = &_platform##_##_clk_name##_ao, \
+ .peer = &clk_rpmh_##_clk_name##_ao, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE) | \
BIT(RPMH_SLEEP_STATE)), \
@@ -92,12 +92,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
.num_parents = 1, \
}, \
}; \
- static struct clk_rpmh _platform##_##_clk_name##_ao= { \
+ static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
- .peer = &_platform##_##_clk_name, \
+ .peer = &clk_rpmh_##_clk_name, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE)), \
.hw.init = &(struct clk_init_data){ \
@@ -111,12 +111,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
}, \
}
-#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \
+#define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \
+ __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
-#define DEFINE_CLK_RPMH_VRM(_platform, _name, _suffix, _res_name, _div) \
- __DEFINE_CLK_RPMH(_platform, _name, _name##_suffix, _res_name, \
+#define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \
+ __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
@@ -340,33 +340,33 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
};
/* Resource name must match resource id present in cmd-db */
-DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, "xo.lvl", 0x3, 1);
-DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2);
-DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4);
-DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4);
+DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
+DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
+DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
+DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
-DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, _a2, "lnbclka1", 2);
-DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, _a2, "lnbclka2", 2);
-DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, _a2, "lnbclka3", 2);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, _a4, "lnbclka1", 4);
-DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, _a4, "lnbclka2", 4);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, _g4, "lnbclkg2", 4);
-DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, _g4, "lnbclkg3", 4);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, _a, "rfclka1", 1);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, _a, "rfclka2", 1);
-DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, _a, "rfclka3", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, _a, "rfclka4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, _a, "rfclka5", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, _d, "rfclkd1", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, _d, "rfclkd2", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, _d, "rfclkd3", 1);
-DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, _d, "rfclkd4", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
+DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
-DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, _div2, "divclka1", 2);
+DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
@@ -375,18 +375,18 @@ DEFINE_CLK_RPMH_BCM(pka, "PKA0");
DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
@@ -397,16 +397,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
};
static struct clk_hw *sdm670_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
@@ -417,12 +417,12 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
};
static struct clk_hw *sdx55_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
- [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
- [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
- [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
@@ -433,18 +433,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
};
static struct clk_hw *sm8150_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
@@ -453,16 +453,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
};
static struct clk_hw *sc7180_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
@@ -472,18 +472,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
};
static struct clk_hw *sc8180x_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
- [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
- [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
- [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
- [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
- [RPMH_RF_CLK3] = &sc8180x_rf_clk3_d.hw,
- [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_d_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
@@ -492,18 +492,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
};
static struct clk_hw *sm8250_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
@@ -512,22 +512,22 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
};
static struct clk_hw *sm8350_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_DIV_CLK1] = &sm8350_div_clk1_div2.hw,
- [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_div2_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
- [RPMH_RF_CLK5] = &sm8350_rf_clk5_a.hw,
- [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw,
+ [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw,
+ [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
+ [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw,
+ [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
@@ -539,10 +539,10 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
};
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
- [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
- [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
- [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
@@ -554,20 +554,20 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
};
static struct clk_hw *sm8450_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
- [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2_a4.hw,
- [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_a4_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
+ [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
@@ -577,16 +577,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
- [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
@@ -598,14 +598,14 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
};
static struct clk_hw *sm6350_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2_g4.hw,
- [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_g4_ao.hw,
- [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3_g4.hw,
- [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_g4_ao.hw,
- [RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw,
- [RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw,
+ [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw,
+ [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
@@ -614,18 +614,18 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
};
static struct clk_hw *sdx65_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
- [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
- [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
- [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
- [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
- [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
- [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
- [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
- [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
- [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
- [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
- [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
+ [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
};
@@ -636,8 +636,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
};
static struct clk_hw *qdu1000_rpmh_clocks[] = {
- [RPMH_CXO_CLK] = &qdu1000_bi_tcxo_div1.hw,
- [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_div1_ao.hw,
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 8/8] clk: qcom: rpmh: remove usage of platform name
2022-12-02 18:58 ` [PATCH v3 8/8] clk: qcom: rpmh: remove usage of platform name Dmitry Baryshkov
@ 2022-12-02 19:30 ` Alex Elder
0 siblings, 0 replies; 15+ messages in thread
From: Alex Elder @ 2022-12-02 19:30 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Taniya Das
Cc: linux-arm-msm, linux-clk
On 12/2/22 12:58 PM, Dmitry Baryshkov wrote:
> Now that all clocks have individual names, remove the names of SoCs from
> the RPMH clock definitions. Replace it with the common clk_rpmh_ prefix.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
I like it. You can follow up later with alphabetizing the lists
as Bjorn suggested (or someone else can).
Thanks, I think your series is a good improvement.
Reviewed-by: Alex Elder <elder@linaro.org>
> ---
> drivers/clk/qcom/clk-rpmh.c | 342 ++++++++++++++++++------------------
> 1 file changed, 171 insertions(+), 171 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index b543939de1c8..2c2ef4b6d130 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -70,15 +70,15 @@ struct clk_rpmh_desc {
>
> static DEFINE_MUTEX(rpmh_clk_lock);
>
> -#define __DEFINE_CLK_RPMH(_platform, _name, _clk_name, _res_name, \
> +#define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \
> _res_en_offset, _res_on, _div) \
> - static struct clk_rpmh _platform##_##_clk_name##_ao; \
> - static struct clk_rpmh _platform##_##_clk_name = { \
> + static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \
> + static struct clk_rpmh clk_rpmh_##_clk_name = { \
> .res_name = _res_name, \
> .res_addr = _res_en_offset, \
> .res_on_val = _res_on, \
> .div = _div, \
> - .peer = &_platform##_##_clk_name##_ao, \
> + .peer = &clk_rpmh_##_clk_name##_ao, \
> .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
> BIT(RPMH_ACTIVE_ONLY_STATE) | \
> BIT(RPMH_SLEEP_STATE)), \
> @@ -92,12 +92,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> .num_parents = 1, \
> }, \
> }; \
> - static struct clk_rpmh _platform##_##_clk_name##_ao= { \
> + static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \
> .res_name = _res_name, \
> .res_addr = _res_en_offset, \
> .res_on_val = _res_on, \
> .div = _div, \
> - .peer = &_platform##_##_clk_name, \
> + .peer = &clk_rpmh_##_clk_name, \
> .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
> BIT(RPMH_ACTIVE_ONLY_STATE)), \
> .hw.init = &(struct clk_init_data){ \
> @@ -111,12 +111,12 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> }, \
> }
>
> -#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \
> - __DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \
> +#define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \
> + __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \
> CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
>
> -#define DEFINE_CLK_RPMH_VRM(_platform, _name, _suffix, _res_name, _div) \
> - __DEFINE_CLK_RPMH(_platform, _name, _name##_suffix, _res_name, \
> +#define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \
> + __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \
> CLK_RPMH_VRM_EN_OFFSET, 1, _div)
>
> #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
> @@ -340,33 +340,33 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
> };
>
> /* Resource name must match resource id present in cmd-db */
> -DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, "xo.lvl", 0x3, 1);
> -DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2);
> -DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4);
> -DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4);
> +DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
> +DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
> +DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
> +DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
>
> -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, _a2, "lnbclka1", 2);
> -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, _a2, "lnbclka2", 2);
> -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, _a2, "lnbclka3", 2);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
>
> -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, _a4, "lnbclka1", 4);
> -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, _a4, "lnbclka2", 4);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
>
> -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, _g4, "lnbclkg2", 4);
> -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, _g4, "lnbclkg3", 4);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
> +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
>
> -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, _a, "rfclka1", 1);
> -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, _a, "rfclka2", 1);
> -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, _a, "rfclka3", 1);
> -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, _a, "rfclka4", 1);
> -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, _a, "rfclka5", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1);
>
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, _d, "rfclkd1", 1);
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, _d, "rfclkd2", 1);
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, _d, "rfclkd3", 1);
> -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, _d, "rfclkd4", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
> +DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
>
> -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, _div2, "divclka1", 2);
> +DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
>
> DEFINE_CLK_RPMH_BCM(ce, "CE0");
> DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
> @@ -375,18 +375,18 @@ DEFINE_CLK_RPMH_BCM(pka, "PKA0");
> DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
>
> static struct clk_hw *sdm845_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_CE_CLK] = &clk_rpmh_ce.hw,
> };
> @@ -397,16 +397,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
> };
>
> static struct clk_hw *sdm670_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_CE_CLK] = &clk_rpmh_ce.hw,
> };
> @@ -417,12 +417,12 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
> };
>
> static struct clk_hw *sdx55_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
> - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
> - [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
> - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
> [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> };
> @@ -433,18 +433,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
> };
>
> static struct clk_hw *sm8150_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
> @@ -453,16 +453,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
> };
>
> static struct clk_hw *sc7180_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> };
>
> @@ -472,18 +472,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
> };
>
> static struct clk_hw *sc8180x_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw,
> - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw,
> - [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw,
> - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw,
> - [RPMH_RF_CLK3] = &sc8180x_rf_clk3_d.hw,
> - [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_d_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
> @@ -492,18 +492,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
> };
>
> static struct clk_hw *sm8250_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> @@ -512,22 +512,22 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> };
>
> static struct clk_hw *sm8350_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_DIV_CLK1] = &sm8350_div_clk1_div2.hw,
> - [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_div2_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> - [RPMH_RF_CLK5] = &sm8350_rf_clk5_a.hw,
> - [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw,
> + [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw,
> + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
> + [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw,
> + [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
> [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
> @@ -539,10 +539,10 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
> };
>
> static struct clk_hw *sc8280xp_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw,
> - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw,
> - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
> [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
> @@ -554,20 +554,20 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
> };
>
> static struct clk_hw *sm8450_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2_a4.hw,
> - [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_a4_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
> + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> };
>
> @@ -577,16 +577,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
> };
>
> static struct clk_hw *sc7280_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw,
> - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
> [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
> @@ -598,14 +598,14 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
> };
>
> static struct clk_hw *sm6350_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2_g4.hw,
> - [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_g4_ao.hw,
> - [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3_g4.hw,
> - [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_g4_ao.hw,
> - [RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw,
> - [RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw,
> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw,
> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw,
> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw,
> + [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw,
> + [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
> @@ -614,18 +614,18 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
> };
>
> static struct clk_hw *sdx65_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw,
> - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw,
> - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw,
> - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw,
> - [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw,
> - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw,
> - [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw,
> - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw,
> - [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw,
> - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw,
> - [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw,
> - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
> + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
> + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
> [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
> [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
> };
> @@ -636,8 +636,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
> };
>
> static struct clk_hw *qdu1000_rpmh_clocks[] = {
> - [RPMH_CXO_CLK] = &qdu1000_bi_tcxo_div1.hw,
> - [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_div1_ao.hw,
> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
> };
>
> static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (7 preceding siblings ...)
2022-12-02 18:58 ` [PATCH v3 8/8] clk: qcom: rpmh: remove usage of platform name Dmitry Baryshkov
@ 2022-12-02 19:55 ` Bjorn Andersson
2022-12-02 20:58 ` Bjorn Andersson
9 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2022-12-02 19:55 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Konrad Dybcio, Stephen Boyd, Michael Turquette,
Taniya Das, linux-arm-msm, linux-clk, Alex Elder
On Fri, Dec 02, 2022 at 08:58:35PM +0200, Dmitry Baryshkov wrote:
> Both RPM and RPMH clocks use platform (SoC) as a part of the clock
> definition. However there is nothing really SoC-specific in this
> part. Using it just leads to confusion and sometimes to duplication of
> definitions. Drop the SoC name where it is logical.
>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> Changes since v2:
> - Additional rework of ARC/VRM clock handling as suggested by Alex
>
> Changes since v1:
> - Reworked and split the Soc-name removal patch for RPMH clocks
>
> Dmitry Baryshkov (8):
> clk: qcom: rpmh: group clock definitions together
> clk: qcom: rpmh: reuse common duplicate clocks
> clk: qcom: rpmh: drop all _ao names
> clk: qcom: rpmh: remove platform names from BCM clocks
> clk: qcom: rpmh: support separate symbol name for the RPMH clocks
> clk: qcom: rpmh: rename ARC clock data
> clk: qcom: rpmh: rename VRM clock data
> clk: qcom: rpmh: remove usage of platform name
>
> drivers/clk/qcom/clk-rpmh.c | 421 ++++++++++++++++++------------------
> 1 file changed, 205 insertions(+), 216 deletions(-)
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names
2022-12-02 18:58 [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Dmitry Baryshkov
` (8 preceding siblings ...)
2022-12-02 19:55 ` [PATCH v3 0/8] clk: qcom: rpm/rpmh: drop platform names Bjorn Andersson
@ 2022-12-02 20:58 ` Bjorn Andersson
9 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2022-12-02 20:58 UTC (permalink / raw)
To: dmitry.baryshkov, sboyd, quic_tdas, Konrad Dybcio, agross,
mturquette
Cc: linux-arm-msm, elder, linux-clk
On Fri, 2 Dec 2022 20:58:35 +0200, Dmitry Baryshkov wrote:
> Both RPM and RPMH clocks use platform (SoC) as a part of the clock
> definition. However there is nothing really SoC-specific in this
> part. Using it just leads to confusion and sometimes to duplication of
> definitions. Drop the SoC name where it is logical.
>
> Changes since v2:
> - Additional rework of ARC/VRM clock handling as suggested by Alex
>
> [...]
Applied, thanks!
[1/8] clk: qcom: rpmh: group clock definitions together
commit: 82349cc0d1f70df9436da2f565ec10aadf1c3680
[2/8] clk: qcom: rpmh: reuse common duplicate clocks
commit: 65b0c564a34f38832b25b0f5769e9cdf9e5faefd
[3/8] clk: qcom: rpmh: drop all _ao names
commit: 012c226fc68afe32acd7da01a0c2d2e483143bd4
[4/8] clk: qcom: rpmh: remove platform names from BCM clocks
commit: fe20294f4b7b180acc1ab7dcb7feff8601c76d7d
[5/8] clk: qcom: rpmh: support separate symbol name for the RPMH clocks
commit: 49e4aa233c6c239f814e8872d6757455e49e8106
[6/8] clk: qcom: rpmh: rename ARC clock data
commit: 166eb3eb3bb394255a9a8aa4cadbba5567ba184a
[7/8] clk: qcom: rpmh: rename VRM clock data
commit: 6ad844d739ee57779d3814fe3c9f97dff68719b2
[8/8] clk: qcom: rpmh: remove usage of platform name
commit: ec304d02b988132ac037c5b41fe375950c55de87
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 15+ messages in thread