From: Stephen Boyd <sboyd@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Biju Das <biju.das.au@gmail.com>
Subject: Re: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock
Date: Wed, 05 Mar 2025 15:16:46 -0800 [thread overview]
Message-ID: <1347ee4d678ce81c33917b3802601aee.sboyd@kernel.org> (raw)
In-Reply-To: <20250303110433.76576-2-biju.das.jz@bp.renesas.com>
Quoting Biju Das (2025-03-03 03:04:19)
> The spi and spix2 clk share same bit for clock gating. Add support
> for coupled clock with checking the monitor bit for both the clocks.
Could you add an intermediate parent clk of both spi and spix2 that only
handles the enable bit for clock gating? Then the enable count handling
would be in the core clk code.
next prev parent reply other threads:[~2025-03-05 23:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-03 11:04 [PATCH 0/4] Add RZ/G3E XSPI clocks Biju Das
2025-03-03 11:04 ` [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock Biju Das
2025-03-05 23:16 ` Stephen Boyd [this message]
2025-03-06 10:10 ` Biju Das
2025-03-06 22:36 ` Stephen Boyd
[not found] ` <TY3PR01MB113469E04E10E3D14FB3F69F186D52@TY3PR01MB11346.jpnprd01.prod.outlook.com>
2025-03-14 7:18 ` Biju Das
2025-03-20 21:56 ` Stephen Boyd
2025-03-21 14:21 ` Biju Das
2025-03-24 23:48 ` Stephen Boyd
2025-03-25 12:22 ` Biju Das
2025-03-26 15:17 ` Biju Das
2025-03-03 11:04 ` [PATCH 2/4] clk: renesas: rzv2h-cpg: Add support for static dividers Biju Das
2025-03-03 11:04 ` [PATCH 3/4] clk: renesas: r9a09g047: Add support for xspi mux and divider Biju Das
2025-03-03 11:04 ` [PATCH 4/4] clk: renesas: r9a09g047: Add XSPI clock/reset Biju Das
2025-03-06 14:44 ` Geert Uytterhoeven
2025-03-20 9:56 ` Biju Das
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