[PATCH 0/6] arc_emac: fixes the emac issues oand cleanup emac drivers

[PATCH 0/6] arc_emac: fixes the emac issues oand cleanup emac drivers

[Caesar Wang]

This series patches are based on kernel 4.5-rc7+ version.
Linux version 4.5.0-rc7-next-20160310+ (wxt@nb) (...) #23 SMP Fri Mar 11 15:55:53

Verified on kylin board with my github.
https://github.com/Caesar-github/rockchip/tree/kylin/next

That's verified on kylin board with ubuntu os.

How to test and verify?

You can refer to the following wiki document.
http://rockchip.wikidot.com/linux-develop-guide

bootup log:
   1.268113] rockchip_emac 10200000.ethernet: no regulator found
   [    1.286682] rockchip_emac 10200000.ethernet: ARC EMAC detected with id: 0x7fd02
   [    1.294007] rockchip_emac 10200000.ethernet: IRQ is 29
   [    1.299453] rockchip_emac 10200000.ethernet: MAC address is now 1e:cd:18:78:90:25
   [    1.726564] rockchip_emac 10200000.ethernet: connected to Generic PHY phy with id 0x1cc816
   [    8.936862] rockchip_emac 10200000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off

root@localhost:/# busybox ping www.baidu.com
PING www.baidu.com (14.215.177.38): 56 data bytes
64 bytes from 14.215.177.38: seq=0 ttl=48 time=35.046 ms
64 bytes from 14.215.177.38: seq=1 ttl=48 time=35.095 ms
64 bytes from 14.215.177.38: seq=2 ttl=48 time=34.203 ms
64 bytes from 14.215.177.38: seq=3 ttl=48 time=38.516 ms
...
---

1) This series has 6 patches: (1--->6)
net: arc_emac: make the rockchip emac document more compatible
net: arc_emac: add phy-reset-* are optional for device tree
net: arc_emac: support the phy reset for emac driver
net: arc: trivial: cleanup the emac driver
clk: rockchip: rk3036: fix and add node id for emac clock
ARM: dts: rockchip: add support emac for RK3036

2) This series patches have the following decriptions:

Hi Rob, David:
PATCH[1/6-2/6]: ====>
net: arc_emac: make the rockchip emac document more compatible
net: arc_emac: add phy-reset-* are optional for device tree

The patches change the rockchip emac document for more compatible and
Add the phy-reset-* property for document.

This patch adds the following property for arc_emac.

phy-reset-* include the following:
1) phy-reset-gpios:
The phy-reset-gpios is an optional property for arc emac device tree boot.
Change the binding document to match the driver code.

2) phy-reset-duration:
Different boards may require different phy reset duration. Add property
phy-reset-duration for device tree probe, so that the boards that need
a longer reset duration can specify it in their device tree.

3) phy-reset-active-high:
We need that for a custom hardware that needs the reverse reset sequence.
---

Hi David
PATCH[3/6]: ====>
net: arc_emac: support the phy reset for emac driver

The emac didn't work on kylin board since in some case the clocks parent changed.
The kylin hardware connects the phy reset pin, we should use it with real world.

As the previous patch discuss on https://patchwork.kernel.org/patch/8186801/

Hi David
PATCH[4/6]: ====>
net: arc: trivial: cleanup the emac driver

The first time to look the emac drivers, I think that have to cleanup the drivers with scripts.
Although it's the trivial things, in order to be more read.
---

Hi Heiko,Michael,Stephen:
PATCH[5/6]: ====>
clk: rockchip: rk3036: fix and add node id for emac clock

Add the emac needed clocks for rk3036 SOCs
---

Hi Heiko:
PATCH[6/6]: ====>
ARM: dts: rockchip: add support emac for RK3036

Add the emac node info for rk3036 dts/dtsi.
---

Thanks your reviewing! :)



Caesar Wang (4):
  net: arc_emac: make the rockchip emac document more compatible
  net: arc_emac: add phy-reset-* are optional for device tree
  net: arc_emac: support the phy reset for emac driver
  net: arc: trivial: cleanup the emac driver

zhengxing (2):
  clk: rockchip: rk3036: fix and add node id for emac clock
  ARM: dts: rockchip: add support emac for RK3036

 Documentation/devicetree/bindings/net/arc_emac.txt | 10 +++
 .../devicetree/bindings/net/emac_rockchip.txt      |  8 ++-
 arch/arm/boot/dts/rk3036-evb.dts                   | 23 +++++++
 arch/arm/boot/dts/rk3036-kylin.dts                 | 20 ++++++
 arch/arm/boot/dts/rk3036.dtsi                      | 39 +++++++++++
 drivers/clk/rockchip/clk-rk3036.c                  |  9 ++-
 drivers/net/ethernet/arc/emac.h                    | 54 +++++++--------
 drivers/net/ethernet/arc/emac_main.c               | 76 +++++++++++++++++-----
 drivers/net/ethernet/arc/emac_mdio.c               |  2 +-
 drivers/net/ethernet/arc/emac_rockchip.c           | 41 ++++++++----
 include/dt-bindings/clock/rk3036-cru.h             |  2 +
 11 files changed, 221 insertions(+), 63 deletions(-)

-- 
1.9.1

[PATCH 5/6] clk: rockchip: rk3036: fix and add node id for emac clock

[Caesar Wang]

From: zhengxing <zhengxing@rock-chips.com>

In the emac driver, we need to refer HCLK_MAC since there are
only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clocks are under the
GPLL, and it is unable to provide the accurate rate for mac_ref which
need to 50MHz probability, we should let it under the DPLL and are
able to set the freq which integer multiples of 50MHz, so we add these
emac node for reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3036.c      | 9 ++++++---
 include/dt-bindings/clock/rk3036-cru.h | 2 ++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 0703c8f..27c35fa 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -348,8 +348,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
 			RK2928_CLKGATE_CON(10), 5, GFLAGS),
 
-	COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
-			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
+	MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
+			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
+	DIV(0, "mac_pll_src", "mac_pll_pre", 0,
+			RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
+
 	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
 
@@ -408,7 +411,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 	GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
 	GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
 	GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
-	GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
+	GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
 
 	/* pclk_peri gates */
 	GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b..de44109 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -54,6 +54,7 @@
 #define SCLK_PVTM_VIDEO		125
 #define SCLK_MAC		151
 #define SCLK_MACREF		152
+#define SCLK_MACPLL		153
 #define SCLK_SFC		160
 
 /* aclk gates */
@@ -92,6 +93,7 @@
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
 #define HCLK_EMMC		459
+#define HCLK_MAC		460
 #define HCLK_I2S		462
 #define HCLK_LCDC		465
 #define HCLK_ROM		467
-- 
1.9.1

Re: [PATCH 5/6] clk: rockchip: rk3036: fix and add node id for emac clock

[Heiko Stübner]

Hi Caesar,

Am Freitag, 11. M=E4rz 2016, 18:55:30 schrieb Caesar Wang:
> From: zhengxing <zhengxing@rock-chips.com>
>=20
> In the emac driver, we need to refer HCLK_MAC since there are
> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clocks are under the
> GPLL, and it is unable to provide the accurate rate for mac_ref which=

> need to 50MHz probability, we should let it under the DPLL and are
> able to set the freq which integer multiples of 50MHz, so we add thes=
e
> emac node for reference.
>=20
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

I think I mentioned it somewhere before, but I'd like to do this
differently, like in [0].

That should work in a similar way and at least in my tests the reported=

clock rate seems to be correct. As I said as well I haven't been able t=
o
make the emac detect a link on my kylin boards, so it would be cool
if you could test if this different approach works in practice as well.=



Thanks
Heiko

------ 8< ---------
>From e83a8b19dbf95c40d2c908727c342fbc6b167ea1 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Fri, 19 Feb 2016 21:31:43 +0100
Subject: [PATCH] clk: rockchip: associate SCLK_MAC_PLL and disable repa=
renting
 on rk3036

The emac needs constant and very specific rate but the possible PLL-sou=
rces
are very limited, so we expect the PLL source to be set manually on per=

board and don't want it to get changed in an automatic way later.
So add the necessary clock-id and disable reparenting on set_rate calls=
.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3036.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/c=
lk-rk3036.c
index 3c742bf..0084c57 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -348,7 +348,7 @@ static struct rockchip_clk_branch rk3036_clk_branch=
es[] __initdata =3D {
 =09=09=09RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
 =09=09=09RK2928_CLKGATE_CON(10), 5, GFLAGS),
=20
-=09COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
+=09COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, C=
LK_SET_RATE_NO_REPARENT,
 =09=09=09RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
 =09MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
 =09=09=09RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),

------ 8< ---------


[0] https://github.com/mmind/linux-rockchip/commit/e83a8b19dbf95c40d2c9=
08727c342fbc6b167ea1


> ---
>=20
>  drivers/clk/rockchip/clk-rk3036.c      | 9 ++++++---
>  include/dt-bindings/clock/rk3036-cru.h | 2 ++
>  2 files changed, 8 insertions(+), 3 deletions(-)
>=20
> diff --git a/drivers/clk/rockchip/clk-rk3036.c
> b/drivers/clk/rockchip/clk-rk3036.c index 0703c8f..27c35fa 100644
> --- a/drivers/clk/rockchip/clk-rk3036.c
> +++ b/drivers/clk/rockchip/clk-rk3036.c
> @@ -348,8 +348,11 @@ static struct rockchip_clk_branch rk3036_clk_bra=
nches[]
> __initdata =3D { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
>  =09=09=09RK2928_CLKGATE_CON(10), 5, GFLAGS),
>=20
> -=09COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
> -=09=09=09RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
> +=09MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
> +=09=09=09RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
> +=09DIV(0, "mac_pll_src", "mac_pll_pre", 0,
> +=09=09=09RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
> +
>  =09MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
>  =09=09=09RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
>=20
> @@ -408,7 +411,7 @@ static struct rockchip_clk_branch rk3036_clk_bran=
ches[]
> __initdata =3D { GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE=
_UNUSED,
> RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", "hclk_p=
eri",
> 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_sfc", "hclk_peri"=
,
> CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), -=09GATE(0,
> "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15=
,
> GFLAGS), +=09GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0,
> RK2928_CLKGATE_CON(3), 5, GFLAGS),
>=20
>  =09/* pclk_peri gates */
>  =09GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED,
> RK2928_CLKGATE_CON(4), 1, GFLAGS), diff --git
> a/include/dt-bindings/clock/rk3036-cru.h
> b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b..de44109 10064=
4
> --- a/include/dt-bindings/clock/rk3036-cru.h
> +++ b/include/dt-bindings/clock/rk3036-cru.h
> @@ -54,6 +54,7 @@
>  #define SCLK_PVTM_VIDEO=09=09125
>  #define SCLK_MAC=09=09151
>  #define SCLK_MACREF=09=09152
> +#define SCLK_MACPLL=09=09153
>  #define SCLK_SFC=09=09160
>=20
>  /* aclk gates */
> @@ -92,6 +93,7 @@
>  #define HCLK_SDMMC=09=09456
>  #define HCLK_SDIO=09=09457
>  #define HCLK_EMMC=09=09459
> +#define HCLK_MAC=09=09460
>  #define HCLK_I2S=09=09462
>  #define HCLK_LCDC=09=09465
>  #define HCLK_ROM=09=09467

Re: [PATCH 5/6] clk: rockchip: rk3036: fix and add node id for emac clock

[Caesar Wang]

Hi Heiko,

The link [0] need a bit changes if we want the emac to be happy work.

-RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),

+RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),


I will need resend the series patches with your change in link[0], OK?

Since the Mr.rebot just notice the build error, I will check and resend 
with your emac changing.




在 2016年03月11日 19:15, Heiko Stübner 写道:
> Hi Caesar,
>
> Am Freitag, 11. März 2016, 18:55:30 schrieb Caesar Wang:
>> From: zhengxing <zhengxing@rock-chips.com>
>>
>> In the emac driver, we need to refer HCLK_MAC since there are
>> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clocks are under the
>> GPLL, and it is unable to provide the accurate rate for mac_ref which
>> need to 50MHz probability, we should let it under the DPLL and are
>> able to set the freq which integer multiples of 50MHz, so we add these
>> emac node for reference.
>>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> I think I mentioned it somewhere before, but I'd like to do this
> differently, like in [0].
>
> That should work in a similar way and at least in my tests the reported
> clock rate seems to be correct. As I said as well I haven't been able to
> make the emac detect a link on my kylin boards, so it would be cool
> if you could test if this different approach works in practice as well.

I fetch your branch patches, it doesn't work for me.
c467a5f clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on 
rk3036
ae7ed09 clk: rockchip: add clock-id for rk3036 emac pll source clock
f876a7e clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
5093371 clk: rockchip: add node-id for rk3036 emac hclk

f44eeee Revert "clk: rockchip: rk3036: fix and add node id for emac clock"
..

It works if the patch
c467a5f clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on 
rk3036 to change as following

--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -348,8 +348,8 @@ static struct rockchip_clk_branch 
rk3036_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
                         RK2928_CLKGATE_CON(10), 5, GFLAGS),

-       COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
-                       RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
+       COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", 
mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
+                       RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),


>
>
> Thanks
> Heiko
>
> ------ 8< ---------
>  From e83a8b19dbf95c40d2c908727c342fbc6b167ea1 Mon Sep 17 00:00:00 2001
> From: Heiko Stuebner <heiko@sntech.de>
> Date: Fri, 19 Feb 2016 21:31:43 +0100
> Subject: [PATCH] clk: rockchip: associate SCLK_MAC_PLL and disable reparenting
>   on rk3036
>
> The emac needs constant and very specific rate but the possible PLL-sources
> are very limited, so we expect the PLL source to be set manually on per
> board and don't want it to get changed in an automatic way later.
> So add the necessary clock-id and disable reparenting on set_rate calls.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>   drivers/clk/rockchip/clk-rk3036.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
> index 3c742bf..0084c57 100644
> --- a/drivers/clk/rockchip/clk-rk3036.c
> +++ b/drivers/clk/rockchip/clk-rk3036.c
> @@ -348,7 +348,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
>   			RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
>   			RK2928_CLKGATE_CON(10), 5, GFLAGS),
>   
> -	COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
> +	COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
>   			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),

-RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),

+RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),



>   	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
>   			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
>
> ------ 8< ---------
>
>
> [0] https://github.com/mmind/linux-rockchip/commit/e83a8b19dbf95c40d2c908727c342fbc6b167ea1
>
>
>> ---
>>
>>   drivers/clk/rockchip/clk-rk3036.c      | 9 ++++++---
>>   include/dt-bindings/clock/rk3036-cru.h | 2 ++
>>   2 files changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3036.c
>> b/drivers/clk/rockchip/clk-rk3036.c index 0703c8f..27c35fa 100644
>> --- a/drivers/clk/rockchip/clk-rk3036.c
>> +++ b/drivers/clk/rockchip/clk-rk3036.c
>> @@ -348,8 +348,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[]
>> __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
>>   			RK2928_CLKGATE_CON(10), 5, GFLAGS),
>>
>> -	COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
>> -			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
>> +	MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
>> +			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
>> +	DIV(0, "mac_pll_src", "mac_pll_pre", 0,
>> +			RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
>> +
>>   	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
>>   			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
>>
>> @@ -408,7 +411,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[]
>> __initdata = { GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED,
>> RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", "hclk_peri",
>> 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_sfc", "hclk_peri",
>> CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), -	GATE(0,
>> "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15,
>> GFLAGS), +	GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0,
>> RK2928_CLKGATE_CON(3), 5, GFLAGS),
>>
>>   	/* pclk_peri gates */
>>   	GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED,
>> RK2928_CLKGATE_CON(4), 1, GFLAGS), diff --git
>> a/include/dt-bindings/clock/rk3036-cru.h
>> b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b..de44109 100644
>> --- a/include/dt-bindings/clock/rk3036-cru.h
>> +++ b/include/dt-bindings/clock/rk3036-cru.h
>> @@ -54,6 +54,7 @@
>>   #define SCLK_PVTM_VIDEO		125
>>   #define SCLK_MAC		151
>>   #define SCLK_MACREF		152
>> +#define SCLK_MACPLL		153
>>   #define SCLK_SFC		160
>>
>>   /* aclk gates */
>> @@ -92,6 +93,7 @@
>>   #define HCLK_SDMMC		456
>>   #define HCLK_SDIO		457
>>   #define HCLK_EMMC		459
>> +#define HCLK_MAC		460
>>   #define HCLK_I2S		462
>>   #define HCLK_LCDC		465
>>   #define HCLK_ROM		467
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar

Re: [PATCH 5/6] clk: rockchip: rk3036: fix and add node id for emac clock

[Heiko Stübner]

Hi Caesar,

Am Freitag, 11. M=C3=A4rz 2016, 20:01:10 schrieb Caesar Wang:
> The link [0] need a bit changes if we want the emac to be happy work.=

>=20
> -RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
>=20
> +RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),

ah, then that is probably the reason I don't get connectivity. Thanks f=
or=20
noticing this.


> I will need resend the series patches with your change in link[0], OK=
?
>=20
> Since the Mr.rebot just notice the build error, I will check and rese=
nd
> with your emac changing.

ok, great :-D


Thanks
Heiko


> =E5=9C=A8 2016=E5=B9=B403=E6=9C=8811=E6=97=A5 19:15, Heiko St=C3=BCbn=
er =E5=86=99=E9=81=93:
> > Hi Caesar,
> >=20
> > Am Freitag, 11. M=C3=A4rz 2016, 18:55:30 schrieb Caesar Wang:
> >> From: zhengxing <zhengxing@rock-chips.com>
> >>=20
> >> In the emac driver, we need to refer HCLK_MAC since there are
> >> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clocks are under t=
he
> >> GPLL, and it is unable to provide the accurate rate for mac_ref wh=
ich
> >> need to 50MHz probability, we should let it under the DPLL and are=

> >> able to set the freq which integer multiples of 50MHz, so we add t=
hese
> >> emac node for reference.
> >>=20
> >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> >=20
> > I think I mentioned it somewhere before, but I'd like to do this
> > differently, like in [0].
> >=20
> > That should work in a similar way and at least in my tests the repo=
rted
> > clock rate seems to be correct. As I said as well I haven't been ab=
le to
> > make the emac detect a link on my kylin boards, so it would be cool=

> > if you could test if this different approach works in practice as w=
ell.
>=20
> I fetch your branch patches, it doesn't work for me.
> c467a5f clk: rockchip: associate SCLK_MAC_PLL and disable reparenting=
 on
> rk3036
> ae7ed09 clk: rockchip: add clock-id for rk3036 emac pll source clock
> f876a7e clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
> 5093371 clk: rockchip: add node-id for rk3036 emac hclk
>=20
> f44eeee Revert "clk: rockchip: rk3036: fix and add node id for emac c=
lock"
> ..
>=20
> It works if the patch
> c467a5f clk: rockchip: associate SCLK_MAC_PLL and disable reparenting=
 on
> rk3036 to change as following
>=20
> --- a/drivers/clk/rockchip/clk-rk3036.c
> +++ b/drivers/clk/rockchip/clk-rk3036.c
> @@ -348,8 +348,8 @@ static struct rockchip_clk_branch
> rk3036_clk_branches[] __initdata =3D {
>                          RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, D=
FLAGS,
>                          RK2928_CLKGATE_CON(10), 5, GFLAGS),
>=20
> -       COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
> -                       RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DF=
LAGS),
> +       COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src",
> mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
> +                       RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DF=
LAGS),
>=20
> > Thanks
> > Heiko
> >=20
> > ------ 8< ---------
> >=20
> >  From e83a8b19dbf95c40d2c908727c342fbc6b167ea1 Mon Sep 17 00:00:00 =
2001
> >=20
> > From: Heiko Stuebner <heiko@sntech.de>
> > Date: Fri, 19 Feb 2016 21:31:43 +0100
> > Subject: [PATCH] clk: rockchip: associate SCLK_MAC_PLL and disable
> > reparenting>=20
> >   on rk3036
> >=20
> > The emac needs constant and very specific rate but the possible
> > PLL-sources
> > are very limited, so we expect the PLL source to be set manually on=
 per
> > board and don't want it to get changed in an automatic way later.
> > So add the necessary clock-id and disable reparenting on set_rate c=
alls.
> >=20
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >=20
> >   drivers/clk/rockchip/clk-rk3036.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >=20
> > diff --git a/drivers/clk/rockchip/clk-rk3036.c
> > b/drivers/clk/rockchip/clk-rk3036.c index 3c742bf..0084c57 100644
> > --- a/drivers/clk/rockchip/clk-rk3036.c
> > +++ b/drivers/clk/rockchip/clk-rk3036.c
> > @@ -348,7 +348,7 @@ static struct rockchip_clk_branch
> > rk3036_clk_branches[] __initdata =3D {>=20
> >   =09=09=09RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
> >   =09=09=09RK2928_CLKGATE_CON(10), 5, GFLAGS),
> >=20
> > -=09COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
> > +=09COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_=
p,
> > CLK_SET_RATE_NO_REPARENT,>=20
> >   =09=09=09RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
>=20
> -RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
>=20
> +RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
>=20
> >   =09MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT=
,
> >   =09
> >   =09=09=09RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
> >=20
> > ------ 8< ---------
> >=20
> >=20
> > [0]
> > https://github.com/mmind/linux-rockchip/commit/e83a8b19dbf95c40d2c9=
08727c
> > 342fbc6b167ea1>=20
> >> ---
> >>=20
> >>   drivers/clk/rockchip/clk-rk3036.c      | 9 ++++++---
> >>   include/dt-bindings/clock/rk3036-cru.h | 2 ++
> >>   2 files changed, 8 insertions(+), 3 deletions(-)
> >>=20
> >> diff --git a/drivers/clk/rockchip/clk-rk3036.c
> >> b/drivers/clk/rockchip/clk-rk3036.c index 0703c8f..27c35fa 100644
> >> --- a/drivers/clk/rockchip/clk-rk3036.c
> >> +++ b/drivers/clk/rockchip/clk-rk3036.c
> >> @@ -348,8 +348,11 @@ static struct rockchip_clk_branch
> >> rk3036_clk_branches[] __initdata =3D { RK2928_CLKSEL_CON(16), 0, 2=
,
> >> MFLAGS, 2, 5, DFLAGS,
> >>=20
> >>   =09=09=09RK2928_CLKGATE_CON(10), 5, GFLAGS),
> >>=20
> >> -=09COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
> >> -=09=09=09RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
> >> +=09MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
> >> +=09=09=09RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
> >> +=09DIV(0, "mac_pll_src", "mac_pll_pre", 0,
> >> +=09=09=09RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
> >> +
> >>=20
> >>   =09MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PAREN=
T,
> >>   =09
> >>   =09=09=09RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
> >>=20
> >> @@ -408,7 +411,7 @@ static struct rockchip_clk_branch
> >> rk3036_clk_branches[]
> >> __initdata =3D { GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri",
> >> CLK_IGNORE_UNUSED,
> >> RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s",
> >> "hclk_peri",
> >> 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_sfc", "hclk_pe=
ri",
> >> CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), -=09GATE(0,=

> >> "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3),=
 15,
> >> GFLAGS), +=09GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0,
> >> RK2928_CLKGATE_CON(3), 5, GFLAGS),
> >>=20
> >>   =09/* pclk_peri gates */
> >>   =09GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED,
> >>=20
> >> RK2928_CLKGATE_CON(4), 1, GFLAGS), diff --git
> >> a/include/dt-bindings/clock/rk3036-cru.h
> >> b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b..de44109 10=
0644
> >> --- a/include/dt-bindings/clock/rk3036-cru.h
> >> +++ b/include/dt-bindings/clock/rk3036-cru.h
> >> @@ -54,6 +54,7 @@
> >>=20
> >>   #define SCLK_PVTM_VIDEO=09=09125
> >>   #define SCLK_MAC=09=09151
> >>   #define SCLK_MACREF=09=09152
> >>=20
> >> +#define SCLK_MACPLL=09=09153
> >>=20
> >>   #define SCLK_SFC=09=09160
> >>  =20
> >>   /* aclk gates */
> >>=20
> >> @@ -92,6 +93,7 @@
> >>=20
> >>   #define HCLK_SDMMC=09=09456
> >>   #define HCLK_SDIO=09=09457
> >>   #define HCLK_EMMC=09=09459
> >>=20
> >> +#define HCLK_MAC=09=09460
> >>=20
> >>   #define HCLK_I2S=09=09462
> >>   #define HCLK_LCDC=09=09465
> >>   #define HCLK_ROM=09=09467
> >=20
> > _______________________________________________
> > Linux-rockchip mailing list
> > Linux-rockchip@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH 0/6] arc_emac: fixes the emac issues oand cleanup emac drivers

[Sergei Shtylyov]

Hello.

On 3/11/2016 1:55 PM, Caesar Wang wrote:

> This series patches are based on kernel 4.5-rc7+ version.
> Linux version 4.5.0-rc7-next-20160310+ (wxt@nb) (...) #23 SMP Fri Mar 11 15:55:53

[...]

> 1) This series has 6 patches: (1--->6)
> net: arc_emac: make the rockchip emac document more compatible
> net: arc_emac: add phy-reset-* are optional for device tree

    I'm not seeing these patches on netdev...

> net: arc_emac: support the phy reset for emac driver
> net: arc: trivial: cleanup the emac driver
> clk: rockchip: rk3036: fix and add node id for emac clock
> ARM: dts: rockchip: add support emac for RK3036
>
> 2) This series patches have the following decriptions:

    Descriptions.

> Hi Rob, David:
> PATCH[1/6-2/6]: ====>
> net: arc_emac: make the rockchip emac document more compatible
> net: arc_emac: add phy-reset-* are optional for device tree
>
> The patches change the rockchip emac document for more compatible and
> Add the phy-reset-* property for document.
>
> This patch adds the following property for arc_emac.
>
> phy-reset-* include the following:
> 1) phy-reset-gpios:
> The phy-reset-gpios is an optional property for arc emac device tree boot.
> Change the binding document to match the driver code.
>
> 2) phy-reset-duration:
> Different boards may require different phy reset duration. Add property
> phy-reset-duration for device tree probe, so that the boards that need
> a longer reset duration can specify it in their device tree.
>
> 3) phy-reset-active-high:
> We need that for a custom hardware that needs the reverse reset sequence.

    Why not infer this from the "phy-reset-gpios" prop?

MBR, Sergei

Re: [PATCH 0/6] arc_emac: fixes the emac issues oand cleanup emac drivers

[Caesar Wang]

Hi Sergei,

在 2016年03月11日 21:46, Sergei Shtylyov 写道:
> Hello.
>
> On 3/11/2016 1:55 PM, Caesar Wang wrote:
>
>> This series patches are based on kernel 4.5-rc7+ version.
>> Linux version 4.5.0-rc7-next-20160310+ (wxt@nb) (...) #23 SMP Fri Mar 
>> 11 15:55:53
>
> [...]
>
>> 1) This series has 6 patches: (1--->6)
>> net: arc_emac: make the rockchip emac document more compatible
>> net: arc_emac: add phy-reset-* are optional for device tree
>
>    I'm not seeing these patches on netdev...

Sent by the patman tool.

LKML:
https://patchwork.kernel.org/patch/8564501/
https://patchwork.kernel.org/patch/8564511/

>
>> net: arc_emac: support the phy reset for emac driver
>> net: arc: trivial: cleanup the emac driver
>> clk: rockchip: rk3036: fix and add node id for emac clock
>> ARM: dts: rockchip: add support emac for RK3036
>>
>> 2) This series patches have the following decriptions:
>
>    Descriptions.
>
>> Hi Rob, David:
>> PATCH[1/6-2/6]: ====>
>> net: arc_emac: make the rockchip emac document more compatible
>> net: arc_emac: add phy-reset-* are optional for device tree
>>
>> The patches change the rockchip emac document for more compatible and
>> Add the phy-reset-* property for document.
>>
>> This patch adds the following property for arc_emac.
>>
>> phy-reset-* include the following:
>> 1) phy-reset-gpios:
>> The phy-reset-gpios is an optional property for arc emac device tree 
>> boot.
>> Change the binding document to match the driver code.
>>
>> 2) phy-reset-duration:
>> Different boards may require different phy reset duration. Add property
>> phy-reset-duration for device tree probe, so that the boards that need
>> a longer reset duration can specify it in their device tree.
>>
>> 3) phy-reset-active-high:
>> We need that for a custom hardware that needs the reverse reset 
>> sequence.
>
>    Why not infer this from the "phy-reset-gpios" prop?

See:
https://patchwork.kernel.org/patch/8564511/

phy-reset-active-high : If present then the reset sequence using the GPIO
  specified in the "phy-reset-gpios" property is reversed (H=reset state,
  L=operation state).


Thanks,

Caesar

>
> MBR, Sergei
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH 0/6] arc_emac: fixes the emac issues oand cleanup emac drivers

[Sergei Shtylyov]

Hello.

On 03/11/2016 05:48 PM, Caesar Wang wrote:

[...]

>>> Hi Rob, David:
>>> PATCH[1/6-2/6]: ====>
>>> net: arc_emac: make the rockchip emac document more compatible
>>> net: arc_emac: add phy-reset-* are optional for device tree
>>>
>>> The patches change the rockchip emac document for more compatible and
>>> Add the phy-reset-* property for document.
>>>
>>> This patch adds the following property for arc_emac.
>>>
>>> phy-reset-* include the following:
>>> 1) phy-reset-gpios:
>>> The phy-reset-gpios is an optional property for arc emac device tree boot.
>>> Change the binding document to match the driver code.
>>>
>>> 2) phy-reset-duration:
>>> Different boards may require different phy reset duration. Add property
>>> phy-reset-duration for device tree probe, so that the boards that need
>>> a longer reset duration can specify it in their device tree.
>>>
>>> 3) phy-reset-active-high:
>>> We need that for a custom hardware that needs the reverse reset sequence.
>>
>>    Why not infer this from the "phy-reset-gpios" prop?
>
> See:
> https://patchwork.kernel.org/patch/8564511/
 >
> phy-reset-active-high : If present then the reset sequence using the GPIO
>   specified in the "phy-reset-gpios" property is reversed (H=reset state,
>   L=operation state).

    Referring to your own suggested bindings isn't an answer. If the driver 
that you're copying from here (fec) had a reason to handle the GPIO sense with 
the help of an extra prop (legacy code), it doesn't mean your new driver needs 
to mimic this as well, AFAIU...

> Thanks,
>
> Caesar

MBR, Sergei

Re: [PATCH 0/6] arc_emac: fixes the emac issues oand cleanup emac drivers

[Caesar Wang]

在 2016年03月12日 02:46, Sergei Shtylyov 写道:
> Hello.
>
> On 03/11/2016 05:48 PM, Caesar Wang wrote:
>
> [...]
>
>>>> Hi Rob, David:
>>>> PATCH[1/6-2/6]: ====>
>>>> net: arc_emac: make the rockchip emac document more compatible
>>>> net: arc_emac: add phy-reset-* are optional for device tree
>>>>
>>>> The patches change the rockchip emac document for more compatible and
>>>> Add the phy-reset-* property for document.
>>>>
>>>> This patch adds the following property for arc_emac.
>>>>
>>>> phy-reset-* include the following:
>>>> 1) phy-reset-gpios:
>>>> The phy-reset-gpios is an optional property for arc emac device 
>>>> tree boot.
>>>> Change the binding document to match the driver code.
>>>>
>>>> 2) phy-reset-duration:
>>>> Different boards may require different phy reset duration. Add 
>>>> property
>>>> phy-reset-duration for device tree probe, so that the boards that need
>>>> a longer reset duration can specify it in their device tree.
>>>>
>>>> 3) phy-reset-active-high:
>>>> We need that for a custom hardware that needs the reverse reset 
>>>> sequence.
>>>
>>>    Why not infer this from the "phy-reset-gpios" prop?
>>
>> See:
>> https://patchwork.kernel.org/patch/8564511/
> >
>> phy-reset-active-high : If present then the reset sequence using the 
>> GPIO
>>   specified in the "phy-reset-gpios" property is reversed (H=reset 
>> state,
>>   L=operation state).
>
>    Referring to your own suggested bindings isn't an answer. If the 
> driver that you're copying from here (fec) had a reason to handle the 
> GPIO sense with the help of an extra prop (legacy code), it doesn't 
> mean your new driver needs to mimic this as well, AFAIU...

I know your suggestion is a fair request.

Oh, that copy from the 'freescale/fec_main.c' ....

So, The exist way was old and unwise in mainline. :(

wxt@nb:~/kernel/drivers/net/ethernet$ ag reset-gpios
micrel/ks8851.c
1427:    gpio = of_get_named_gpio_flags(spi->dev.of_node, "reset-gpios",

arc/emac_main.c
787:    phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
797:        dev_err(dev, "failed to get phy-reset-gpios: %d\n", err);

arc/emac_main.c~
784:    phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
794:        dev_err(dev, "failed to get phy-reset-gpios: %d\n", err);

davicom/dm9000.c
1451:    reset_gpios = of_get_named_gpio_flags(dev->of_node, 
"reset-gpios", 0,

freescale/fec_main.c
3206:    phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3216:        dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", 
err);

cadence/macb.c
2958:        int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);

...


Anyway, I will update it with your suggestion.

Thanks,


Caesar





>
>> Thanks,
>>
>> Caesar
>
> MBR, Sergei
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar