* [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] [not found] <1472569308.5703.22.camel@toradex.com> @ 2016-08-31 7:15 ` Marcel Ziswiler 2016-08-31 9:47 ` Mirza Krak 0 siblings, 1 reply; 3+ messages in thread From: Marcel Ziswiler @ 2016-08-31 7:15 UTC (permalink / raw) To: jonathanh@nvidia.com, mirza.krak@gmail.com, swarren@wwwdotorg.org, thierry.reding@gmail.com Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, mturquette@baylibre.com, pgaikwad@nvidia.com, linux@armlinux.org.uk, devicetree@vger.kernel.org, gnurou@gmail.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, pdeschrijver@nvidia.com, sboyd@codeaurora.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org T24gV2VkLCAyMDE2LTA4LTI0IGF0IDE1OjM3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiAN Cj4gRnJvbTogTWlyemEgS3JhayA8bWlyemEua3Jhay1SZTVKUUVlUXFlOEF2eHRpdU13eDN3QHB1 YmxpYy5nbWFuZS5vcmc+DQo+IA0KPiBBZGQgVEVHUkEyMF9DTEtfTk9SIHRvIGluaXQgdGFiZWwg YW5kIHNldCBkZWZhdWx0IHJhdGUgdG8gOTIgTUh6DQo+IHdoaWNoDQo+IGlzIG1heCByYXRlLg0K DQp0YWJsZQ0KDQo+IA0KPiBTaWduZWQtb2ZmLWJ5OiBNaXJ6YSBLcmFrIDxtaXJ6YS5rcmFrLVJl NUpRRWVRcWU4QXZ4dGl1TXd4M3dAcHVibGljLmcNCj4gbWFuZS5vcmc+DQo+IC0tLQ0KPiBDaGFu Z2VzIGluIHYyOg0KPiAtIG5vIGNoYW5nZXMNCj4gDQo+IMKgZHJpdmVycy9jbGsvdGVncmEvY2xr LXRlZ3JhMjAuYyB8IDEgKw0KPiDCoDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlvbigrKQ0KPiAN Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xrL3RlZ3JhL2Nsay10ZWdyYTIwLmMgYi9kcml2ZXJz L2Nsay90ZWdyYS9jbGstDQo+IHRlZ3JhMjAuYw0KPiBpbmRleCA4MzdlNWNiLi4xM2QzYjVhIDEw MDY0NA0KPiAtLS0gYS9kcml2ZXJzL2Nsay90ZWdyYS9jbGstdGVncmEyMC5jDQo+ICsrKyBiL2Ry aXZlcnMvY2xrL3RlZ3JhL2Nsay10ZWdyYTIwLmMNCj4gQEAgLTEwNDcsNiArMTA0Nyw3IEBAIHN0 YXRpYyBzdHJ1Y3QgdGVncmFfY2xrX2luaXRfdGFibGUgaW5pdF90YWJsZVtdDQo+IF9faW5pdGRh dGEgPSB7DQo+IMKgCXsgVEVHUkEyMF9DTEtfU0RNTUMzLCBURUdSQTIwX0NMS19QTExfUCwgNDgw MDAwMDAsIDAgfSwNCj4gwqAJeyBURUdSQTIwX0NMS19TRE1NQzQsIFRFR1JBMjBfQ0xLX1BMTF9Q LCA0ODAwMDAwMCwgMCB9LA0KPiDCoAl7IFRFR1JBMjBfQ0xLX1NQSSwgVEVHUkEyMF9DTEtfUExM X1AsIDIwMDAwMDAwLCAwIH0sDQo+ICsJeyBURUdSQTIwX0NMS19OT1IsIFRFR1JBMjBfQ0xLX1BM TF9QLCA5MjAwMDAwMCwgMCB9LA0KDQpJJ20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6 IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRvIHRoZSBUZWdyYSAyDQpJbnRlcmZhY2UgRGVzaWduIEd1 aWRlIHVwIHRvIDEzMyBNSHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KDQo+IA0KPiDC oAl7IFRFR1JBMjBfQ0xLX1NCQzEsIFRFR1JBMjBfQ0xLX1BMTF9QLCAxMDAwMDAwMDAsIDAgfSwN Cj4gwqAJeyBURUdSQTIwX0NMS19TQkMyLCBURUdSQTIwX0NMS19QTExfUCwgMTAwMDAwMDAwLCAw IH0sDQo+IMKgCXsgVEVHUkEyMF9DTEtfU0JDMywgVEVHUkEyMF9DTEtfUExMX1AsIDEwMDAwMDAw MCwgMCB9LA0KPiAtLQ0KPiAyLjEuNA== ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] 2016-08-31 7:15 ` [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Marcel Ziswiler @ 2016-08-31 9:47 ` Mirza Krak 2016-08-31 11:28 ` Marcel Ziswiler 0 siblings, 1 reply; 3+ messages in thread From: Mirza Krak @ 2016-08-31 9:47 UTC (permalink / raw) To: Marcel Ziswiler Cc: jonathanh@nvidia.com, swarren@wwwdotorg.org, thierry.reding@gmail.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mturquette@baylibre.com, pgaikwad@nvidia.com, linux@armlinux.org.uk, devicetree@vger.kernel.org, gnurou@gmail.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, pdeschrijver@nvidia.com, sboyd@codeaurora.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, mchourasia 2016-08-31 9:15 GMT+02:00 Marcel Ziswiler <marcel.ziswiler@toradex.com>: > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> >> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> >> >> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz >> which >> is max rate. > > table ACK > >> >> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.g >> mane.org> >> --- >> Changes in v2: >> - no changes >> >> drivers/clk/tegra/clk-tegra20.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk- >> tegra20.c >> index 837e5cb..13d3b5a 100644 >> --- a/drivers/clk/tegra/clk-tegra20.c >> +++ b/drivers/clk/tegra/clk-tegra20.c >> @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] >> __initdata = { >> { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, >> { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, >> { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, >> + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 }, > > I'm just curious where that 92 MHz came from. According to the Tegra 2 > Interface Design Guide up to 133 MHz should actually be possible. The maximum rates for both T20 and T30 are values that are set as maximum in the downstream L4T kernel. In tegra2_clocks.c: PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ And in tegra3_clocks.c PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ I looked up the commit in the downstream kernel that added the "nor" clock, it does not mention reason behind the maximal rates. Author was Manoj Chourasia, added him to CC. I actually do not have the Tegra2 Interface Design Guide, do not know if I can get access to it. Best Regards Mirza ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] 2016-08-31 9:47 ` Mirza Krak @ 2016-08-31 11:28 ` Marcel Ziswiler 0 siblings, 0 replies; 3+ messages in thread From: Marcel Ziswiler @ 2016-08-31 11:28 UTC (permalink / raw) To: mirza.krak@gmail.com Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, jonathanh@nvidia.com, mturquette@baylibre.com, pgaikwad@nvidia.com, linux@armlinux.org.uk, devicetree@vger.kernel.org, gnurou@gmail.com, mchourasia@nvidia.com, thierry.reding@gmail.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, pdeschrijver@nvidia.com, sboyd@codeaurora.org, linux-tegra@vger.kernel.org, swarren@wwwdotorg.org, linux-clk@vger.kernel.org T24gV2VkLCAyMDE2LTA4LTMxIGF0IDExOjQ3ICswMjAwLCBNaXJ6YSBLcmFrIHdyb3RlOg0KPiBJ J20ganVzdCBjdXJpb3VzIHdoZXJlIHRoYXQgOTIgTUh6IGNhbWUgZnJvbS4gQWNjb3JkaW5nIHRv IHRoZQ0KPiA+IFRlZ3JhIDINCj4gPiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlIHVwIHRvIDEzMyBN SHogc2hvdWxkIGFjdHVhbGx5IGJlIHBvc3NpYmxlLg0KPiBUaGUgbWF4aW11bSByYXRlcyBmb3Ig Ym90aCBUMjAgYW5kIFQzMCBhcmUgdmFsdWVzIHRoYXQgYXJlIHNldCBhcw0KPiBtYXhpbXVtIGlu IHRoZSBkb3duc3RyZWFtIEw0VCBrZXJuZWwuDQo+IA0KPiBJbiB0ZWdyYTJfY2xvY2tzLmM6DQo+ IFBFUklQSF9DTEsoIm5vciIsICJ0ZWdyYS1ub3IiLCBOVUxMLCA0MiwgMHgxZDAsIDB4MzFFLCA5 MjAwMDAwMCwNCj4gbXV4X3BsbHBfcGxsY19wbGxtX2Nsa20sIE1VWCB8IERJVl9VNzEpLCAvKiBy ZXF1aXJlcyBtaW4gdm9sdGFnZSAqLw0KPiANCj4gQW5kIGluIHRlZ3JhM19jbG9ja3MuYw0KPiBQ RVJJUEhfQ0xLKCJub3IiLCAidGVncmEtbm9yIiwgTlVMTCwgNDIsIDB4MWQwLCAxMjcwMDAwMDAs DQo+IG11eF9wbGxwX3BsbGNfcGxsbV9jbGttLCBNVVggfCBESVZfVTcxKSwgLyogcmVxdWlyZXMg bWluIHZvbHRhZ2UgKi8NCj4gDQo+IEkgbG9va2VkIHVwIHRoZSBjb21taXQgaW4gdGhlIGRvd25z dHJlYW0ga2VybmVsIHRoYXQgYWRkZWQgdGhlICJub3IiDQo+IGNsb2NrLCBpdCBkb2VzIG5vdCBt ZW50aW9uIHJlYXNvbiBiZWhpbmQgdGhlIG1heGltYWwgcmF0ZXMuIEF1dGhvcg0KPiB3YXMNCj4g TWFub2ogQ2hvdXJhc2lhLCBhZGRlZCBoaW0gdG8gQ0MuDQoNCkxldCdzIHNlZSB3aGV0aGVyIHdl IGRvIGdldCBhbnkgZmVlZGJhY2sgZnJvbSBoaW0uDQoNCk5vbmV0aGVsZXNzIGl0IG1heSBiZSBn b29kIHRvIGFkZCB0aGlzIGluZm9ybWF0aW9uIHRvIHRoZSBjb21taXQNCm1lc3NhZ2Ugc28gc2hv dWxkIHNvbWVib2R5IGV2ZXIgZmVlbCB0aGUgc2FtZSBjdXJpb3NpdHkgbGlrZSBJIGRpZCBoZQ0K d291bGQgYXQgbGVhc3Qga25vdyB3aGVyZSBpdCBpbml0aWFsbHkgY2FtZSBmcm9tLg0KDQo+IEkg YWN0dWFsbHkgZG8gbm90IGhhdmUgdGhlIFRlZ3JhMiBJbnRlcmZhY2UgRGVzaWduIEd1aWRlLCBk byBub3Qga25vdw0KPiBpZiBJIGNhbiBnZXQgYWNjZXNzIHRvIGl0Lg0KDQpJIGd1ZXNzIHRoYXQg b25lIGlzIG9ubHkgYWNjZXNzaWJsZSB1bmRlciBOREEuIFdlIGNvdWxkIG9mIGNvdXJzZSB0cnkN CnRvIGdldCBvbmUgaW4gcGxhY2UgZm9yIHlvdSBidXQgSSBjYW4ndCBwcm9taXNlIHlvdSBhbnl0 aGluZy4NCg0KPiBCZXN0IFJlZ2FyZHMNCj4gTWlyemENCg0KVGhhbmtzLCBNaXJ6YQ== ^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <1472569308.5703.22.camel@toradex.com>
2016-08-31 7:15 ` [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Marcel Ziswiler
2016-08-31 9:47 ` Mirza Krak
2016-08-31 11:28 ` Marcel Ziswiler
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