Re: [PATCH 08/13] clk: renesas: r8a77990: Correct parent clock of DU

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

Hi Geert,

Thank you for the patch.

On Thursday, 29 November 2018 12:50:03 EET Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
> of the DU module clocks on R-Car E3 is S1D1.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
>  drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> b/drivers/clk/renesas/r8a77990-cpg-mssr.c index
> 9eb80180eea0b1a6..9a278c75c918cfa8 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -183,8 +183,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[]
> __initconst = { DEF_MOD("ehci0",		 703,	R8A77990_CLK_S3D4),
>  	DEF_MOD("hsusb",		 704,	R8A77990_CLK_S3D4),
>  	DEF_MOD("csi40",		 716,	R8A77990_CLK_CSI0),
> -	DEF_MOD("du1",			 723,	R8A77990_CLK_S2D1),
> -	DEF_MOD("du0",			 724,	R8A77990_CLK_S2D1),
> +	DEF_MOD("du1",			 723,	R8A77990_CLK_S1D1),
> +	DEF_MOD("du0",			 724,	R8A77990_CLK_S1D1),
>  	DEF_MOD("lvds",			 727,	R8A77990_CLK_S2D1),
> 
>  	DEF_MOD("vin5",			 806,	R8A77990_CLK_S1D2),

-- 
Regards,

Laurent Pinchart